9-325; Rev ; /98 Low-oltage, Phase-Reversal General Description The low-voltage, CMOS analog IC is configured as a phase-reversal switch and optimized for highspeed applications such as chopper amplifiers. It operates from a +2.7 to +2 single supply or from ±2.7 to ±6 dual supplies. On-resistance (Ω max) is matched between switches to 7Ω (max). Each switch can handle Rail-to-Rail analog signals. The leakage current is only.5n at and 2n at +85 C. ll digital inputs have.8 to 2.4 logic thresholds, ensuring both TTL- and CMOS-logic compatibility. For higher voltage operation, see the M4526/ M4527 data sheet. Features 5pC (max) Charge Injection Ω Signal Paths with ±5 Supplies Rail-to-Rail Signal Handling Transition Time <ns with ±5 Supplies.µ (max) Current Consumption >2k ESD Protection per Method 35.7 TTL/CMOS-Compatible Input Small Packages: 8-Pin SO, DIP, and µm pplications Chopper-Stabilized mplifiers alanced Modulators/Demodulators Data cquisition Test Equipment udio-signal Routing Ordering Information PRT TEMP. RNGE P-PCKGE CP CS CU C to +7 C C to +7 C C to +7 C 8 Plastic DIP 8 SO 8 µm C/D C to +7 C Dice* EP -4 C to +85 C 8 Plastic DIP ES -4 C to +85 C 8 SO EU -4 C to +85 C 8 µm *Contact factory for availability. Pin Configuration/Functional Diagram/Truth Table TOP IEW 8 2 7 TRUTH TLE 3 4 6 5 O DIP/SO/µM SWITCH POSITIONS SHOWN WITH = LOW Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. Maxim Integrated Products For free samples & the latest literature: http://www.maxim-ic.com, or phone -8-998-88. For small orders, phone 48-737-76 ext. 3468.
SOLUTE MIMUM RTGS (oltages Referenced to )...-.3 to 3...-3 to.3 to...-.3 to 3 ll Other Pins (Note )...( -.3) to ( +.3) Continuous Current into ny Terminal...±2m Peak Current into ny Terminal (pulsed at ms, % duty cycle)...±5m ESD per Method 35.7...>2 Continuous Power Dissipation (T = +7 C) (Note 2) Plastic DIP (derate 9.9mW/ C above +7 C)...727mW SO (derate 5.88mW/ C above +7 C)...47mW µm (derate 4.mW/ C above +7 C)...33mW Operating Temperature Ranges C... C to +7 C E...-4 C to +85 C Storage Temperature Range...-65 C to +5 C Lead Temperature (soldering, sec)...+3 C Note : Signals on,,,, or exceeding or are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: ll leads are soldered or welded to PC boards. Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICL CHRCTERISTICS: ±5 Dual Supplies ( = 5, = -5, H = 2.4, L =.8, T = T M to T M, unless otherwise noted. Typical values are at T =.) PRMETER SMOL CONDITIONS T M TP M (Note 3) UNITS NLOG SWITCH nalog-signal Range,,, (Note 4) -, -, -, - On-Resistance R ON = = ±3, I = I = m 7 3 Ω -, -, -, - On-Resistance Match (Note 5) R ON = = ±3, I = I = m 3 7 9 Ω -, -, -, - On-Resistance Flatness (Note 6) R FLT(ON) = = 3,, -3; I = I = m 9 5 7 Ω -, - Leakage Current (Note 7) I, I, I, I = 5.5; = -5.5; =, 3; = ±4.5; = +4.5 -.5..5-2 2 n LOGIC PUT Input Logic Threshold High H.6 2.4 Input Logic Threshold Low L.8.6 Input Current Logic High or Low I H, I L _ =.8 or 2.4 -.3 µ SWITCH DNMIC CHRCTERISTICS Transition Time t TRNS = = ±3, = 5, = -5, R L = 3Ω, Figure 3 7 25 ns reak-efore-make Time Delay t M = = ±3, = 5, = -5, R L = 3Ω, Figure 4 2 ns Charge Injection (Note 4) Q C L =.nf, or =, Figure 5 5 pc -, -, -, - Capacitance C ON = =, f = MHz, Figure 6 3 pf -, -, -, - Isolation (Note 8) ISO R L = 5Ω, C L = 5pF, f = MHz, = = RMS, Figure 7-68 d 2
ELECTRICL CHRCTERISTICS: ±5 Dual Supplies (continued) ( = 5, = -5, H = 2.4, L =.8, T = T M to T M, unless otherwise noted. Typical values are at T =.) PRMETER POWER SUPPL Power-Supply Range Supply Current Supply Current SMOL, I+ I- = or = or M TP M CONDITIONS T UNITS (Note 3) ±2.7 ±6 - - - - µ µ ELECTRICL CHRCTERISTICS: +5 Single Supply ( = 5, =, H = 2.4, L =.8, T = T M to T M, unless otherwise noted. Typical values are at T =.) nalog-signal Range -, -, -, - On-Resistance -, - Leakage Current (Note 9) Transition Time PRMETER NLOG SWITCH -, -, -, - On-Resistance Match (Note 5) LOGIC PUT Input Logic Threshold High Input Logic Threshold Low Input Current Logic High or Low reak-efore-make Time Delay Charge Injection -, -, -, - Capacitance -, -, -, - Isolation (Note 8) SMOL,,, R ON R ON I, I, I, I H L I H, I L SWITCH DNMIC CHRCTERISTICS (Note 4) POWER SUPPL Power-Supply Range Supply Current t TRNS t M Q C OFF ISO I+ (Note 4) CONDITIONS = = 3, I = I = m = = 3, I = I = m = 5.5; =, 3; = 4.5, ; =, 4.5 _ =.8 or 2.4 = = 3, = 5, R L = 3Ω, Figure 3 = = 3, = 5, R L = 3Ω, Figure 4 C L =.nf, or =, Figure 5 = =, f = MHz, Figure 6 R L = 5Ω, C L = 5pF, f = MHz, = = RMS, Figure 7 = or T 2 75 2 5 2 -.5..5 M TP M (Note 3) -2 2.8.6 2.6 2.4 -.3 75-7 2.5 5 7 UNITS Ω Ω n µ ns ns pc pf d 2.7 2 - - µ 3
ELECTRICL CHRCTERISTICS: +3 Single Supply ( = 2.7 to 3.6, =, H = 2.4, L =.6, T = T M to T M, unless otherwise noted. Typical values are at T =.) nalog-signal Range -, -, -, - On-Resistance LOGIC PUT Transition Time PRMETER NLOG SWITCH Input Logic Threshold High reak-efore-make Time Delay Charge Injection Power-Supply Range Supply Current,,, R ON H (Note 4) = 3, = =.5, I = I =.m = 3 Input Logic Threshold Low L = 3 Input Current Logic High I H, _ = or or Low I L SWITCH DNMIC CHRCTERISTICS (Note 4) POWER SUPPL SMOL t TRNS t M Q, I+ CONDITIONS =.5, =, = 3, =, R L = kω, Figure 3 =.5, =, = 3, =, R L = kω, Figure 4 C L =.nf, or =, Figure 5 = or T 5 2.7 2 - M TP M (Note 3).6.9 2 5 25 9.9 2.4 -.3 5 4 5 - UNITS Ω µ ns ns pc µ Note 3: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 4: Guaranteed by design. Note 5: R ON = R ON(M) - R ON(M). Note 6: Resistance flatness is defined as the difference between the maximum and the minimum value of on-resistance as measured over the specified analog-signal range. Note 7: Leakage parameters are % tested at maximum rated hot temperature and guaranteed by correlation at. Note 8: Off isolation = 2log [( or ) / ( or )], or = output, or = input to off switch. Note 9: Leakage testing for single-supply operation guaranteed by testing with dual supplies. 4
Typical Operating Characteristics ( = 5, = -5, =, T =, unless otherwise noted.) RON (Ω) ON-RESISTNCE vs., (DUL SUPPLIES) = 2.7 = -2.7 = 3.3 = -3.3 =.2 = -.2 = 5 = -5 = 2 = -2 - RON (Ω) 4 2 8 6 4 2 ON-RESISTNCE vs.,, ND TEMPERTURE (DUL SUPPLIES) T = +25 C T = +85 C T = -4 C T = T = +7 C T = -55 C -2 RON (Ω) ON-RESISTNCE vs., (SGLE SUPPL) = 2 = 2.7 = 3.3 = 5 = 7.5 = = -3-5 -4-3 -2-2 3 4 5, () -5-4 -3-2 - 2 3 4 5, () 2 3 4 5 6 7 8 9, () 2 8 6 4 ON-RESISTNCE vs.,, ND TEMPERTURE (SGLE SUPPL) T = +25 C T = +7 C T = +85 C -4, LEKGE vs. TEMPERTURE -5 5 CHRGE JECTION, CHRGE- JECTION MTCHG vs., Q MTCHG -6 RON (Ω) Q (pc) 2 8 6 4 2 4 2-2 -4 = 5 = T = T = -4 C T = -55 C 2 3 4 5, () CHRGE JECTION, CHRGE- JECTION MTCHG vs., (+5 SUPPL) Q MTCHG Q -7 LEKGE (p) Q (pc)... 4 3 2-55 -25 5 35 65 95 25 TEMPERTURE ( C) CHRGE JECTION, CHRGE- JECTION MTCHG vs., (+3 SUPPL) Q Q = 3 = -8 Q (pc) ttrns (ns) -5 - -5-2 -25 25 2 5 = 5 = 5-5 -4-3 -2-2 3 4 5, () Q TRNSITION TIME vs. SUPPL OLTGE SGLE SUPPL Q -9-6 -8 - = 5 = Q 2 3 4 5, () - -2-3 Q MTCHG 2 3 4 5, () 5 DUL SUPPLIES 2 4 6 8 SUPPL OLTGE () 5
Typical Operating Characteristics (continued) ( = 5, = -5, =, T =, unless otherwise noted.) ttrns (ns) 25 2 5 5 TRNSITION TIME vs. TEMPERTURE +2.7 SGLE SUPPL +5 SGLE SUPPL ±5 DUL SUPPLIES -55-25 5 35 65 95 25 TEMPERTURE ( C) - I+, I () - -2-3 -4-5 -6-7 -8-9 - - SUPPL CURRENT ND GROUND CURRENT vs. PUT OLTGE = 5 = 2 = 2 3 4 5 6 7 8 9 2 () - LOSS (d) FREQUENC RESPONSE 8-2 - ON LOSS 5-2 2-3 OFF ISOLTION 9-4 6-5 3-6 ON PHSE -7-3 -8-6 -9-9 = 5 - = -5-2 - 5Ω ND OUT -5-2 -8. FREQUENC (MHz) PHSE (DEGREES) THD (%). TOTL HRMONIC DISTORTION vs. FREQUENC = 5 = -5 6Ω ND OUT M4526/27 TOC-3 LOGIC-LEEL THRESHOLD () 3. 2.5 2..5..5 LOGIC-LEEL THRESHOLD vs. SUPPL OLTGE -4. k k 2k FREQUENC (Hz) 2 3 4 5 6 7 8 9 2 () 6
Pin Description P NME 2 3 4 5 FUNCTION nalog-switch Input Terminal. Connected to when is low; connected to when is high. nalog-switch Input Terminal. Connected to when is low; connected to when is high. Ground. Connect to digital ground. (nalog signals have no ground reference; they are limited to and.) Logic-Level Control Inputs (see Truth Table) Negative nalog Supply-oltage Input. Connect to for singlesupply operation. 6 nalog-switch Output Terminal 7 nalog-switch Output Terminal 8 Positive nalog/digital Supply-oltage Input. Internally connected to substrate. Note: Pins,,, and are identical and interchangeable. ny may be considered as an input or output; signals pass equally well in either direction. However, C symmetry is best when and are the inputs and and are the outputs. Reduce C balance in critical applications by using and or and as the input, and and or and as the output. Detailed Description The is a phase-reversal analog switch consisting of two normally open and two normally closed CMOS analog switches arranged in a bridge configuration. nalog signals are put into two input pins and taken out of two output pins. logic-level signal controls whether the input signal is routed through normally or inverted. low-resistance DC path goes from inputs to outputs at all times, yet isolation between the two signal paths is excellent. nalog signals range from to. These parts are characterized and optimized with ±5 supplies, and can operate from a single supply. The is designed for DC and low-frequencysignal phase-reversal applications, such as chopper amplifiers, modulator/demodulators, and self-zeroing or self-calibrating circuits. Unlike conventional CMOS switches externally wired in a bridge configuration, both DC and C symmetry are optimized with a small 8-pin configuration that allows simple board layout and isolation of logic signals from analog signals. Power-Supply Considerations Overview The s construction is typical of most CMOS analog switches. It has three supply pins:,, and. and drive the internal CMOS switches and set the analog-voltage limits on any switch. Reverse ESD-protection diodes are internally connected between each analog-signal pin and both and. One of these diodes conducts if any analog signal exceeds or. irtually all of the analog leakage current is through the ESD diodes to or. lthough the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages vary as the signal varies. The difference in the two diode leakages from the signal path to the and pins constitutes the analog-signal-path leakage current. ll analog leakage current flows to the supply terminals, not to the other switch terminal. This explains how both sides of a given switch can show leakage currents of either the same or opposite polarity. There is no connection between the analog-signal paths and. The analog-signal paths consist of an N-channel and P-channel MOSFET with their sources and drains paralleled and their gates driven out-ofphase to and by the logic-level translators. and power the internal logic and logic-level translator and set the input logic threshold. The logiclevel translator converts the logic levels to switched and signals to drive the analog switches gates. This drive signal is the only connection between and the analog supplies. and have ESD-protection diodes to. The logic-level input has ESD protection to and, but not to, so the logic signal can go below (as low as ) when bipolar supplies are used. Increasing has no effect on the logic-level thresholds, but it does increase the drive to the internal P-channel switches, reducing overall switch on-resistance. also sets the negative limit of the analog-signal voltage. The logic-level input pin () has ESD-protection diodes to and but not to, so it can be safely driven to and. The logic-level threshold () is CMOS/ TTL compatible when is between 4.5 and 2 (see Typical Operating Characteristics). 7
ipolar Supplies The operates with bipolar supplies between ±2.7 and ±6.. The and supplies need not be symmetrical, but their sum cannot exceed the 3 absolute maximum rating (see bsolute Maximum Ratings). Single Supply The operates from a single +2.7 to +2 supply when is connected to. Observe all of the bipolar precautions when operating from a single supply. pplications Information The is designed for DC and low-frequencysignal phase-reversal applications. oth DC and C symmetry are optimized for use with ±5 supplies. Signal Phase/Polarity Reversal The can reverse the phase or polarity of a pair of signals that are out-of-phase and balanced to ground. This is done by routing signals through the and, under control of, reversing the two signals paths inside the switch before sending out to a balanced output. Figure shows a typical example. The cannot reverse the phase or polarity of a single grounded signal, as can be done with an inverting op amp or transformer. alanced Modulator/Demodulator The can be used as a balanced modulator/ demodulator at carrier frequencies up to khz (Figure 2). Higher frequencies are possible, but as frequency increases, small imbalances in the s internal capacitance and resistance gradually impair performance. Similarly, imbalances in external circuit capacitance and resistance to reduce overall carrier suppression. The carrier is applied as a logic-level square wave to. (Note that this voltage can go as negative as.) For best carrier suppression, the power-supply voltages should be equal, the square wave should have a precise 5% duty cycle, and both the input and output signals should be symmetrical around ground. ypass and to with.µf ceramic capacitors, as close to the IC pins as possible. In critical applications, carrier suppression can be optimized by trimming duty cycle, DC bias around, or external source and load capacitance. In signal lines, balancing both capacitance and resistance to produces the best carrier suppression. Transformer coupling of input and output signals provides the best isolation and carrier suppression. Transformers can also provide signal filtering, impedance matching, or low-noise voltage gain. Use a center-tapped transformer or high-resistance voltage divider to provide a DC path to on either the input or output signal. This ensures a DC path to and symmetrical operation of the internal switches. PUTS PUTS OUTPUTS OUTPUTS LOGIC LOW LOGIC HIGH TRUTH TLE O Figure. Typical pplication Circuits 8
NPUT MODULTOR/DEMODULTOR CIRCUIT OUTPUT LOGIC (CRRIER) TIME WEFORMS LOWER SIDEND OUTPUT SPECTRUM UPPER SIDEND SUPPRESSED CRRIER MPLITUDE LOGIC (CRRIER) FREQUENC - (OUTPUT) Figure 2. alanced Modulator/Demodulator Test Circuits/Timing Diagrams 5Ω +3-3 5% 3Ω 35pF OUT OUT 9% 9% t TRNS t TRNS IS CONNECTED TO () FOR SGLE-SUPPL OPERTION. Figure 3. ddress Transition Time 9
Test Circuits/Timing Diagrams (continued) +3 5% t F < 5ns t R < 5ns 5Ω OR OUT OUT 9% 3Ω 35pF t M IS CONNECTED TO () FOR SGLE-SUPPL OPERTION. Figure 4. reak-efore-make Interval OR OR N.C. OR OR OUT 5Ω C L pf OUT OUT OUT IS THE MESURED OLTGE DUE TO CHRGE TRNSFER ERROR Q WHEN THE CHNNEL TURNS OFF. IS CONNECTED TO () FOR SGLE-SUPPL OPERTION. Q = OUT x C L Figure 5. Charge Injection
Test Circuits/Timing Diagrams (continued) SWITCH SELECT MHz CPCITNCE NLZER Figure 6.,,, Capacitance nf, 5Ω NETWORK NLZER 5Ω OFF ISOLTION = 2log ON LOSS = 2log OUT OUT SWITCH SELECT, OUT MES. 5Ω 5Ω REF nf MESUREMENTS RE STNDRDIZED GST SHORT T SOCKET TERMLS. OFF ISOLTION IS MESURED ETWEEN, ND "OFF", TERML. ON LOSS IS MESURED ETWEEN, ND "ON", TERML. SIGNL DIRECTION THROUGH SWITCH IS REERSED; WORST LUES RE RECORDED. IS CONNECTED TO () FOR SGLE-SUPPL OPERTION. Figure 7. Off Isolation and On Loss
Chip Topography TRNSISTOR COUNT: 4 SUSTRTE IS TERNLL CONNECTED TO.54" (.37mm) N 8LUMD.EPS.38 (.97mm) Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 2 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, C 9486 48-737-76 998 Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products.