PART MAX4144ESD MAX4146ESD. Typical Application Circuit. R t IN- IN+ TWISTED-PAIR-TO-COAX CABLE CONVERTER

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1 9-47; Rev ; 9/9 EVALUATION KIT AVAILABLE General Description The / differential line receivers offer unparalleled high-speed performance. Utilizing a threeop-amp instrumentation amplifier architecture, these ICs have fully symmetrical differential inputs and a single-ended output. The devices drive ±3.V into a Ω load. The is internally set for a V/V closedloop gain, while the can be externally set to gains from V/V to V/V. These amplifiers use laser-trimmed, matched thin-film resistors to deliver a 7dB CMR at. Using current-feedback techniques, the achieves a 3 bandwidth and V/µs slew rate, while the maintains a 7 bandwidth at G = V/V and an 8V/µs slew rate. Excellent differential gain/phase and noise specifications make these amplifiers ideal in a variety of video and RF signal-processing applications. For a complete differential transmission link, use the / with the MAX447 differential line driver (see the MAX447 data sheet for more information). Applications Differential-to-Single-Ended Conversion Twisted-Pair-to-Coax Converter High-Speed Instrumentation Amplifier Data Acquisition Medical Instrumentation High-Speed Differential Features : V/V Fixed Gain 3 Bandwidth V/µs Slew Rate 7dB CMR at -9 dbc SFDR (f C = khz) Low Differential Gain/Phase:.3%/.3 8µA Shutdown : External Gain Selection 7 Bandwidth (A V = V/V) 8V/µs Slew Rate 9dB CMR at -8dBc SFDR (f C = khz) Very Low Noise: 3.nV/ Hz (G = V/V) 8µA Shutdown Ordering Information PART ESD ESD TEMP. RANGE -4 C to +8 C -4 C to +8 C Pin Configurations appear on last page. PPACKAGE 4 SO 4 SO / Typical Application Circuit SENSE+ MAX447 - SENSE- + R t R t R t R t SENSE REF 7Ω 7Ω COAX 7Ω V TWISTED-PAIR-TO-COAX CABLE CONVERTER Maxim Integrated Products For free samples & the latest literature: or phone

2 / ABSOLUTE MAXIMUM RATINGS Supply Voltage (V CC to V EE )...V Voltage on IN_, SHDN, REF,, SENSE, RG_...(V CC +.3V) to (V EE -.3V) Continuous Power Dissipation (T A = +7 C) SO (derate 8.33mW/ C above +7 C)...7mW Short-Circuit Duration to Ground...sec Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Input Current (IN_, RG_)...±mA Output Current...±mA Operating Temperature Range MAX44_ESD...-4 C to +8 C Storage Temperature Range...- C to + C Lead Temperature (soldering, sec)...+3 C (V CC = +V, V EE = -V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = + C.) PARAMETER Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Noise Input Current Noise Input Capacitance Differential Input Resistance Differential Input Voltage Range Common-Mode Input Voltage Range Gain A V -V V +V, R L = Ω + (4kΩ / R G) -V V. Gain Error +V, AV = V/V. RL = Ω AV = V/V. Gain Drift Common-Mode Rejection Power-Supply Rejection Quiescent Supply Current Shutdown Supply Current Output Voltage Swing Output Current Drive SYMBOL V OS TCV OS I B I OS e n i n C IN V CM CMR PSR I SY I SHDN V I V = V, R L = V = V, R L = V C = ±.8V V S = ±4.V to ±.V R L = R L = Shutdown Output Impedance V SHDN.V R L = R L = Ω V = ±.7V CONDITIONS V = V, R L =, V IN = -V OS V = V, R L =, V IN = -V OS f = f = R L = Ω R L = -V V +V, R L = Ω C T A 8 C -4 C T A < C C T A 8 C -4 C T A < C MIN TYP MAX UNITS. 8 mv µv/ C 9 µa.. µa. + (3 / G) nv/ Hz.7 pa/ Hz pf MΩ / G 3. / G V ±3.4 ±3.8 ±3. ± G.8. V V/V % ppm/ C db db ma ma kω V ma

3 DC ELECTRICAL CHARACTERISTICS (continued) (V CC = +V, V EE = -V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = + C.) SHDN High Threshold SHDN Low Threshold SHDN Input Current (Note ) AC ELECTRICAL CHARACTERISTICS (V CC = +V, V EE = -V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = + C.) PARAMETER -3dB Bandwidth.dB Bandwidth Common-Mode Rejection Slew Rate Settling Time Differential Gain PARAMETER Full-Power Bandwidth Differential Phase Spurious-Free Dynamic Range SYMBOL BW (-3dB) FPBW BW (.db) CMR SR t s DG DP SFDR SYMBOL V IH V IL I SHDN V SHDN.8V V SHDN.V V.V RMS V = Vp-p V.V RMS f = -V V +V -V V +V f = 3.8, R L = Ω f = 3.8, R L = Ω f C = khz, V = Vp-p, R L = Ω f C =, V = Vp-p, R L = Ω CONDITIONS CONDITIONS to.% to.% MIN TYP MAX 3 A VCL = V/V 7 A VCL = V/V 3 A VCL = V/V 7 A VCL = V/V A V = V/V A V = V/V A V = V/V A V = V/V MIN TYP MAX ±. ± UNITS V V µa UNITS db V/µs ns % degrees dbc / Note : The negative sign indicates that current is flowing out of the SHDN pin. Note : Differential gain and phase are tested using a modulated ramp, IRE (.74V). 3

4 High-Speed Differential / Typical Operating Characteristics (T A = + C, R L = Ω, unless otherwise noted.) SMALL-SIGNAL GAIN vs. FREQUENCY (A V = +) V = mv RMS k M M M G / TOC- SMALL-SIGNAL GAIN vs. FREQUENCY (A V = +) V = mv RMS k M M M G / TOC SMALL-SIGNAL GAIN vs. FREQUENCY (A V = +) V = mv RMS 3 k M M M G / LARGE-SIGNAL GAIN vs. FREQUENCY(A V = +) V = Vp-p / LARGE-SIGNAL GAIN vs. FREQUENCY (A V = +) V = Vp-p / LARGE-SIGNAL GAIN vs. FREQUENCY (A V = +) V = Vp-p / k M M M G k M M M G 33 k M M M G VOLTAGE (mv/div) IN SMALL-SIGNAL PULSE RESPONSE (A V = +) TOC-7 VOLTAGE (mv/div) IN SMALL-SIGNAL PULSE RESPONSE (A V = +) TOC-9 VOLTAGE IN mv/div mv/div SMALL-SIGNAL PULSE RESPONSE (A V = +) TOC-8 TIME (ns/div) TIME (ns/div) TIME (ns/div) 4

5 High-Speed Differential Typical Operating Characteristics (continued) (T A = + C, R L = Ω, unless otherwise noted.) VOLTAGE (mv/div) IN LARGE-SIGNAL PULSE RESPONSE (A V = +) TIME (ns/div) TOC- VOLTAGE (mv/div) IN LARGE-SIGNAL PULSE RESPONSE (A V = +) TIME (ns/div) TOC- VOLTAGE IN mv/div mv/div LARGE-SIGNAL PULSE RESPONSE (A V = +) TIME (ns/div) TOC- / PUT IMPEDANCE (Ω) PUT IMPEDANCE vs. FREQUENCY. k M M M /44-7 PUT IMPEDANCE (Ω) PUT IMPEDANCE vs. FREQUENCY. k M M M /44-8 PHASE (deg) GAIN (%) DIFFERENTIAL GAIN AND PHASE A V = V/V IRE A V = V/V IRE / TOC- PHASE (deg) GAIN (%) DIFFERENTIAL GAIN AND PHASE A V = V/V IRE A V = V/V IRE / TOC- PUT SWING (VPEAK) PUT SWING vs. LOAD RESISTANCE LOAD (Ω) /44-9 PUT SWING (VPEAK) PUT SWING vs. LOAD RESISTANCE LOAD (Ω) /44-3

6 / Typical Operating Characteristics (continued) (T A = + C, R L = Ω, unless otherwise noted.) HARMONIC DISTORTION vs. FREQUENCY (A V = +) V = Vp-p R L = Ω ND HARMONIC - k M M / TOC HARMONIC DISTORTION vs. FREQUENCY (A V = +) V = Vp-p R L = Ω ND HARMONIC - k M M / TOC HARMONIC DISTORTION vs. FREQUENCY (A V = +) V = Vp-p ND HARMONIC - k M M / V = Vp-p HARMONIC DISTORTION vs. LOAD ND HARMONIC / HARMONIC DISTORTION vs. LOAD (A V = +) V = Vp-p - ND HARMONIC / HARMONIC DISTORTION vs. LOAD (A V = +) V = Vp-p ND HARMONIC / LOAD (Ω) LOAD (Ω) LOAD (Ω) HARMONIC DISTORTION vs. PUT SWING R L = Ω ND HARMONIC / HARMONIC DISTORTION vs. PUT SWING (A V = +) R L = Ω ND HARMONIC / HARMONIC DISTORTION vs. PUT SWING (A V = +) R L = Ω ND HARMONIC / PUT SWING (Vp-p) PUT SWING (Vp-p) PUT SWING (Vp-p)

7 Typical Operating Characteristics (continued) (T A = + C, R L = Ω, unless otherwise noted.) NOISE (nv/ Hz) VOLTAGE NOISE vs. FREQUENCY k k k M /44-3 NOISE (nv/ Hz) VOLTAGE NOISE vs. FREQUENCY (A V = +) k k k M /44-4 NOISE (nv/ Hz) VOLTAGE NOISE vs. FREQUENCY (A V = +) k k k M /44- / POWER-SUPPLY REJECTION (db) (A V = ) (A V = ) POWER-SUPPLY REJECTION vs. FREQUENCY 3 k M M M /44- CMR (db) CMR vs. FREQUENCY k M M M / TOC- CMR (db) CMR vs. FREQUENCY A V = V/V V CM = mv RMS k M M M / TOC- 7

8 / Pin Description PIN NAME, 7, 7 V EE Negative Power Supply. Connect to -V. Inverting Input 3,,,, No Connect. Not internally connected. 3 RG- 4 4 SHDN RG+ Non-Inverting Input for Gain-Set Resistor FUNCTION Inverting Input for Gain-Set Resistor. A gain-setting resistor (R G ) between RG+ and RG- sets the gain (in V/V) according to the following equation: G = + 4k Ω R G Logic Input for Shutdown Circuitry. A logic low enables the amplifier. A logic high disables the amplifier. Non-Inverting Input 8, 4 8, 4 V CC Positive Power Supply. Connect to +V. 9 9 REF Output Reference. Connect to ground for normal operation. Output 3 3 SENSE Output Sense. Connect to close to the pin for normal operation. Detailed Description The / differential line receivers feature 3 and 7 (A V = V/V) bandwidth, respectively, and 7dB and 9dB common-mode rejection (CMR) at. The parts feature a V/µs slew rate, and power dissipation is a mere mw. The is internally set for a V/V closed-loop gain, while the can be set to gains from V/V to V/V using a single resistor. The amplifiers are ideal as line receivers. They have fully symmetrical differential inputs and a single-ended output, and can drive ±3.V into a Ω load. The differential inputs make the / ideal for applications with high common-mode noise such as receiving T or XDSL transmissions over a twisted-pair cable. Excellent gain and phase, along with low noise, also suit them to video applications and RF signal processing. For a complete differential transmission link, use the / amplifiers with the MAX447 line driver, as shown in the Applications Information section. Applications Information Grounding, Bypassing, and PC Board Layout High-frequency design techniques must be followed when designing the PC board for the /. The printed circuit board should have at least two layers: the signal layer and the ground plane. Do not use wire-wrap boards they are too inductive. Do not use IC sockets they increase parasitic capacitance and inductance. Use surface-mount power-supply bypass capacitors instead of through-hole capacitors. Their shorter lead lengths reduce parasitic inductance, leading to superior high-frequency performance. Keep signal lines as short and as straight as possible. Do not make 9 turns; round all corners. The ground plane should be as free from voids as possible. 8

9 Output Short-Circuit Protection Under short-circuit conditions to ground, the output current is typically limited to ma. This level is low enough that a moderate-duration short to ground will not cause permanent damage to the chip. However, a short to either supply will significantly increase power dissipation, and will cause permanent damage. The high output current capability is an advantage in systems that transmit a signal to several loads. Input State Circuitry The / include internal protection circuitry that prevents damage to the precision input stage from large differential input voltages. This protection circuitry consists of five back-to-back Schottky protection diodes between and R G +, and and R G - (Figure ). The diodes limit the differential voltage applied to the amplifiers internal circuitry to no more than V F, where V F is the diode s forward voltage drop (about.4v at + C). For a large differential input voltage (exceeding 4V), the input bias current (at and ) increases according to the following equation: Input Current = ( ) V - V - VF RG High-Speed Differential The has an internal gain-setting resistor equal to.4kω. A differential input voltage as high as V will cause only 4.3mA to flow much less than the absolute maximum rating of ma. However, in the, R G can be as low as Ω. Under this condition, the absolute maximum input current rating might be exceeded if the differential input voltage exceeds.v (ma x Ω + V F ). In that case, Ω resistors can be placed at and to limit the current without degrading performance. Shutdown Mode The / can be put into low-power shutdown mode by bringing SHDN high. The amplifier output is high impedance in this mode; thus the impedance at is that of the feedback resistors (.4kΩ and kω, respectively, for the /). Setting Gain () The s gain is determined by a single external resistor, RG. The minimum gain is V/V (R G = open), and the maximum practical gain is V/V. The gain (in V/V) is given in the following equation: G = + 4k R G Ω / R G -.4k R G + (a) Figure. / Input Protection Circuit (b) 9

10 / Figure shows the connection for RG. RG might simply be a resistor, or it can be a complex pole-zero pair for filter and shaping applications (Figure 9). Use surfacemount gain-setting components to ensure stability. Using REF and SENSE The / have a REF pin (normally connected to ground) and a SENSE pin (normally connected to ). In some long-line applications, it may be desirable to connect SENSE and together at the load, instead of the typical connection at the part (Figure 3). This compensates for the long line s resistance, which otherwise leads to an IR voltage error. When using this technique, keep the sense lines impedance low to minimize gain errors. Also, keep capacitance low to maximize frequency response. The gain of the / output stage is approximated by the following equation: A = 7 Ω + RSENSE 7 Ω + R V REF + R R + 7 Ω + RREF + 7 Ω + RREF R + 7 Ω + RREF where RSENSE and RREF are the SENSE and REF trace impedances, respectively. R is 7Ω for the and 7Ω for the. 3 Additionally, mismatches in the SENSE and REF traces lead to common-mode gain errors. Common-mode gain is approximated by the following equation: A VCM = R REF - RSENSE R + 7 Substituting numbers for RREF and RSENSE into this equation, we can see that if changes in RREF and RSENSE are equal, CMR is not degraded. Driving Capacitive Loads The / provide maximum AC performance when driving no output load capacitance. This is the case when driving a correctly terminated transmission line (i.e., a back-terminated cable). In most amplifier circuits, driving large load capacitance increases the chance of oscillations. The amplifier s output impedance and the load capacitor combine to add a pole and excess phase to the loop response. If the pole s frequency is low enough and phase margin is degraded sufficiently, oscillations may occur. A second concern when driving capacitive loads results from the amplifier s output impedance, which looks inductive at high frequencies. This inductance forms an L-C resonant circuit with the capacitive load. This causes peaking in the frequency response and degrades the amplifier s phase margin. The / drive capacitive loads up to pf without oscillation. However, some peaking may occur in the frequency domain (Figure 4). R G 3 9 Figure. Connection of R G in SENSE REF Figure 3. Connection of SENSE and REF to a Remote Load R L C L = pf C L = pf - k M M M G C L = pf Figure 4. Small-Signal Response with Capacitative Load

11 To drive larger capacitance loads or to reduce ringing, add an isolation resistor between the amplifier s output and the load (Figure ). The value of R ISO depends on the circuit s gain and the capacitive load (Figures and 7). With higher capacitive values, bandwidth is dominated by the RC network formed by RISO and CL; the bandwidth of the amplifier itself is much higher. Also note that the isolation resistor forms a divider that decreases the voltage delivered to the load. R ISO CLOAD R LOAD Twisted-Pair Line Receiver The / are well suited as receivers in twisted-pair XDSL or NTSC/PAL video applications. The standard 4AWG telephone wire widely used in these applications is a lossy medium for high-frequency signals. The losses in NTSC video applications are almost db per, feet (Figure 8). Losses are higher at higher frequencies, contributing to severe pulse-edge rounding in digital applications. The nominal impedance of twisted pair telephone wire is Ω. ISOLATION RESISTANCE (Ω) A V = V/V / 4 CAPACITATIVE LOAD (pf) Figure. Addition of R ISO to Amplifier Output Figure 7. Isolation Resistance vs. Capacitative Load 3 ISOLATION RESISTANCE (Ω) CAPACITATIVE LOAD (pf) -3 k k M M Figure. Isolation Resistance vs. Capacitative Load Figure 8. Feet of AWG4 Twisted-Pair Telephone Cable (Gain vs. Frequency)

12 / The, with variable gain up to V/V, can be used to compensate for cable losses. In the circuit of Figure 8, the cable characteristics are such that the video-chroma frequency loss is almost db greater than the low-frequency loss. The losses can be compensated for by using the RC-shaping network (Figure 9). VIDEO INPUT 7Ω 7Ω V CC 8, 4 3 MAX447 9, 7.µF.µF ' Ω A Ω resistance and a pf capacitance shape the gain to inversely match the frequency of the feet of telephone cable. The differential gain and phase, using the circuit of Figure 8, is.% and.8, respectively. pf Ω V CC 8, , 7.µF 7Ω VIDEO PUT V EE.µF V EE Figure 9. Circuit for Transmitting NTSC/PAL Video Over Feet of Twisted-Pair Telephone Line Pin Configurations TOP VIEW V EE 4 V CC V EE 4 V CC R R SENSE 3 SENSE R R SENSE 3 SENSE 3 R f 3 R f SHDN 4 R G R f R SHDN 4 R f R R REF R REF 9 REF 9 REF V EE 7 8 V CC V EE 7 8 V CC SO SO Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA 948 (48) Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.