DTSHEET X1288 2-Wire RT Real Time lock/alendar/pu Supervisor wih EEPROM FN8102 Rev 3.00 FETURES Real Time lock/alendar Tracks ime in Hours, Minues, Seconds and Hundredhs of a Second Day of he Week, Day, Monh, and Year 2 Polled larms (Non-volaile) Seable on he Second, Minue, Hour, Day of he Week, Day, or Monh Repea Mode (periodic inerrups) Oscillaor ompensaion on hip Inernal feedback resisor and compensaion capaciors 64 posiion Digially onrolled Trim apacior 6 digial-frequency adjusmen seing o ±30ppm PU Supervisor Funcions Power-on Rese, Low Volage Sense Wachdog Timer (SW Selecable: 0.25s, 0.75s, 1.75s, off) Baery Swich or Super ap Inpu 32 x 8 Bis of EEPROM 128-Bye Page Wrie Mode 8 modes of Block Lock Proecion Single Bye Wrie apabiliy High Reliabiliy Daa Reenion: 100 years Endurance: 100,000 cycles per bye 2-Wire Inerface ineroperable wih I2* 400kHz daa ransfer rae Frequency Oupu (SW Selecable: Off, 1Hz, 100Hz, or 32.768kHz) Low Power MOS 1.25µ Operaing urren (Typical) Small Package Opions 16-Lead SOI and 14-Lead TSSOP Pb-Free Plus nneal vailable (RoHS omplian) PPLITIONS Uiliy Meers HV Equipmen udio/video omponens Se Top Box/Television Modems Nework Rouers, Hubs, Swiches, Bridges ellular Infrasrucure Equipmen Fixed Broadband Wireless Equipmen Pagers/PD POS Equipmen Tes Meers/Fixures Office uomaion (opiers, Fax) Home ppliances ompuer Producs Oher Indusrial/Medical/uomoive BLO DIGRM OS ompensaion X1 32.768kHz X2 PHZ/IRQ Selec Oscillaor Frequency Divider 1Hz Timer alendar Logic Time eeping Regisers (SRM) Baery Swich ircuiry V V B SL SD Serial Inerface Decoder onrol Decode Logic onrol/ Regisers (EEPROM) Saus Regisers (SRM) larm Mask ompare larm Regs (EEPROM) RESET 8 Wachdog Timer Low Volage Rese 256 EEPROM RRY FN8102 Rev 3.00 Page 1 of 27
PIN DESRIPTIONS 16 Ld SOI 14 Ld TSSOP X1 X2 RESET V SS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V V B PHZ/IRQ SL SD X1 X2 RESET V SS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V V B PHZ/IRQ SL SD = No inernal connecion Ordering Informaion PRT NUMBER PRT MRING V RNGE (V) V TRIP RNGE OPERTING TEMP RNGE ( ) PGE X1288S16-4.5* X1288S L 4.5 o 5.5 4.63V±112mV 0 o 70 16 Ld SOI X1288S16I-4.5* X1288S M -40 o +85 16 Ld SOI X1288V14-4.5* X1288V L 0 o 70 14 Ld TSSOP X1288V14Z-4.5* (Noe) X1288V ZL 0 o 70 14 Ld TSSOP (Pb-free) X1288V14I-4.5* X1288V M -40 o +85 14 Ld TSSOP X1288V14IZ-4.5* (Noe) X1288V ZM -40 o +85 14 Ld TSSOP (Pb-free) X1288S16* X1288S 4.38V±112mV 0 o 70 16 Ld SOI X1288S16I* X1288S I -40 o +85 16 Ld SOI X1288V14* X1288V 0 o 70 14 Ld TSSOP X1288V14Z* (Noe) X1288V Z 0 o 70 14 Ld TSSOP (Pb-free) X1288V14I* X1288V I -40 o +85 14 Ld TSSOP X1288V14IZ* (Noe) X1288V ZI -40 o +85 14 Ld TSSOP (Pb-free) X1288S16-2.7* X1288S N 2.7 o 5.5 2.85V±100mV 0 o 70 16 Ld SOI X1288S16I-2.7* X1288S P -40 o +85 16 Ld SOI X1288V14-2.7* X1288V N 0 o 70 14 Ld TSSOP X1288V14Z-2.7* (Noe) X1288V ZN 0 o 70 14 Ld TSSOP (Pb-free) X1288V14I-2.7* X1288V P -40 o +85 14 Ld TSSOP X1288V14IZ-2.7* (Noe) X1288V ZP -40 o +85 14 Ld TSSOP (Pb-free) X1288S16-2.7* X1288S F 2.65V±100mV 0 o 70 16 Ld SOI X1288S16I-2.7* X1288S G -40 o +85 16 Ld SOI X1288V14-2.7* X1288V F 0 o 70 14 Ld TSSOP X1288V14Z-2.7* (Noe) X1288V ZF 0 o 70 14 Ld TSSOP (Pb-free) X1288V14I-2.7* X1288V G -40 o +85 14 Ld TSSOP X1288V14IZ-2.7* (Noe) X1288V ZG -40 o +85 14 Ld TSSOP (Pb-free) *dd "T1" suffix for ape and reel. NOTE: Inersil Pb-free plus anneal producs employ special Pb-free maerial ses; molding compounds/die aach maerials and 100% mae in plae erminaion finish, which are RoHS complian and compaible wih boh SnPb and Pb-free soldering operaions. Inersil Pb-free producs are MSL classified a Pb-free peak reflow emperaures ha mee or exceed he Pb-free requiremens of IP/JEDE J STD-020. FN8102 Rev 3.00 Page 2 of 27
PIN SSIGNMENTS Pin Number SOI TSSOP Symbol Brief Descripion 1 1 X1 X1. The X1 pin is he inpu of an invering amplifier. n exernal 32.768kHz quarz crysal is used wih he X1288 o supply a imebase for he real ime clock. The recommended crysal is a iizen FS206-32.768DZF. Inernal compensaion circuiry is included o form a complee oscillaor circui. are should be aken in he placemen of he crysal and he layou of he circui. Pleny of ground plane around he device and shor races o X1 are highly recommended. See pplicaion secion for more informaion. 2 2 X2 X2. The X2 pin is he oupu of an invering amplifier. n exernal 32.768kHz quarz crysal is used wih he X1288 o supply a imebase for he real ime clock. The recommended crysal is a iizen FS206-32.768DZF. Inernal compensaion circuiry is included o form a complee oscillaor circui. are should be aken in he placemen of he crysal and he layou of he circui. Pleny of ground plane around he device and shor races o X2 are highly recommended. See pplicaion secion for more informaion. 7 6 RESET RESET Oupu RESET. This is a rese signal oupu. This signal noifies a hos processor ha he wachdog ime period has expired or ha he volage has dropped below a fixed V TRIP hreshold. I is an open drain acive LOW oupu. Recommended value for he pullup resisor is 5k. If unused, ie o ground. 8 7 V SS V SS. 9 8 SD Serial Daa (SD). SD is a bidirecional pin used o ransfer daa ino and ou of he device. I has an open drain oupu and may be wire ORed wih oher open drain or open collecor oupus. The inpu buffer is always acive (no gaed). n open drain oupu requires he use of a pull-up resisor. The oupu circuiry conrols he fall ime of he oupu signal wih he use of a slope conrolled pull-down. The circui is designed for 400kHz 2-wire inerface speed. 10 9 SL Serial lock (SL). The SL inpu is used o clock all daa ino and ou of he device. The inpu buffer on his pin is always acive (no gaed). 14 12 PHZ/IRQ Programmable Frequency/Inerrup Oupu PHZ/IRQ. This is eiher an oupu from he inernal oscillaor or an inerrup signal oupu. I is a MOS oupu. When used as frequency oupu, his signal has a frequency of 32.768kHz, 100Hz, 1Hz or inacive. When used as inerrup oupu, his signal noifies a hos processor ha an alarm has occurred and an acion is required. I is an acive LOW oupu. The conrol bis for his funcion are FO1 and FO0 and are found in address 0011h of he lock onrol Memory map. See Programmable Frequency Oupu Bis - FO1, FO0 on page 13. 15 13 V B V B. This inpu provides a backup supply volage o he device. V B supplies power o he device in he even he V supply fails. This pin can be conneced o a baery, a Supercap or ied o ground if no used. 16 14 V V. FN8102 Rev 3.00 Page 3 of 27
BSOLUTE MXIMUM RTINGS Temperaure Under Bias... -65 o +135 Sorage Temperaure... -65 o +150 Volage on V, V B and PHZ/IRQ pin (respec o ground)...-0.5v o 7.0V Volage on SL, SD, X1 and X2 pin (respec o ground)... -0.5V o 7.0V or 0.5V above V or V B (whichever is higher) D Oupu urren... 5 m Lead Temperaure (Soldering, 10 sec)... 300 Sresses above hose lised under bsolue Maximum Raings may cause permanen damage o he device. This is a sress raing only and he funcional operaion of he device a hese or any oher condiions above hose indicaed in he operaional secions of his specificaion is no implied. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. D OPERTING HRTERISTIS (Temperaure = -40 o +85, unless oherwise saed.) Symbol Parameer ondiions Min Typ Max Uni Noes V Main Power Supply 2.7 5.5 V V B Backup Power Supply 1.8 5.5 V V B Swich o Backup Supply V B -0.2 V B -0.1 V V B Swich o Main Supply V B V B +0.2 V OPERTING HRTERISTIS Symbol Parameer ondiions Min Typ Max Uni Noes I 1 Read cive Supply V = 2.7V 400 µ 1, 5, 7, 14 urren V = 5.0V 800 µ I 2 Program Supply urren V = 2.7V 2.5 m 2, 5, 7, 14 (nonvolaile) V = 5.0V 3.0 m I 3 Main Timekeeping V = 2.7V 10 µ 3, 7, 8, 14, 15 urren V = 5.0V 20 µ I B Timekeeping urren (Low Volage Sense and Wachdog Timer disabled V B = 1.8V 1.25 µ 3, 6, 9, 14, 15 See Performance V B = 3.3V 1.5 µ Daa V 13 I LI Inpu Leakage urren 10 µ 10 I LO Oupu Leakage urren 10 µ 10 V IL Inpu LOW Volage -0.5 V x 0.2 or V 13 V B x 0.2 V IH Inpu HIGH Volage V x 0.7 or V B x 0.7 V + 0.5 or V B + 0.5 V 13 V HYS Schmi Trigger Inpu V relaed level.05 x V or Hyseresis.05 x V B V OL1 Oupu LOW Volage for V = 2.7V 0.4 V 11 SD and RESET V = 5.5V 0.4 V OL2 Oupu LOW Volage for V = 2.7V V x 0.3 V 11 PHZ/IRQ V = 5.5V V x 0.3 V OH2 Oupu HIGH Volage for V = 2.7V V x 0.7 V 12 PHZ/IRQ V = 5.5V V x 0.7 Noes: (1) The device eners he cive sae afer any sar, and remains acive: for 9 clock cycles if he Device Selec Bis in he Slave ddress Bye are incorrec or unil 200nS afer a sop ending a read or wrie operaion. (2) The device eners he Program sae 200nS afer a sop ending a wrie operaion and coninues for W. FN8102 Rev 3.00 Page 4 of 27
(3) The device goes ino he Timekeeping sae 200nS afer any sop, excep hose ha iniiae a nonvolaile wrie cycle; W afer a sop ha iniiaes a nonvolaile wrie cycle; or 9 clock cycles afer any sar ha is no followed by he correc Device Selec Bis in he Slave ddress Bye. (4) For reference only and no esed. (5) V IL = V x 0.1, V IH = V x 0.9, f SL = 400Hz (6) V = 0V (7) V B = 0V (8) V SD = V SL =V, Ohers = GND or V (9) V SD =V SL =V B, Ohers = GND or V B (10) V SD = GND or V, V SL = GND or V, V RESET = GND or V (11) I OL = 3.0m a 5.5V, 1.5m a 2.7V (12) I OH = -1.0m a 5.5V, -0.4m a 2.7V (13) Threshold volages based on he higher of Vcc or Vback. (14) Using recommended crysal and oscillaor nework applied o X1 and X2 (25 ). (15) Typical values are for T = 25 apaciance T = 25, f = 1.0 MHz, V = 5V Symbol Parameer Max. Unis Tes ondiions (1) OUT Oupu apaciance (SD, PHZ/IRQ, RESET) 10 pf V OUT = 0V (1) IN Inpu apaciance (SL) 10 pf V IN = 0V Noes: (1) This parameer is no 100% esed. (2) The inpu capaciance beween x1 and x2 pins can be varied beween 5pF and 19.75pF by using analog rimming regisers HRTERISTIS Tes ondiions Inpu Pulse Levels V x 0.1 o V x 0.9 Inpu Rise and Fall Times 10ns Inpu and Oupu Timing V x 0.5 Levels Oupu Load Sandard Oupu Load Equivalen Oupu Load ircui for V = 5V 5.0V 5.0V 1533 For V OL = 0.4V and I OL = 3 m 1316 SD PHZ/IRQ 100pF 806 100pF FIGURE 1. STNDRD OUTPUT LOD FOR TESTING THE DEVIE WITH V = 5.0V FN8102 Rev 3.00 Page 5 of 27
Specificaions (T = -40 o +85, V = +2.7V o +5.5V, unless oherwise specified.) Symbol Parameer Min. Max. Unis f SL SL lock Frequency 400 khz IN Pulse widh Suppression Time a inpus 50 (1) ns SL LOW o SD Daa Ou Valid 0.9 s BUF Time he bus mus be free before a new ransmission can sar 1.3 s LOW lock LOW Time 1.3 s HIGH lock HIGH Time 0.6 s SU:ST Sar ondiion Seup Time 0.6 s HD:ST Sar ondiion Hold Time 0.6 s SU:DT Daa In Seup Time 100 ns HD:DT Daa In Hold Time 0 s SU:STO Sop ondiion Seup Time 0.6 s DH Daa Oupu Hold Time 50 ns R SD and SL Rise Time 20 +.1b (1)(2) 300 ns F SD and SL Fall Time 20 +.1b (1)(2) 300 ns b apaciive load for each bus line 400 pf Noes: (1) This parameer is no 100% esed. (2) b = oal capaciance of one bus line in pf. TIMING DIGRMS Bus Timing F HIGH LOW R SL SU:DT SU:ST HD:ST HD:DT SU:STO SD IN DH BUF SD OUT Wrie ycle Timing SL SD 8h Bi of Las Bye Sop ondiion W Sar ondiion FN8102 Rev 3.00 Page 6 of 27
Power-up Timing Noes: (1) Delays are measured from he ime V is sable unil he specified operaion can be iniiaed. These parameers are no 100% esed. V slew rae should be beween 0.2mV/µsec and 50mV/µsec. (2) Typical values are for T = 25 and V = 5.0V Nonvolaile Wrie ycle Timing Noe: Symbol Parameer Min. Typ. (2) Max. Unis (1) PUR Time from Power-up o Read 1 ms (1) PUW Time from Power-up o Wrie 5 ms Symbol Parameer Min. Typ. (1) Max. Unis W (1) Wrie ycle Time 5 10 ms (1) W is he ime from a valid sop condiion a he end of a wrie sequence o he end of he self-imed inernal nonvolaile wrie cycle. I is he minimum cycle ime o be allowed for any nonvolaile wrie by he user, unless cknowledge Polling is used. WTHDOG TIMER/LOW VOLTGE RESET OPERTING HRTERISTIS Wachdog/Low Volage Rese Parameers (See Figures 3 and 4) Symbols Parameers Min. Typ. Max. Uni V PTRIP Programmed Rese Trip Volage X1288-4.5 X1288 X1288-2.7 X1288-2.7 RPD V Deec o RESET LOW 500 ns PURST Power-up Rese Time-ou Delay 100 250 400 ms F V Fall Time 10 µs R V Rise Time 10 µs WDO Wachdog Timer Period (rysal=32.768khz): WD1=0, WD0=0, (defaul) 1.7 1.75 1.8 s WD1=0, WD0=1 725 750 775 ms WD1=1, WD0=0 225 250 275 ms RST Wachdog Rese Time-ou Delay (rysal=32.768khz) 225 250 275 ms RSP 2-Wire inerface 1 µs V RVLID Rese Valid V 1.0 V 4.50 4.25 2.75 2.55 4.63 4.38 2.85 2.65 4.75 4.50 2.95 2.75 V FN8102 Rev 3.00 Page 7 of 27
V TRIP Programming Timing Diagram V (V TRIP ) V TRIP TSU THD RESET V P = 15V V V SL VPS VPH 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VPO RP SD Eh 00h 03h/01h 00h V TRIP Programming Parameers Parameer Descripion Min. Max. Unis VPS V TRIP Program Enable Volage Seup ime 1 µs VPH V TRIP Program Enable Volage Hold ime 1 µs TSU V TRIP Seup ime 1 µs THD V TRIP Hold (sable) ime 10 ms VPO V TRIP Program Enable Volage Off ime 0 µs (Beween successive adjusmens) RP V TRIP Program Recovery Period 10 ms (Beween successive adjusmens) V P Programming Volage 14 16 V V TRN V TRIP Programmed Volage Range 1.7 5.0 V V v V TRIP Program variaion afer programming (Programmed a 25 ) -25 +25 mv V TRIP programming parameers are no 100% Tesed. DESRIPTION The X1288 device is a Real Time lock wih clock/calendar, wo polled alarms wih inegraed 32kx8 EEPROM, oscillaor compensaion, PU Supervisor (POR/LVS and WDT) and baery backup swich. The oscillaor uses an exernal, low-cos 32.768kHz crysal. ll compensaion and rim componens are inegraed on he chip. This eliminaes several exernal discree componens and a rim capacior, saving board area and componen cos. The Real-Time lock keeps rack of ime wih separae regisers for Hours, Minues, Seconds and 1/100 of a second. The alendar has separae regisers for Dae, Monh, Year and Day-of-week. The calendar is correc hrough 2099, wih auomaic leap year correcion. The powerful Dual larms can be se o any lock/alendar value for a mach. For insance, every minue, every Tuesday, or 5:23 M on March 21. The alarms can be polled in he Saus Regiser or provide a hardware inerrup (IRQ Pin). There is a repea mode for he alarms allowing a periodic inerrup. The PHZ/IRQ pin may be sofware seleced o provide a frequency oupu of 1 Hz, 100 Hz, or 32,768 Hz. The X1288 device inegraes PU Supervisor func-ions and a Baery Swich. There is a Power-On Rese (RESET oupu) wih ypically 250 ms delay from power-on. I will also asser RESET when Vcc goes below he specified hreshold. The Vrip hreshold is user repro-grammable. There is a WachDog Timer (WDT) wih 3 selecable imeou periods (0.25s, 0.75s, 1.75s) and a disabled seing. The wachdog acivaes he RESET pin when i expires. FN8102 Rev 3.00 Page 8 of 27
The device offers a backup power inpu pin. This V B pin allows he device o be backed up by baery or Superap. The enire X1288 device is fully operaional from 2.7 o 5.5 vols and he clock/calendar porion of he X1288 device remains fully operaional down o 1.8 vols (Sandby Mode). The X1288 device provides 256 bis of EEPROM wih 8 modes of BlockLock conrol. The BlockLock allows a safe, secure memory for criical user and configuraion daa, while allowing a large user sorage area. PIN DESRIPTIONS X1 X2 RESET V SS 16 Ld SOI 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 X1288 14 Ld TSSOP V X1 1 14 V V B X2 2 13 V B PHZ/IRQ 3 4 12 11 PHZ/IRQ 5 10 RESET 6 9 SL SL SD V SS 7 8 SD = No inernal connecion Serial lock (SL) The SL inpu is used o clock all daa ino and ou of he device. The inpu buffer on his pin is always acive (no gaed). Serial Daa (SD) SD is a bidirecional pin used o ransfer daa ino and ou of he device. I has an open drain oupu and may be wire ORed wih oher open drain or open collecor oupus. The inpu buffer is always acive (no gaed). n open drain oupu requires he use of a pull-up resisor. The oupu circuiry conrols he fall ime of he oupu signal wih he use of a slope conrolled pull-down. The circui is designed for 400kHz 2-wire inerface speed. V B This inpu provides a backup supply volage o he device. V B supplies power o he device in he even he V supply fails. This pin can be conneced o a baery, a Supercap or ied o ground if no used. RESET Oupu RESET This is a rese signal oupu. This signal noifies a hos processor ha he wachdog ime period has expired or ha he volage has dropped below a fixed V TRIP hreshold. I is an open drain acive LOW oupu. Recommended value for he pullup resisor is 5k. If unused, ie o ground. Programmable Frequency/Inerrup Oupu PHZ/IRQ This is eiher an oupu from he inernal oscillaor or an inerrup signal oupu. I is a MOS oupu. When used as frequency oupu, his signal has a frequency of 32.768kHz, 100Hz, 1Hz or inacive. When used as inerrup oupu, his signal noifies a hos processor ha an alarm has occurred and an acion is required. I is an acive LOW oupu. The conrol bis for his funcion are FO1 and FO0 and are found in address 0011h of he lock onrol Memory map. See Programmable Frequency Oupu Bis - FO1, FO0 on page 13. X1, X2 The X1 and X2 pins are he inpu and oupu, respecively, of an invering amplifier. n exernal 32.768kHz quarz crysal is used wih he X1288 o supply a imebase for he real ime clock. The recommended crysal is a iizen FS206-32.768DZF. Inernal compensaion circuiry is included o form a complee oscillaor circui. are should be aken in he placemen of he crysal and he layou of he circui. Pleny of ground plane around he device and shor races o X1 and X2 are highly recommended. See pplicaion secion for more informaion. POWER ONTROL OPERTION The power conrol circui acceps a V and a V B inpu. The power conrol circui powers he clock from V B when V < V B - 0.2V. I will swich back o power he device from V when V exceeds V B. V B X1 X2 FIGURE 2. REOMMENDED RYSTL ONNETION Off V Volage FIGURE 3. POWER ONTROL REL TIME LO OPERTION The Real Time lock (RT) uses an exernal 32.768kHz quarz crysal o mainain an accurae inernal represenaion of he 1/100 of a second, second, minue, hour, day, dae, monh, and year. The RT has leap-year correcion. The clock also correcs for monhs having fewer han 31 days and has a bi ha conrols 24 hour or M/PM forma. When he X1288 powers up afer he loss of boh V and V B, he clock will no operae unil a leas one bye is wrien o he clock regiser. On In FN8102 Rev 3.00 Page 9 of 27
Reading he Real Time lock The RT is read by iniiaing a Read command and specifying he address corresponding o he regiser of he Real Time lock. The RT Regisers can hen be read in a Sequenial Read Mode. Since he clock runs coninuously and a read akes a finie amoun of ime, here is he possibiliy ha he clock could change during he course of a read operaion. In his device, he ime is lached by he read command (falling edge of he clock on he bi prior o RT daa oupu) ino a separae lach o avoid ime changes during he read operaion. The clock coninues o run. larms occurring during a read are unaffeced by he read operaion. Wriing o he Real Time lock The ime and dae may be se by wriing o he RT regisers. To avoid changing he curren ime by an uncompleed wrie operaion, he curren ime value is loaded ino a separae buffer a he falling edge of he clock on he bi before he RT daa inpu byes, he clock coninues o run. The new serial inpu daa replaces he values in he buffer. This new RT value is loaded back ino he RT Regiser by a sop bi a he end of a valid wrie sequence. n invalid wrie operaion abors he ime updae procedure and he conens of he buffer are discarded. fer a valid wrie operaion he RT will reflec he newly loaded daa beginning wih he SSE regiser rese o 0 a he nex sub-second updae afer he sop bi is wrien. The 1Hz frequency oupu from he PHZ/IRQ pin will be rese o resar afer he sop bi is wrien. The RT coninues o updae he ime while an RT regiser wrie is in progress and he RT coninues o run during any nonvolaile wrie sequences. single bye may be wrien o he RT wihou affecing he oher byes. ccuracy of he Real Time lock The accuracy of he Real Time lock depends on he frequency of he quarz crysal ha is used as he ime base for he RT. Since he resonan frequency of a crysal is emperaure dependen, he RT performance will also be dependen upon emperaure. The frequency deviaion of he crysal is a funcion of he urnover emperaure of he crysal from he crysal s nominal frequency. For example, a >20ppm frequency deviaion ranslaes ino an accuracy of >1 minue per monh. hese parameers are available from he crysal manufacurer. Inersil s RT family provides on-chip crysal compensaion neworks o adjus load-capaciance o une oscillaor frequency from +116 ppm o 37 ppm when using a 12.5 pf load crysal. For more deail informaion see he pplicaion secion. following a slave bye of 1101111x and reads or wries o addresses [0000h:003Fh]. The clock/conrol memory map has memory addresses from 0000h o 003Fh. The defined addresses are described in he Table 1. Wriing o and reading from he undefined addresses are no recommended. R ccess The conens of he R can be modified by performing a bye or a page wrie operaion direcly o any address in he R. Prior o wriing o he R (excep he saus regiser), however, he WEL and RWEL bis mus be se using a wo sep process (See secion Wriing o he lock/onrol Regisers. ) The R is divided ino 5 secions. These are: 1. larm 0 (8 byes; non-volaile) 2. larm 1 (8 byes; non-volaile) 3. onrol (4 byes; non-volaile) 4. Real Time lock (8 byes; volaile) 5. Saus (1 bye; volaile) Each regiser is read and wrien hrough buffers. The nonvolaile porion (or he couner porion of he RT) is updaed only if RWEL is se and only afer a valid wrie operaion and sop bi. sequenial read or page wrie operaion provides access o he conens of only one secion of he R per operaion. ccess o anoher secion requires a new operaion. oninued reads or wries, once reaching he end of a secion, will wrap around o he sar of he secion. read or wrie can begin a any address in he R. I is no necessary o se he RWEL bi prior o wriing he saus regiser. Secion 5 suppors a single bye read or wrie only. oninued reads or wries from his secion erminaes he operaion. The sae of he R can be read by performing a random read a any address in he R a any ime. This reurns he conens of ha regiser locaion. ddiional regisers are read by performing a sequenial read. The read insrucion laches all lock regisers ino a buffer, so an updae of he clock does no change he ime being read. sequenial read of he R will no resul in he oupu of daa from he memory array. he end of a read, he maser supplies a sop condiion o end he operaion and free he bus. fer a read of he R, he address remains a he previous address +1 so he user can execue a curren address read of he R and coninue reading he nex Regiser. LO/ONTROL REGISTERS (R) The onrol/lock Regisers are locaed in an area separae from he EEPROM array and are only accessible FN8102 Rev 3.00 Page 10 of 27
Table 1. lock/onrol Memory Map ddr. Type Reg Name 7 6 5 4 3 2 1 Bi 0 (opional) 003F Saus SR BT L1 L0 0 0 RWEL WEL RTF 01h 0037 RT SSE SS23 SS22 SS21 SS20 SS13 SS12 SS11 SS10 0-99 xxh 0036 (SRM) DW 0 0 0 0 0 DY2 DY1 DY0 0-6 xxh 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 xxh 0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 xxh 0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 xxh 0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 xxh 0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 xxh 0030 S 0 S22 S21 S20 S13 S12 S11 S10 0-59 xxh 0013 onrol (EE- DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h 0012 PROM) TR 0 0 TR5 TR4 TR3 TR2 TR1 TR0 00h 0011 INT IM L1E L0E FO1 FO0 Read Only Read Only Read Only 00h 0010 BL BP2 BP1 BP0 WD1 WD0 Read Only Read Only Read Only 18h 000F larm1 Y21 Read-only - Defaul = 20h 20 20h 000E (EEPROM) DW1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h 000D YR1 Unused - Defaul = RT Year value (No EEPROM) - Fuure expansion 000 MO1 EMO1 0 0 1G20 1G13 1G12 1G11 1G10 1-12 00h 000B DT1 EDT1 0 1D21 1D20 1D13 1D12 1D11 1D10 1-31 00h 000 HR1 EHR1 0 1H21 1H20 1H13 1H12 1H11 1H10 0-23 00h 0009 MN1 EMN1 1M22 1M21 1M20 1M13 1M12 1M11 1M10 0-59 00h 0008 S1 ES1 1S22 1S21 1S20 1S13 1S12 1S11 1S10 0-59 00h 0007 larm0 Y20 Read-only - Defaul = 20h 20 20h 0006 (EEPROM) DW0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h 0005 YR0 Unused - Defaul = RT Year value (No EEPROM) Fuure expansion 0004 MO0 EMO0 0 0 0G20 0G13 0G12 0G11 0G10 1-12 00h 0003 DT0 EDT0 0 0D21 0D20 0D13 0D12 0D11 0D10 1-31 00h 0002 HR0 EHR0 0 0H21 0H20 0H13 0H12 0H11 0H10 0-23 00h 0001 MN0 EMN0 0M22 0M21 0M20 0M13 0M12 0M11 0M10 0-59 00h 0000 S0 ES0 0S22 0S21 0S20 0S13 0S12 0S11 0S10 0-59 00h Range Defaul LRM REGISTERS There are wo alarm regisers whose conens mimic he conens of he RT regiser, bu add enable bis and exclude he 24 hour ime selecion bi. The enable bis specify which regisers o use in he comparison beween he larm and Real Time Regisers. For example: Seing he Enable Monh bi (EMOn*) bi in combinaion wih oher enable bis and a specific alarm ime, he user can esablish an alarm ha riggers a he same ime once a year. *n = 0 for larm 0: N = 1 for larm 1 When here is a mach, an alarm flag is se. The occurrence of an alarm can be deermined by polling he L0 and L1 bis or by enabling he IRQ oupu, using i as hardware flag. The alarm enable bis are locaed in he MSB of he paricular regiser. When all enable bis are se o 0, here are no alarms. The user can se he X1288 o alarm every Wednesday a 8:00 M by seing he EDWn*, he EHRn* and EMNn* enable bis o 1 and seing he DWn*, HRn* and MNn* larm regisers o 8:00 M Wednesday. daily alarm for 9:30PM resuls when he EHRn* and EMNn* enable bis are se o 1 and he HRn* and MNn* regisers are se o 9:30 PM. *n = 0 for larm 0: N = 1 for larm 1 REL TIME LO REGISTERS lock/alendar Regisers (SSE, S, MN, HR, DT, MO, YR) These regisers depic BD represenaions of he ime. s such, SSE (1/100 Second) range from 00 o 99, S (Seconds) and MN (Minues) range from 00 o 59, HR (Hour) is 1 o 12 wih an M or PM indicaor (H21 bi) or FN8102 Rev 3.00 Page 11 of 27
0 o 23 (wih MIL=1), DT (Dae) is 1 o 31, MO (Monh) is 1 o 12, YR (Year) is 0 o 99. The SSE regiser is readonly. Dae of he Week Regiser (DW) This regiser provides a Day of he Week saus and uses hree bis DY2 o DY0 o represen he seven days of he week. The couner advances in he cycle 0-1-2-3- 4-5-6-0-1-2- The assignmen of a numerical value o a specific day of he week is arbirary and may be decided by he sysem sofware designer. The defaul value is defined as 0. 24 Hour Time If he MIL bi of he HR regiser is 1, he RT uses a 24- hour forma. If he MIL bi is 0, he RT uses a 12-hour forma and H21 bi funcions as an M/PM indicaor wih a 1 represening PM. The clock defauls o sandard ime wih H21=0. Leap Years Leap years add he day February 29 and are defined as hose years ha are divisible by 4. Years divisible by 100 are no leap years, unless hey are also divisible by 400. This means ha he year 2000 is a leap year, he year 2100 is no. The X1288 does no correc for he leap year in he year 2100. STTUS REGISTER (SR) The Saus Regiser is locaed in he R memory map a address 003Fh. This is a volaile regiser only and is used o conrol he WEL and RWEL wrie enable laches, read wo power saus and wo alarm bis. This regiser is separae from boh he array and he lock/onrol Regisers (R). Table 2. Saus Regiser (SR) ddr 7 6 5 4 3 2 1 0 003Fh BT L1 L0 0 0 RWEL WEL RTF Defaul 0 0 0 0 0 0 0 1 BT: Baery Supply - Volaile This bi se o 1 indicaes ha he device is operaing from V B, no V. I is a read-only bi and is se/rese by hardware (X1288 inernally). Once he device begins operaing from V, he device ses his bi o 0. alarm bi ha is se by an alarm occurring during an SR read operaion will remain se afer he read operaion is complee. RWEL: Regiser Wrie Enable Lach - Volaile This bi is a volaile lach ha powers up in he LOW (disabled) sae. The RWEL bi mus be se o 1 prior o any wries o he lock/onrol Regisers. Wries o RWEL bi do no cause a nonvolaile wrie cycle, so he device is ready for he nex operaion immediaely afer he sop condiion. wrie o he R requires boh he RWEL and WEL bis o be se in a specific sequence. WEL: Wrie Enable Lach - Volaile The WEL bi conrols he access o he R and memory array during a wrie operaion. This bi is a volaile lach ha powers up in he LOW (disabled) sae. While he WEL bi is LOW, wries o he R or any array address will be ignored (no acknowledge will be issued afer he Daa Bye). The WEL bi is se by wriing a 1 o he WEL bi and zeroes o he oher bis of he Saus Regiser. Once se, WEL remains se unil eiher rese o 0 (by wriing a 0 o he WEL bi and zeroes o he oher bis of he Saus Regiser) or unil he par powers up again. Wries o WEL bi do no cause a nonvolaile wrie cycle, so he device is ready for he nex operaion immediaely afer he sop condiion. RTF: Real Time lock Fail Bi - Volaile This bi is se o a 1 afer a oal power failure. This is a read only bi ha is se by hardware (ISL1288 inernally) when he device powers up afer having los all power o he device (boh V and V B go o 0V). The bi is se regardless of wheher V or V B is applied firs. The loss of only one of he supplies does no se he RTF bi o 1. On power up afer a oal power failure, all regisers are se o heir defaul saes and he clock will no incremen unil a leas one bye is wrien o he clock regiser. The firs valid wrie o he RT secion afer a complee power failure reses he RTF bi o 0 (wriing one bye is sufficien). Unused Bis: This device does no use bis 3 or 4 in he SR, bu mus have a zero in hese bi posiions. The Daa Bye oupu during a SR read will conain zeros in hese bi locaions. L1, L0: larm Bis - Volaile These bis announce if eiher alarm 0 or alarm 1 mach he real ime clock. If here is a mach, he respecive bi is se o 1. The falling edge of he las daa bi in a SR Read operaion reses he flags. Noe: Only he L bis ha are se when an SR read sars will be rese. n FN8102 Rev 3.00 Page 12 of 27
ONTROL REGISTERS The onrol Bis and Regisers, described under his secion, are nonvolaile. Block Proec Bis - BP2, BP1, BP0 The Block Proec Bis, BP2, BP1 and BP0, deermine which blocks of he array are wrie proeced. wrie o a proeced block of memory is ignored. The block proec bis will preven wrie operaions o one of eigh segmens of he array. The pariions are described in Table 3. Wachdog Timer onrol Bis - WD1, WD0 The bis WD1 and WD0 conrol he period of he Wachdog Timer. See Table 4 for opions. Table 3. Block Proec Bis Proeced ddresses X1288 rray Lock 0 0 0 None None (defaul) 0 0 1 6000h 7FFFh Upper 1/4 0 1 0 4000h 7FFFh Upper 1/2 0 1 1 0000h 7FFFh Full rray 1 0 0 0000h 007Fh Firs Page 1 0 1 0000h 00FFh Firs 2 pgs 1 1 0 0000h 01FFh Firs 4 pgs 1 1 1 0000h 03FFh Firs 8 Pgs BP2 BP1 BP0 Table 4. Wachdog Timer Time-Ou Opions WD1 WD0 Wachdog Time-Ou Period 0 0 1.75 seconds 0 1 750 milliseconds 1 0 250 milliseconds 1 1 Disabled (defaul) INTERRUPT ONTROL ND FREQUEY OUTPUT REGISTER (INT) Inerrup onrol and Saus Bis (IM, L1E, L0E) There are wo Inerrup onrol bis, larm 1 Inerrup Enable (L1E) and larm 0 Inerrup Enable (L0E) o specifically enable or disable he alarm inerrup signal oupu (IRQ). The inerrups are enabled when eiher L1E and L0E are se o 1, respecively. Two volaile bis (L1 and L0), associaed wih he wo alarms respecively, indicae if an alarm has happened. These bis are se on an alarm condiion regardless of wheher he IRQ inerrup is enabled. The L1 and L0 bis in he saus regiser are rese by he falling edge of he eighh clock of a read of he regiser conaining he bis. Pulse Inerrup Mode The pulsed inerrup mode allows for repeiive or recurring alarm funcionaliy. Hence an repeiive or recurring alarm can be se for every n h second, or n h minue, or n h hour, or n h dae, or for he same day of he week. The pulsed inerrup mode can be considered a repeiive inerrup mode, wih he repeiion rae se by he ime seing fo he alarm. The Pulse Inerrup Mode is enabled when he IM bi is se. IM Bi Inerrup/larm Frequency 0 Single Time Even Se By larm 1 Repeiive/Recurring Time Even Se By larm The larm IRQ oupu will oupu a single pulse of shor duraion (approximaely 10-40ms) once he alarm condiion is me. If he inerrup mode bi (IM bi) is se, hen his pulse will be periodic. Programmable Frequency Oupu Bis - FO1, FO0 These are wo oupu conrol bis. They selec one of hree divisions of he inernal oscillaor, ha is applied o he PHZ oupu pin. Table 5 shows he selecion bis for his oupu. When using he PHZ oupu funcion, he larm IRQ oupu funcion is disabled. Table 5. Programmable Frequency Oupu Bis FO1 FO0 Oupu Frequency (average of 100 samples) 0 0 larm IRQ oupu 0 1 32.768kHz 1 0 100Hz 1 1 1Hz ON-HIP OSILLTOR OMPENSTION Digial Trimming Regiser (DTR) - DTR2, DTR1 and DTR0 (Non-Volaile) The digial rimming Bis DTR2, DTR1 and DTR0 adjus he number of couns per second and average he ppm error o achieve beer accuracy. DTR2 is a sign bi. DTR2=0 means frequency compensaion is > 0. DTR2=1 means frequency compensaion is < 0. DTR1 and DTR0 are scale bis. DTR1 gives 10 ppm adjusmen and DTR0 gives 20 ppm adjusmen. range from -30ppm o +30ppm can be represened by using hree bis above. FN8102 Rev 3.00 Page 13 of 27
Table 6. Digial Trimming Regisers DTR Regiser Esimaed frequency DTR2 DTR1 DTR0 PPM 0 0 0 0 0 1 0 +10 0 0 1 +20 0 1 1 +30 1 0 0 0 1 1 0-10 1 0 1-20 1 1 1-30 nalog Trimming Regiser (TR) (Non-volaile) Six analog rimming Bis from TR5 o TR0 are provided o adjus he on-chip loading capaciance range. The onchip load capaciance ranges from 3.25pF o 18.75pF. Each bi has a differen weigh for capaciance adjusmen. Using a iizen FS-206 crysal wih differen TR bi combinaions provides an esimaed ppm range from +116ppm o -37ppm o he nominal frequency compensaion. The combinaion of digial and analog rimming can give up o +146ppm adjusmen. The on-chip capaciance can be calculaed as follows: TR = [(TR value, decimal) x 0.25pF] + 11.0pF Noe ha he TR values are in wo s complemen, wih TR(000000) = 11.0pF, so he enire range runs from 3.25pF o 18.75pF in 0.25pF seps. The values calculaed above are ypical, and oal load capaciance seen by he crysal will include approximaely 2pF of package and board capaciance in addiion o he TR value. See pplicaion secion and Inersil s pplicaion Noe N154 for more informaion. WRITING TO THE LO/ONTROL REGISTERS hanging any of he nonvolaile bis of he clock/ conrol regiser requires he following seps: Wrie a 02h o he Saus Regiser o se he Wrie Enable Lach (WEL). This is a volaile operaion, so here is no delay afer he wrie. (Operaion preceeded by a sar and ended wih a sop). Wrie a 06h o he Saus Regiser o se boh he Regiser Wrie Enable Lach (RWEL) and he WEL bi. This is also a volaile cycle. The zeros in he daa bye are required. (Operaion preceeded by a sar and ended wih a sop). Wrie one o 8 byes o he lock/onrol Regisers wih he desired clock, alarm, or conrol daa. This sequence sars wih a sar bi, requires a slave bye of 11011110 and an address wihin he R and is erminaed by a sop bi. wrie o he R changes EEPROM values so hese iniiae a nonvolaile wrie cycle and will ake up o 10ms o complee. Wries o undefined areas have no effec. The RWEL bi is rese by he compleion of a nonvolaile wrie cycle, so he sequence mus be repeaed o again iniiae anoher change o he R conens. If he sequence is no compleed for any reason (by sending an incorrec number of bis or sending a sar insead of a sop, for example) he RWEL bi is no rese and he device remains in an acive mode. Wriing all zeros o he saus regiser reses boh he WEL and RWEL bis. read operaion occurring beween any of he previous operaions will no inerrup he regiser wrie operaion. POWER-ON RESET pplicaion of power o he X1288 acivaes a Power-on Rese ircui ha pulls he RESET pin acive. This signal provides several benefis. I prevens he sysem microprocessor from saring o operae wih insufficien volage. I prevens he processor from operaing prior o sabilizaion of he oscillaor. I allows ime for an FPG o download is configuraion prior o iniializaion of he circui. I prevens communicaion o he EEPROM, grealy reducing he likelihood of daa corrupion on power-up. When V exceeds he device V TRIP hreshold value for ypically, 250ms he circui releases RESET, allowing he sysem o begin operaion. Recommended V slew rae is beween 0.2V/ms and 50V/ms. WTHDOG TIMER OPERTION The wachdog imer is selecable. By wriing a value o WD1 and WD0, he wachdog imer can be se o 3 differen ime ou periods or off. When he Wachdog imer is se o off, he wachdog circui is configured for low power operaion. Wachdog Timer Resar The Wachdog Timer is sared by a falling edge of SD when he SL line is high and followed by a sop bi. The sar signal resars he wachdog imer couner, reseing he period of he couner back o he maximum. If anoher sar fails o be deeced prior o he wachdog imer expiraion, hen he RESET pin becomes acive. In he even ha he sar signal occurs during a rese ime ou period, he sar will have no effec. When using a single STRT o refresh wachdog imer, a STOP bi should be followed o rese he device back o sand-by mode. FN8102 Rev 3.00 Page 14 of 27
RSP RSP > WDO RSP < WDO RSP > WDO RST RST SL SD RESET Sar Sop Sar Noe: ll inpus are ignored during he acive rese period ( RST ). FIGURE 4. WTHDOG RESTRT/TIME OUT LOW VOLTGE RESET OPERTION When a power failure occurs, and he volage o he par drops below a fixed v TRIP volage, a rese pulse is issued o he hos microconroller. The circuiry moniors he V line wih a volage comparaor which senses a prese hreshold volage. Power-up and power-down waveforms are shown in Figure 5. The Low Volage Rese circui is o be designed so he RESET signal is valid down o 1.0V. When he low volage rese signal is acive, he operaion of any in progress nonvolaile wrie cycle is unaffeced, allowing a nonvolaile wrie o coninue as long as possible (down o he power-on rese volage). The low volage rese signal, when acive, erminaes in progress communicaions o he device and prevens new commands, o reduce he likelihood of daa corrupion. V THRESHOLD RESET PROEDURE [Opional] The X1288 is shipped wih a sandard V hreshold (V TRIP ) volage. This value will no change over normal operaing and sorage condiions. However, in applicaions where he sandard V TRIP is no exacly righ, or if higher precision is needed in he V TRIP value, he X1288 hreshold may be adjused. The procedure is described below, and uses he applicaion of a nonvolaile wrie conrol signal. Seing he V TRIP Volage I is necessary o rese he rip poin before seing he new value. operaion may ake up o 10 milliseconds o complee and also wries 00h o address 01h of he EEPROM array. Reseing he V TRIP Volage This procedure is used o se he V TRIP o a naive volage level. For example, if he curren V TRIP is 4.4V and he new V TRIP mus be 4.0V, hen he V TRIP mus be rese. When V TRIP is rese, he new V TRIP is somehing less han 1.7V. This procedure mus be used o se he volage o a lower value. To rese he new V TRIP volage, apply more han 5.5V o he V pin and ie he RESET pin o he programming volage V P. Then wrie 00h o address 03h. The sop bi of a valid wrie operaion iniiaes he V TRIP programming sequence. Bring RESET o V o complee he operaion. Noe: his operaion akes up o 10 milliseconds o complee and also wries 00h o address 03h of he EEPROM array. For bes accuracy in seing V TRIP, i is advised ha he following sequence be used. 1.Program V TRIP as above. 2.Measure resuling V TRIP by measuring he V value where a RESET occurs. alculae Dela = (Desired Measured) V TRIP value. 3.Perform a V TRIP program using he following formula o se he volage of he RESET pin: V RESET = (Desired Value Dela) + 0.025V To se he new V TRIP volage, apply he desired V TRIP hreshold volage o he V pin and ie he RESET pin o he programming volage V P. Then wrie daa 00h o address 01h. The sop bi following a valid wrie operaion iniiaes he V TRIP programming sequence. Bring RESET o V o complee he operaion. Noe: his FN8102 Rev 3.00 Page 15 of 27
V TRIP V PURST PURST RPD R F RESET V RVLID FIGURE 5. POWER-ON RESET ND LOW VOLTGE RESET RESET V SL V P = 15V 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 V SD Eh 00h 01h 00h Noe: BP0, BP1, BP2 mus be disabled. FIGURE 6. SET V TRIP LEVEL SEQUEE (V = DESIRED V TRIP VLUE) RESET V P = 15V V V 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SL SD Eh 00h 03h 00h Noe: BP0, BP1, BP2 mus be disabled. FIGURE 7. RESET V TRIP LEVEL SEQUEE SL SD Daa Sable Daa hange Daa Sable FIGURE 8. VLID DT HNGES ON THE SD BUS FN8102 Rev 3.00 Page 16 of 27
SL SD Sar Sop FIGURE 9. VLID STRT ND STOP ONDITIONS SL from Maser 1 8 9 Daa Oupu from Transmier Daa Oupu from Receiver Sar cknowledge FIGURE 10. NOWLEDGE RESPONSE FROM REEIVER Device Idenifier rray R 1 1 0 1 1 0 0 1 1 1 1 R/W Slave ddress Bye Bye 0 0 14 13 12 11 10 9 8 Word ddress 1 Bye 1 7 6 5 4 3 2 1 0 Word ddress 0 Bye 2 D7 D6 D5 D4 D3 D2 D1 D0 Daa Bye Bye 3 FIGURE 11. SLVE DDRESS, WORD DDRESS, ND DT BYTES (128 BYTE PGES) FN8102 Rev 3.00 Page 17 of 27
Signals from he Maser S a r Slave ddress Word ddress 1 Word ddress 0 Daa S o p SD Bus 1 1 1 1 0 0 Signals From The Slave FIGURE 12. BYTE WRITE SEQUEE. 7 Byes 23 Byes ddress = 6 ddress Poiner Ends Here ddr = 7 ddress 105 ddress 127 FIGURE 13. WRITING 30 BYTES TO 128-BYTE MEMORY PGE STRTING T DDRESS 105 SERIL OMMUNITION Inerface onvenions The device suppors a bidirecional bus oriened proocol. The proocol defines any device ha sends daa ono he bus as a ransmier, and he receiving device as he receiver. The device conrolling he ransfer is called he maser and he device being conrolled is called he slave. The maser always iniiaes daa ransfers, and provides he clock for boh ransmi and receive operaions. Therefore, he devices in his family operae as slaves in all applicaions. lock and Daa Daa saes on he SD line can change only during SL LOW. SD sae changes during SL HIGH are reserved for indicaing sar and sop condiions. See Figure 8. Sar ondiion ll commands are preceded by he sar condiion, which is a HIGH o LOW ransiion of SD when SL is HIGH. The device coninuously moniors he SD and SL lines for he sar condiion and will no respond o any command unil his condiion has been me. See Figure 9. Sop ondiion ll communicaions mus be erminaed by a sop condiion, which is a LOW o HIGH ransiion of SD when SL is HIGH. The sop condiion is also used o place he device ino he Sandby power mode afer a read sequence. sop condiion can only be issued afer he ransmiing device has released he bus. See Figure 9. cknowledge cknowledge is a sofware convenion used o indicae successful daa ransfer. The ransmiing device, eiher maser or slave, will release he bus afer ransmiing eigh bis. During he ninh clock cycle, he receiver will pull he SD line LOW o acknowledge ha i received he eigh bis of daa. Refer o Figure 10. The device will respond wih an acknowledge afer recogniion of a sar condiion and if he correc Device Idenifier and Selec bis are conained in he Slave ddress Bye. If a wrie operaion is seleced, he device will respond wih an acknowledge afer he receip of each subsequen eigh bi word. The device will acknowledge all incoming daa and address byes, excep for: The Slave ddress Bye when he Device Idenifier and/or Selec bis are incorrec ll Daa Byes of a wrie when he WEL in he Wrie Proec Regiser is LOW The 2nd Daa Bye of a Saus Regiser Wrie Operaion (only 1 daa bye is allowed) In he read mode, he device will ransmi eigh bis of daa, release he SD line, hen monior he line for an acknowledge. If an acknowledge is deeced and no sop condiion is generaed by he maser, he device will con- FN8102 Rev 3.00 Page 18 of 27
inue o ransmi daa. The device will erminae furher daa ransmissions if an acknowledge is no deeced. The maser mus hen issue a sop condiion o reurn he device o Sandby mode and place he device ino a known sae. DEVIE DDRESSING Following a sar condiion, he maser mus oupu a Slave ddress Bye. The firs four bis of he Slave ddress Bye specify access o eiher he EEPROM array or o he R. Slave bis 1010 access he EEPROM array. Slave bis 1101 access he R. When shipped from he facory, EEPROM array is UNDEFINED, and should be programmed by he cusomer o a known sae. Bi 3 hrough Bi 1 of he slave bye specify he device selec bis. These are se o 111. The las bi of he Slave ddress Bye defines he operaion o be performed. When his R/W bi is a one, hen a read operaion is seleced. zero selecs a wrie operaion. Refer o Figure 11. fer loading he enire Slave ddress Bye from he SD bus, he X1288 compares he device idenifier and device selec bis wih 1010111 or 1101111. Upon a correc compare, he device oupus an acknowledge on he SD line. Following he Slave Bye is a wo bye word address. The word address is eiher supplied by he maser device or obained from an inernal couner. On powerup he inernal address couner is se o address 0h, so a curren address read of he EEPROM array sars a address 0. When required, as par of a random read, he maser mus supply he 2 Word ddress Byes as shown in Figure 11. In a random read operaion, he slave bye in he dummy wrie porion mus mach he slave bye in he read secion. Tha is if he random read is from he array he slave bye mus be 1010111x in boh insances. Similarly, for a random read of he lock/onrol Regisers, he slave bye mus be 1101111x in boh places. Wrie Operaions Bye Wrie For a wrie operaion, he device requires he Slave ddress Bye and he Word ddress Byes. This gives he maser access o any one of he words in he array or R. (Noe: Prior o wriing o he R, he maser mus wrie a 02h, hen 06h o he saus regiser in wo preceding operaions o enable he wrie operaion. See Wriing o he lock/onrol Regisers. Upon receip of each address bye, he X1288 responds wih an acknowledge. fer receiving boh address byes he X1288 awais he eigh bis of daa. fer receiving he 8 daa bis, he X1288 again responds wih an acknowledge. The maser hen erminaes he ransfer by generaing a sop condiion. The X1288 hen begins an inernal wrie cycle of he daa o he nonvolaile memory. During he inernal wrie cycle, he device inpus are disabled, so he device will no respond o any requess from he maser. The SD oupu is a high impedance. See Figure 12. wrie o a proeced block of memory is ignored, bu will sill receive an acknowledge. he end of he wrie command, he X1288 will no iniiae an inernal wrie cycle, and will coninue o commands. Page Wrie The X1288 has a page wrie operaion. I is iniiaed in he same manner as he bye wrie operaion; bu insead of erminaing he wrie cycle afer he firs daa bye is ransferred, he maser can ransmi up o 127 more byes o he memory array and up o 7 more byes o he clock/conrol regisers. (Noe: Prior o wriing o he R, he maser mus wrie a 02h, hen 06h o he saus regiser in wo preceding operaions o enable he wrie operaion. See Wriing o he lock/onrol Regisers. fer he receip of each bye, he X1288 responds wih an acknowledge, and he address is inernally incremened by one. When he couner reaches he end of he page, i rolls over and goes back o he firs address on he same page. This means ha he maser can wrie 128 byes o a memory array page or 8 byes o a R secion saring a any locaion on ha page. For example, if he maser begins wriing a locaion 105 of he memory and loads 30 byes, hen he firs 23 byes are wrien o addresses 105 hrough 127, and he las 7 byes are wrien o columns 0 hrough 6. ferwards, he address couner would poin o locaion 7 on he page ha was jus wrien. If he maser supplies more han he maximum byes in a page, hen he previously loaded daa is over wrien by he new daa, one bye a a ime. Refer o Figure 13. The maser erminaes he Daa Bye loading by issuing a sop condiion, which causes he X1288 o begin he nonvolaile wrie cycle. s wih he bye wrie operaion, FN8102 Rev 3.00 Page 19 of 27
Signals from he Maser S a r Slave ddress Word ddress 1 Word ddress 0 1 n 128 for EEPROM array 1 n 8 for R Daa (1) Daa (n) S o p SD Bus 1 1 1 1 0 0 Signals from he Slave FIGURE 14. PGE WRITE SEQUEE all inpus are disabled unil compleion of he inernal wrie cycle. Refer o Figure 14 for he address, acknowledge, and daa ransfer sequence. Sops and Wrie Modes Sop condiions ha erminae wrie operaions mus be sen by he maser afer sending a leas 1 full daa bye and i s associaed signal. If a sop is issued in he middle of a daa bye, or before 1 full daa bye + is sen, hen he X1288 reses iself wihou performing he wrie. The conens of he array are no affeced. cknowledge Polling Disabling of he inpus during nonvolaile wrie cycles can be used o ake advanage of he ypical 5mS wrie cycle ime. Once he sop condiion is issued o indicae he end of he maser s bye load operaion, he X1288 iniiaes he inernal nonvolaile wrie cycle. cknowledge polling can begin immediaely. To do his, he maser issues a sar condiion followed by he Slave ddress Bye for a wrie or read operaion. If he X1288 is sill busy wih he nonvolaile wrie cycle hen no will be reurned. When he X1288 has compleed he wrie operaion, an is reurned and he hos can proceed wih he read or wrie operaion. Refer o he flow char in Figure 16. Read Operaions There are hree basic read operaions: urren ddress Read, Random Read, and Sequenial Read. urren ddress Read Inernally he X1288 conains an address couner ha mainains he address of he las word read incremened by one. Therefore, if he las read was o address n, he nex read operaion would access daa from address n+1. On power-up, he sixeen bi address is iniialized o 0h. In his way, a curren address read immediaely afer he power-on rese can download he enire conens of memory saring a he firs locaion.upon receip of he Slave ddress Bye wih he R/W bi se o one, he X1288 issues an acknowledge, hen ransmis eigh daa bis. The maser erminaes he read operaion by no responding wih an acknowledge during he ninh clock and issuing a sop condiion. Refer o Figure 15 for he address, acknowledge, and daa ransfer sequence. Signals from he Maser S a r Slave ddress S o p SD Bus 1 1 1 1 1 Signals from he Slave Daa FIGURE 15. URRENT DDRESS RED SEQUEE FN8102 Rev 3.00 Page 20 of 27
Bye load compleed by issuing STOP. Ener Polling Issue STRT Issue Slave ddress Bye (Read or Wrie) Issue STOP The maser issues he sar condiion and he slave address bye, receives an acknowledge, hen issues he word address byes. fer acknowledging receip of each word address bye, he maser immediaely issues anoher sar condiion and he slave address bye wih he R/W bi se o one. This is followed by an acknowledge from he device and hen by he eigh bi daa word. The maser erminaes he read operaion by no responding wih an acknowledge and hen issuing a sop condiion. Refer o Figure 17 for he address, acknowledge, and daa ransfer sequence. reurned? YES nonvolaile wrie ycle complee. oninue command sequence? YES oninue normal Read or Wrie command sequence PROEED I should be noed ha he ninh clock cycle of he read operaion is no a don care. To erminae a read operaion, he maser mus eiher issue a sop condiion during he ninh cycle or hold SD HIGH during he ninh clock cycle and hen issue a sop condiion. Random Read Random read operaions allows he maser o access any locaion in he X1288. Prior o issuing he Slave ddress Bye wih he R/W bi se o zero, he maser mus firs perform a dummy wrie operaion. NO NO Issue STOP FIGURE 16. NOWLEDGE POLLING SEQUEE In a similar operaion called Se urren ddress, he device ses he address if a sop is issued insead of he second sar shown in Figure 17. The X1288 hen goes ino sandby mode afer he sop and all bus aciviy will be ignored unil a sar is deeced. This operaion loads he new address ino he address couner. The nex urren ddress Read operaion will read from he newly loaded address. This operaion could be useful if he maser knows he nex address i needs o read, bu is no ready for he daa. Sequenial Read Sequenial reads can be iniiaed as eiher a curren address read or random address read. The firs daa bye is ransmied as wih he oher modes; however, he maser now responds wih an acknowledge, indicaing i requires addiional daa. The device coninues o oupu daa for each acknowledge received. The maser erminaes he read operaion by no responding wih an acknowledge and hen issuing a sop condiion. The daa oupu is sequenial, wih he daa from address n followed by he daa from address n + 1. The address couner for read operaions incremens hrough all page and column addresses, allowing he enire memory conens o be serially read during one operaion. he end of he address space he couner rolls over o he sar of he address space and he X1288 coninues o oupu daa for each acknowledge received. Refer o Figure 18 for he acknowledge and daa ransfer sequence. FN8102 Rev 3.00 Page 21 of 27