Progress in full field EUV lithography program at IMEC

Similar documents
IMEC update. A.M. Goethals. IMEC, Leuven, Belgium

Lithography Roadmap. without immersion lithography. Node Half pitch. 248nm. 193nm. 157nm EUVL. 3-year cycle: 2-year cycle: imec 2005

Eun-Jin Kim, GukJin Kim, Seong-Sue Kim*, Han-Ku Cho*, Jinho Ahn**, Ilsin An, and Hye-Keun Oh

EUVL getting ready for volume introduction

2009 International Workshop on EUV Lithography

2008 European EUVL. EUV activities the EUVL shop future plans. Rob Hartman

22nm node imaging and beyond: a comparison of EUV and ArFi double patterning

R&D Status and Key Technical and Implementation Challenges for EUV HVM

EUV Lithography Transition from Research to Commercialization

TSMC Property. EUV Lithography. The March toward HVM. Anthony Yen. 9 September TSMC, Ltd

The future of EUVL. Outline. by Winfried Kaiser, Udo Dinger, Peter Kuerz, Martin Lowisch, Hans-Juergen Mann, Stefan Muellender,

EUV: Status and Challenges Ahead International Workshop on EUVL, Maui 2010

Defect printability of thin absorber mask in EUV lithography with refined LER resist

Status and challenges of EUV Lithography

Spring of EUVL: SPIE 2012 AL EUVL Conference Review

EUV lithography: status, future requirements and challenges

EUVL Scanners Operational at Chipmakers. Skip Miller Semicon West 2011

Nikon EUVL Development Progress Update

Optics for EUV Lithography

From ArF Immersion to EUV Lithography

Impact of 3-D Mask Effects on CD and Overlay over Image Field in Extreme Ultraviolet Lithography

SEMATECH Defect Printability Studies

EUV Resist Materials and Process for 16 nm Half Pitch and Beyond

Advanced Patterning Techniques for 22nm HP and beyond

Evaluation of Technology Options by Lithography Simulation

EUV Light Source The Path to HVM Scalability in Practice

TECHNOLOGY ROADMAP 2006 UPDATE LITHOGRAPHY FOR

Towards an affordable Cost of Ownership for EUVL. Melissa Shell Principal Engineer & Program Manager, EUVL Research Components Research October 2006

Holistic View of Lithography for Double Patterning. Skip Miller ASML

Business Unit Electronic Materials

High-NA EUV lithography enabling Moore s law in the next decade

Novel EUV Resist Development for Sub-14nm Half Pitch

Update on 193nm immersion exposure tool

Shot noise and process window study for printing small contacts using EUVL. Sang Hun Lee John Bjorkohlm Robert Bristol

Lithography Industry Collaborations

immersion optics Immersion Lithography with ASML HydroLith TWINSCAN System Modifications for Immersion Lithography by Bob Streefkerk

MASK 3D EFFECTS FIRST EXPERIMENTAL MEASUREMENTS WITH NA 0.55 ANAMORPHIC IMAGING

EUV Interference Lithography in NewSUBARU

EUVL: Challenges to Manufacturing Insertion

Immersion Lithography: New Opportunities for Semiconductor Manufacturing

Holistic Lithography. Christophe Fouquet. Executive Vice President, Applications. 24 November 2014

Shooting for the 22nm Lithography Goal with the. Coat/Develop Track. SOKUDO Lithography Breakfast Forum 2010 July 14 (L1)

Mask Technology Development in Extreme-Ultraviolet Lithography

UV Nanoimprint Stepper Technology: Status and Roadmap. S.V. Sreenivasan Sematech Litho Forum May 14 th, 2008

Discovering Electrical & Computer Engineering. Carmen S. Menoni Professor Week 3 armain.

Flare compensation in EUV lithography

Actinic Review of EUV Masks: Performance Data and Status of the AIMS TM EUV System

Imaging for the next decade

Process Optimization

Progress towards Actinic Patterned Mask Inspection. Oleg Khodykin

Comparative Study of Binary Intensity Mask and Attenuated Phase Shift Mask using Hyper-NA Immersion Lithography for Sub-45nm Era

* AIT-5: Maskless, High-NA, Immersion, EUV, Imprint

Optical Microlithography XXVIII

5. Lithography. 1. photolithography intro: overall, clean room 2. principle 3. tools 4. pattern transfer 5. resolution 6. next-gen

Analysis of Focus Errors in Lithography using Phase-Shift Monitors

Imec pushes the limits of EUV lithography single exposure for future logic and memory

EUVL Activities in China. Xiangzhao Wang Shanghai Inst. Of Opt. and Fine Mech. Of CAS. (SIOM) Shanghai, China.

Jung Sik Kim, Seongchul Hong, Jae Uk Lee, Seung Min Lee, and Jinho Ahn*

Photolithography. References: Introduction to Microlithography Thompson, Willson & Bowder, 1994

OPC Rectification of Random Space Patterns in 193nm Lithography

Double Patterning Combined with Shrink Technique to Extend ArF Lithography for Contact Holes to 22nm Node and Beyond

Scope and Limit of Lithography to the End of Moore s Law

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

Optical Lithography. Keeho Kim Nano Team / R&D DongbuAnam Semi

Challenges of EUV masks and preliminary evaluation

Registration performance on EUV masks using high-resolution registration metrology

450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.

ECSE 6300 IC Fabrication Laboratory Lecture 3 Photolithography. Lecture Outline

EUV lithography: today and tomorrow

Mask magnification at the 45-nm node and beyond

Computational Lithography Requirements & Challenges for Mask Making. Naoya Hayashi, Dai Nippon Printing Co., Ltd

EUV Substrate, Blank, and Mask Flatness Current Specifications & Issues Overview

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

Copyright 2000, Society of Photo-Optical Instrumentation Engineers This paper was published in Optical Microlithography XIII, Volume 4000 and is made

Optimizing FinFET Structures with Design-based Metrology

Advanced Stepper Lithography Technology to Enable Flexible AMOLED Displays. Keith Best Roger McCleary Elvino M da Silveira 5/19/17

Light Sources for EUV Mask Metrology. Heiko Feldmann, Ulrich Müller

Introducing 157nm Full Field Lithography

Key Photolithographic Outputs

Feature-level Compensation & Control

EUVL: Challenges to Manufacturing Insertion

MICROCHIP MANUFACTURING by S. Wolf

Closed Loop Registration Control (RegC ) Using PROVE as the Data Source for the RegC Process

INTERNATIONAL TECHNOLOGY ROADMAP SEMICONDUCTORS 2001 EDITION LITHOGRAPHY FOR

EUVL Challenges for Next Generation Devices

Recent Activities of the Actinic Mask Inspection using the EUV microscope at Center for EUVL

Optical Lithography. Here Is Why. Burn J. Lin SPIE PRESS. Bellingham, Washington USA

Managing Within Budget

EUV Micro-Exposure Tool (MET) for Near-Term Development Using a High NA Projection System

Comparison of actinic and non-actinic inspection of programmed defect masks

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven

Benefit of ArF immersion lithography in 55 nm logic device manufacturing

Scaling of Semiconductor Integrated Circuits and EUV Lithography

EUV Source for High Volume Manufacturing: Performance at 250 W and Key Technologies for Power Scaling

ASML s customer magazine

MICROBUMP LITHOGRAPHY FOR 3D STACKING APPLICATIONS

Light Source Technology Advances to Support Process Stability and Performance Predictability for ArF Immersion Double Patterning

Lithography on the Edge

Double Patterning Combined with Shrink Technique to Extend ArF Lithography for Contact Holes to 22nm Node and Beyond

Reducing Proximity Effects in Optical Lithography

Transcription:

Progress in full field EUV lithography program at IMEC A.M. Goethals*, G.F. Lorusso*, R. Jonckheere*, B. Baudemprez*, J. Hermans*, F. Iwamoto 1, B.S. Kim 2, I.S. Kim 2, A. Myers 3, A. Niroomand 4, N. Stepanenko 5, F. Van Roey*, I. Pollentier* and K. Ronse* *IMEC, Leuven, Belgium 1 On assignment from Matsushita 2 On assignment from Samsung 3 On assignment from Intel 4 On assignment from Micron 5 On assignment from Qimonda International EUVL Symposium, 28-31 October 2007, Sapporo

EUVL program contents vs EUV critical issues 3 projects EUV masks Handling Defect free in fab ADT assessment EUV Source Power, lifetime Reflective optics Quality and lifetime EUV EUV resist resists process Sensitivity, LER, resolution 2

EUVL program contents EUV resists EUV Masks ADT assessment EUV Source Power, lifetime Reflective optics Quality and lifetime Resist Resist process Sensitivity, LER, resolution 3

EUV resist project Key objectives EUV resists Benchmark EUV resist performance versus requirements Drive EUV resist suppliers Demonstrate EUVL ability for small electrically working circuits Build fundamental understanding for EUV resist out-gassing requirements for EUVL high volume manufacturing 50nm 40nm 30nm 25nm Resist Screening at PSI RGA Energetiq source in close collaboration with all major resist suppliers worldwide Optics chamber Process Wfr/reticle chamber loadlock EUV Technology Outgassing Tool 4

Reference resist (Interference litho) MET-2D, 80nm resist thickness 50 nm (80nm thick) +-104 nm 30nm 45 nm 25nm 40 nm +-100 nm 32.5 nm +-97 nm Energy size Exp. Lat. (50nm) LER (3σ) (50nm) Resolution 21.4 mj/cm 2 13% 5.1nm 80 nm 32.5 nm 5

Line Edge Roughness versus sensitivity LER results on 50nm lines (Interference lithography) 12 10 25nm resolved 3 sigma LER [nm] 8 6 4 2 MET-2D ITRS Target 0 0.0 10.0 20.0 30.0 40.0 50.0 dose [mj/cm2] Poster RE-P10 EUV resist process development for full field imaging, A. Niroomand et al 6

Line Edge Roughness versus sensitivity LER results on 50nm lines (Interference lithography) 12 10 EUV-77 EUV-55 25nm resolved 3 sigma LER [nm] 8 6 4 2 EUV-72 EUV-38 MET-2D EUV-73 ITRS Target 0 0.0 10.0 20.0 30.0 40.0 50.0 dose [mj/cm2] Best overall performing resist is EUV-72 (high sensitivity with ~25nm resolution). Poster RE-P10 EUV resist process development for full field imaging, A. Niroomand et al 7

State of the art resist Q3 2006 EUV-38 resist 50 nm +-104 nm 30nm 45 nm 25nm 40 nm +-100 nm 32.5 nm +-97 nm Energy size Exp. Lat. (50nm) LER (3σ) (50nm) Resolution 14.8 mj/cm 2 26% 5.2nm 25nm 50 nm 8

Overall best resist Q3 2007 EUV-72 resist 50 nm +-104 nm 30nm 45 nm 25nm 40 nm +-100 nm 32.5 nm +-97 nm Energy size Exp. Lat. (50nm) LER (3σ) (50nm) Resolution 9.6 mj/cm 2 27% 5.9nm 50 nm ~25 nm 9

EUVL program contents EUV reticles Project EUV EUV Masks Masks Handling in fab ADT assessment EUV Source Power, lifetime Reflective optics Quality and lifetime Resist Sensitivity, LER, resolution 10

EUV reticle project Key objectives 2. EUV masks Benchmark EUV reticle performance versus requirements and blank architecture Build understanding on handling requirements for EUV mask lifetime in fab environment Build understanding on EUV mask defect specs requirements for defect free lithography Reflectivity (%) 0.8 Si Mo 0.75 0.7 0.65 Ru Si 0.6 0.55 Ru 0.5 Mo 0.45 0.4 0 2 4 6 8 10 12 14 Cap thickness Blank reflectivity simulation in close collaboration with all major EUV mask (and blank) suppliers worldwide (including captive mask shops core partners) TNO Particle Scanner 11

Particle defect: variation of n&k 40nm L/S Cubic defect Space Width [nm] 40 38 36 34 32 Space Width [nm] 40 38 36 34 32 0 5 10 15 20 Defect Size [nm] 0 5 10 15 20 Defect Size [nm] Material (n,k) C (1,0.001) (1,0.08) (0.85,0.001) (0.85,0.08) TaN SiO2 Cr Mo Si Ru C The particle material determines its printability. oral DI-01 Mask defect printability in full field EUV lithography, R. Jonckheere 12

Printability study of 4 types of mask defects by simulation Particle eg Carbon or opaque materials defect Critical particle size is ~14nm for C Printability depends on (n,k) Absorber defect Opaque & clear type Critical opaque defect size: is ~8nm Critical distance is typically 2-3X smaller than in ArF Local R%-loss Local carbon deposition If conformal it prints very quickly (from 2nm thickness onwards) ML defect Major effect from multilayer distortion near top (phase defects ~2-3nm). Material dependence only when the defect is located near the surface. Oral DI-01 Mask defect printability in full field EUV lithography, R. Jonckheere 13

EUV reticle long term reflectivity (degradation) Blank Reflectivity Si cap thickness 4nm Si keeps R±0.5% up to ~3nm C C deposition Si cap Mo Si 8nm Si: 3nm C gives 6% reflectivity loss Carbon thickness (nm) Protective mask capping layer (Si or Ru) and thickness can be optimized to minimize/maximize the sensitivity carbon deposition. Poster MC-P03 Study of capping layer impact on reflectivity loss by carbon deposition, Rik Jonckheere et al 14

EUVL program contents EUV ADT assessment project EUV Masks ADT assessment ADT assessment EUV Source Power, lifetime Reflective optics Quality and lifetime Resist Sensitivity, LER, resolution 15

EUV ADT assessment project Key objectives EUV alpha tool assessment Detailed characterization of EUV ADT fingerprint in terms of Imaging Overlay (single machine and matched machine) Detailed stability monitoring of EUV ADT In terms of optics contamination (image degradation) In terms of reliability and up-time (CoO) Develop and demonstrate correction techniques to compensate for EUV shadowing and flare Shadowing Compensation Flare map in close collaboration with ASML Flare map 16

ASML EUV Alpha Demo Tool (ADT) at IMEC First Light Apr 2007 Arrival Aug 2006 installed by Dec 2006 First Wafer May 2007 17

ASML EUV Alpha Demo Tool First imaging with Sn source 50nm 1:1 40nm 1:1 35nm 1:1 CD=47.3nm CD=34nm Resist: Rohm Haas MET-2D Thickness 100nm NA=0.25, σ=0.5 Lens aberration reduction not finalized yet 18

ADT imaging 50nm V and H lines through dose 17.05 mj 17.3 mj 17.55 mj 17.8mJ 18.05mJ 18.3mJ 18.55mJ Vertical lines 57.3nm 59.6nm 52.6nm 52.7nm 51.2nm Horizontal lines 45.6nm 46.1nm 61.9nm 58.3nm 55.8nm 56.4nm 53.8nm 51.6nm 52.4nm Resist: Rohm Haas MET-2D Thickness 100nm NA=0.25, σ=0.5 Lens aberration reduction not finalized yet 19

ADT imaging 50nm V and H lines through focus Vertical L/S Horizontal L/S >160nm DOF Resist: Rohm Haas MET-2D Thickness 100nm NA=0.25, σ=0.5 Lens aberration reduction not finalized yet >240nm DOF 20

ADT imaging 40nm V and H lines through dose 17.55 mj 17.8mJ 18.05mJ 18.3mJ 18.55mJ Vertical lines 42.8nm 40.9nm 38.2nm 33.6nm 34.2nm Horizontal lines 44.5nm 44.4nm 41.3nm 40.6nm 40.5nm Resist: Rohm Haas MET-2D Thickness 100nm Resist: Rohm Haas MET-2D NA=0.25, σ=0.5 Thickness 100nm Lens aberration reduction not finalized yet 21

ADT imaging 35nm V and H lines through dose 18.05mJ/cm 2 18.3mJ/cm 2 18.55mJ/cm 2 Vertical lines 39.1nm 37.nm 37.8nm Horizontal lines 44.3nm 43.8nm 43.5nm Resist: Rohm Haas MET-2D Thickness 100nm NA=0.25, σ=0.5 Lens aberration reduction not finalized yet 22

Shadowing on ASML EUV ADT with Sn Source Experimental validation 10 H-V experiment 45-135 experiment 10 H-V simulation 45-135 simulation Bias (nm) 0 Bias (nm) 0-10 -20-10 0 10 20-10 -20-10 0 10 20 Slit Position (mm) Slit Position (mm) Measurement of 50nm 1:1 L/S at 0 0, 90 0, 45 0, 135 0 Comparison of simulation and experiment for HV bias and 45 0-135 0 bias through slit The experimental measurement of shadowing is in agreement with simulation prediction. Poster MA-P08 Shadowing effect compensation, G.F. Lorusso et al 23

Flare mitigation strategy Quantifying the quality of rule-based flare correction 40 Linear dependence of CD on flare 42 CD variation across die 35 40 CD (nm) 30 25 20 CD CD corrected = CDt arget + * Flare Flare local CD (nm) 38 36 34 32 15 0 5 10 15 Flare (%) 30 0 500 1000 1500 2000 Site (#) CD Uncorrected CD Flare-corrected - not fractured CD Flare-corrected Fractured CD Flare-corrected Fractured Iterated on Flare Rule based correction re-sizes the CD at mask level to remove flare artifacts and seems very effective High-quality Full-Chip Flare map critical to implement rule-based Simulation SOLID-EUV 24

Full Chip Flare Map Density map with dummification Flare map 68 hrs High resolution full chip flare map can be calculated in reasonable time with standard EDA SW. oral OP-03 Flare mitigation strategies for EUV, A. Myers 25

Summary and outlook 1 st high resolution images demonstrated with ASML ADT equipped with a Sn source EUV resists are making steady progress Resolution of 25nm HP demonstrated with interference litho for several materials and sensitivities are reaching the 10mJ/cm 2 target LER is remaining the major challenge EUV reticles Extensive simulation study of defect printability and mask reflectivity Experimental phase in preparation with wide mask shop involvement Feasible Flare and Shadowing compensation strategies have been developed based on simulation. EUV ADT @ IMEC is getting ready for experimental verification Full field EUV Lithography is becoming reality 26

Acknowledgements Many thanks to: ASML Noreen Harned, Hans Meiling, John Zimmerman, Bas Hultermans ASML EUV team at IMEC Age Bakker, Leon Romijn, Charles Schaap, Andre Van Dijk Sjoerd Lok, Joop Van Dijck Sigma-C (Synopsys) Brian Ward IMEC Tom Vandeweyer, Geert Vandenberghe PSI Harun Solak, Anja Weber Resist and BARC suppliers Mask shops IMEC IIAP partners 27

28