EISCAT_3D Digital Beam-Forming and Multi-Beaming

EISCAT_3D Digital Beam-Forming and Multi-Beaming

The phased array principle: Arrange matters such that the signals from all antennas R1 Rn are in phase at the wavefront W Constructive interference in a direction normal to W BEAM DIRECTION W A beam forms in the ε 0 direction! 3 D cos ε 0 2 D cos ε 0 D cos ε 0 N ε 0 D R1 R4 R12

When the individual antennas have directivity, the principle of superposition applies: The pattern of the individual antenna: multiplied by the interferometer pattern: E a (ε) = sin [ N π D / λ(sin ε -sin ε 0 )] / sin [ π D / λ(sin ε -sin ε 0 )] forms the final array pattern: Note the sidelobes! By manipulating (i.e. phasing or delaying) the signals to the individual antennas, we can tilt W to different angles ε 1, ε 2, ε 3 ε 0 - and as long as the new directions fall inside the pattern of the individual antenna, a beam will be formed!

Digital time-delay beam-steering Time-delay beam-steering (TDS) will be used throughout the EI_3D system, as opposed to modulo-2π phase steering, for the following reasons: The 3D system will be employing large BW modulations (up to 5 MHz), Plasma line reception at frequency offsets of up to ±15 MHz (±7% of the center frequency) at large offboresight angles will be a routine feature, in particular at the remote sites, But phase steering modulo-2π is dispersive, i.e. the beam direction is a function of the frequency offset, so won t work in our case! OTOH, TDS is non-dispersive and will maintain the beam direction irrespective of frequency offset! The problem: When implementing the TDS system for the 3D radar, we must find a reliable way to resolve time down to the sub-nanosecond level: The target value for the beam pointing resolution is 0.625 o in each of two orthogonal planes. This requires that the element-to-element delay be settable to a resolution of 0.018 (1/ 2) ns = 12.7 picoseconds! BUT- the sampling will be running at about 80 MHz / 12.5 ns per sample (10 3 times longer!); how to reconcile?

The solution: Better than 10 ps time resolution can be achieved by inserting so-called fractional sample delay (FSD) filters in the signal paths. FSD basics: If a band-limited signal is sampled at the Nyqvist rate for a sufficiently long time, the sample series can be interpolated to find the signal value at any intermediate time, down to an arbitrary fraction of a sample interval. Practical realisation: An all-pass FIR filter, whose coefficients are selected to make it work as and interpolator producing the required delay at the output. Extensive Matlab simulations have shown that 48-tap FIR filters can be designed to provide almost constant group delay across the full 3D receiving bandwidth (30 MHz), albeit with some residual amplitude ripple in the passband; the FSD technique really does work with _3D parameters! References: 1. Murphy, N.P., A. Krukowski and I. Kale, Implementation of a Wide-Band Integer and Fractional Delay Element, Electronics Letters, 30, No. 20, pp. 1658-1659 (1994) 2. Murphy, N.P., A. Krukowski and A. Tarczynski, An Efficient Fractional Sample Delayer for Digital Beam Steering, Proceedings of ICASSP 97 (1997)

Digital beam-forming, multi-beaming and beam errors A digital beam-former (BF) consists of two main parts, viz. a set of fractional sample delay (FSD) units and a full- adder ( ). 16 BF s 0 s -1 s -2 s -3 s -n FSD c -1 X c -2 X c -3 X c -n X One FSD unit is required per element antenna and beam. It can be realised as a generic FIR filter structure in FPGA logic. The coefficients c -m, m= 1 n, determine the filter group delay and must be computed for each element antenna and beam direction. Summing the delayed outputs from all FIR filters in the full-adder generates the beamformed data stream. U -1 Beam-formed data Multiple beams can be generated from the same data by simply adding more beam-formers, one per beam! ADC timing jitter and other timing errors affect the beam, but when the error distribution is Gaussian, the average pointing direction stays the same regardless of the width of the distribution. On the other hand, Gaussian timing jitter causes a widening of the beam and a loss of gain. A 3-σ jitter of 100 ps results in a 0.1 db gain loss; 500 ps jitter results in almost 2 db gain loss! Clock distribution and ADC sampling stabilisation now become important issues; in order not to lose performance, the system must be designed for a 3-σ jitter of less than 100 ps, array-wide.

Block diagram of fully instrumented Demonstrator RX front end / beam-former Four RX front ends per digital down-converter unit Digital down-converter (ASIC) RF 235 MHz From Level 1 Direct-sampling RX (discrete WP 4/LTU Analog BPF BW max. 30 MHz ADC_CLK 80 MHz e iωt Digital LPF BW max. 1 MHz Decimator 80 (1+1) Ms/s LNA Amp Postamp ADC 80 Ms/s WP 9 / 16 WP 12 WP 12 WP 12 FPGA SERDES / Media converter (copper/optical) Optical fibre SERDES / Media converter (optical / copper) Beamformer To UHF RX WP 9 This architecture was adopted to get the Demonstrator array operational as quickly as possible: The digital down-converter unit band-limits the 30 MHz front end signal to 1 MHz, enough for ion line work, Decimated data from all rows is serialised, media-converted and transferred on optical fibre to the site control room, Multiple beam-former processes running in an FPGA combine signals from all rows into beam-formed data streams, These are fed into the existing UHF receiver channel boards and processed normally by lag_wrap under eros.

How the FIR filters are realised in practice: FPGA technology

The combination of direct sampling and digital FSD beam-forming brings some important advantages: A large number of beams in different directions can be generated truly simultaneously, The number of beams is essentially only limited by money, i.e. by how many beam-formers have been installed, The beam-forming process is lossless, i.e. all beams can observe for 100 % of real-time!

When observing the D and E regions, self-clutter from the F region may sometimes make it impossible to reach the desired 1-s, 10% n e time resolution in mono-static mode: To first order: n e /n e P S /P S (1 + SNR -1 )/ (b N τ t) where b is the measurement bandwidth (typically 5 khz), N is the number of radar cycles / unit time (100 200), τ is the pulse length (~ 500 µs), and t is the measurement time (1 s). However, when using a coded transmission with n bits in the code, the effective SNR goes asymptotically towards n -1 as the signal strength increases this is because the self clutter from illuminated plasma outside the volume of interest eventually begins to dominate over thermal and receiver noise. It follows that for a typical modulation using 16 bit codes, the effective mono-static SNR can never exceed ~ 6.7 %, no matter what the electron density Then, under the above conditions P S /P S (t = 1 s) 100 % as SNR! BUT:

In these cases, the multi-static, multi-beam system configuration comes to the rescue: Looking into the illuminated beam from the side with a remote receiving beam resolution ~ 1 km, the self-clutter is effectively suppressed. The SNR can then go as high as 50 %, leading to P S /P S (t = 1 s, remote) 14 %, that is, very close to the performance target! With smart signal processing, multiple intersecting remote beams (>one per scale height) can be formed from the same set of sample-level data from the RX array It will become possible, for the first time, to reconstruct the true instantaneous vector E field through the whole ionosphere!