9-362; Rev 3; 6/7 Quad, SPST Analog Switch General Description The quad analog switch features on-resistance matching (4Ω max) between switches and guarantees on-resistance flatness over the signal range (9Ω max). This low on-resistance switch conducts equally well in either direction. It guarantees low charge injection (pc max), low power consumption (35µW max), and an electrostatic discharge (ESD) tolerance of 2V minimum per Method 35.7. The new design offers lower off-leakage current over temperature (less than 5nA at +85 C). The quad, single-pole/single-throw (SPST) analog switch has two normally closed switches and two normally open switches. Switching times are less than 25ns for ton and less than 7ns for toff. Operation is from a single +4.5V to +4V supply or bipolar ±4.5V to ±2V supplies. Applications Sample-and-Hold Circuits Test Equipment Heads-Up Displays Guidance and Control Systems Military Radios Communication Systems Battery-Operated Systems PBX, PABX Audio Signal Routing Modems/Faxes Features Pin Compatible with Industry-Standard DG23 Guaranteed R ON Match Between Channels (4Ω max) Guaranteed R FLAT(ON) Over Signal Range (9Ω max) Guaranteed Charge Injection (pc max) Low Off-Leakage Current Over Temperature (<5nA at +85 C) Withstands 2V min ESD, per Method 35.7 Low R DS(ON) (85Ω max) Single-Supply Operation +4.5V to +4V Bipolar-Supply Operation ±4.5V to ±2V Low Power Consumption (35µW max) Rail-to-Rail Signal Handling TTL/CMOS-Logic Compatible Pin Configurations/ Functional Diagrams/TruthTable TOP VIEW S S4 2 3 4 D 6 5 4 3 5 D4 IN 6 IN4 IN2 7 IN3 THIN QFN *EP D2 8 D3 2 S2 *EP = EXPOSED PAD, CONNECT EP TO Pin Configurations continued at end of data sheet. 9 S3 Ordering Information PART TEMP RANGE PIN-PACKAGE CPE C to +7 C 6 Plastic DIP CSE C to +7 C 6 Narrow SO CEE C to +7 C 6 QSOP CUE C to +7 C 6 TSSOP** CC/D C to +7 C Dice* ETE -4 C to +85 C 6 TQFN-EP*** (5mm x 5mm) EPE -4 C to +85 C 6 Plastic DIP ESE -4 C to +85 C 6 Narrow SO EEE -4 C to +85 C 6 QSOP EUE -4 C to +85 C 6 TSSOP** *Contact factory for dice specifications. **Contact factory for availability. ***EP = Exposed Pad Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at -888-629-4642, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS Voltage Referenced to...+44v...-44v to...+44v...( -.3V) to ( +.3V) Digital Inputs V V (Note )...( - 2V) to ( + 2V) or 3mA (whichever occurs first) Continuous Current (any terminal)...3ma Peak Current, or (pulsed at ms, % duty cycle max)...ma Continuous Power Dissipation (T A = +7 C) Plastic DIP (derate.53mw/ C above +7 C)...842mW Narrow SO (derate 8.7mW/ C above +7 C)...696mW QSOP (derate 8.3mW/ C above +7 C)...667mW Thin QFN (derate 33.3mW/ C above +7 C)...2667mW TSSOP (derate 6.7mW/ C above +7 C)...457mW Operating Temperature Ranges C... C to +7 C E...-4 C to +85 C Storage Temperature Range...-65 C to +65 C Lead Temperature (soldering, sec)...+3 C Note : Signals on,, or exceeding or are clamped by internal diodes. Limit forward current to maximum current rating. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supplies ( = 5V, =, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Analog Signal Range V ANALOG (Note 3) -5 5 V Drain-Source On-Resistance R DS(ON) V D = ±V, 55 7 I S = ma T A = T MIN to T MAX 85 Ω On-Resistance Match V 4 ΔR D = ±V, Between Channels (Note 4) DS(ON) I S = ma T A = T MIN to T MAX 5 Ω On-Resistance Flatness (Note 4) R FLAT(ON) V D = ±5V, 9 I S = ma T A = T MIN to T MAX 5 Ω Source Leakage Current V D = ±4V, -.5..5 IS(OFF) (Note 5) V S = 4V na Drain-Off Leakage Current (Note 5) Drain-On Leakage Current (Note 5) Input Current with Input Voltage High Input Current with Input Voltage Low ID(OFF) I D(ON) or I S(ON) I INH ± V D = ±4V, V S = 4V ± V D = ±4V, V S = ±4V V IN = 2.4V, all others =.8V -.5..5 -.5.8.5 T A = T MIN to T MAX - -.5 -..5 I INL V IN =.8V, all others = 2.4V -.5 -..5 SUPPLY Power-Supply Range, ±4.5 ±2. V Positive Supply Current I+ -. V IN = or 5V Negative Supply Current I- -. V IN = or 5V 2 na na
ELECTRICAL CHARACTERISTICS Dual Supplies (continued) ( = 5V, =, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Logic Supply Current I L -. V IN = or 5V Ground Current I - -. V IN = or 5V DYNAMIC Turn-On Time (Note 3) t ON V S = ±V, Figure 2 5 25 ns Turn-Off Time (Note 3) t OFF V S = ±V, Figure 2 9 2 ns Break-Before-Make Time Delay (Note 3) t D Figure 3 5 2 ns Charge Injection (Note 3) Off-Isolation Rejection Ratio (Note 6) C L = nf, V GEN =, Q 5 pc R GEN =, Figure 4 R L = 5Ω, C L = 5pF, OIRR 6 db f = MHz, Figure 5 Crosstalk (Note 7) R L = 5Ω, C L = 5pF, f = MHz, Figure 6 db Source-Off Capacitance C S(OFF) f = MHz, Figure 7 4 pf Drain-Off Capacitance C D(OFF) f = MHz, Figure 7 4 pf Source-On Capacitance C S(ON) f = MHz, Figure 8 6 pf Drain-On Capacitance C D(ON) f = MHz, Figure 8 6 pf ELECTRICAL CHARACTERISTICS Single Supply ( = 2V, = V, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX (Note 2) UNITS Analog Signal Range V ANALOG 2 V Drain-Source = 5V; V D = 3V, 8V; 6 R On-Resistance DS(ON) I S = ma T A = T MIN to T MAX 2 Ω SUPPLY Power-Supply Range, 4.5 4 V Power-Supply Current I+ -. V IN = or 5V Negative Supply Current I- - -. V IN = or 5V Logic Supply Current I L -. V IN = or 5V Ground Current I - -. V IN = or 5V 3
ELECTRICAL CHARACTERISTICS Single Supply (continued) ( = 2V, =, = 5V, = V, V INH = 2.4V, V INL =.8V, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER DYNAMIC Turn-On Time (Note 3) Turn-Off Time (Note 3) Charge Injection (Note 3) SYMBOL t ON t OFF Q V S = 8V, Figure 2 V S = 8V, Figure 2 C L = nf, V GEN =, R GEN =, Figure 4 CONDITIONS MIN TYP MAX (Note 2) 3 4 6 2 5 UNITS ns ns pc Note 2: Typical values are for design aid only, are not guaranteed and are not subject to production testing. The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: Guaranteed by design. Note 4: On-resistance match between channels and flatness are guaranteed only with bipolar-supply operation. Flatness is defined as the difference between the maximum and the minimum value of on-resistance as measured at the extremes of the specified analog signal range. Note 5: Leakage parameters I S(OFF), I D(OFF), I D(ON), and I S(ON) are % tested at the maximum rated hot temperature and guaranteed at +25 C. Note 6: Off-Isolation Rejection Ratio = 2log (V D /V S ). Note 7: Between any two switches. Typical Operating Characteristics (, unless otherwise noted.) ON LEAKAGE (na) RDS(ON) (Ω) 2 - T A = +85 C ON LEAKAGE CURRENTS T A = +25 C = 5V = -2-5 - -5 5 5 V S, 5 25 75 5 25 ON-RESISTANCE vs. V D (UNIPOLAR SUPPLY VOLTAGE) = 5V = V = 5V = 2V - -4 RDS(ON) (Ω) OFF LEAKAGE (na).5 -.5-2 9 6 3 OFF LEAKAGE CURRENTS T A = +85 C -5 - -5 5 5 V S, T A = +25 C = 5V = ON-RESISTANCE vs. V D (BIPOLAR SUPPLY VOLTAGE) V± = ±5V V± = ±V V± = ±5V V± = ±2V -2-5 VIN (V) RDS(ON) (Ω) 3.5 3. 2.5 2..5.5 ING THRESHOLD vs. BIPOLAR SUPPLY VOLTAGE IN HIGH MIN IN LOW MAX ±5 ± ±5 ±2 BIPOLAR SUPPLY VOLTAGE (V) 8 6 4 2 ON-RESISTANCE vs. V D (BIPOLAR SUPPLY VOLTAGE AND TEMPERATURE) = 5V, = T A = +25 C T A = -55 C -3-6 5 5 2-2 - 2-5 - -5 5 5 4
Typical Operating Characteristics (continued) (, unless otherwise noted.) RDS(ON) (Ω) 5 25 75 5 ON-RESISTANCE vs. V D (UNIPOLAR SUPPLY VOLTAGE AND TEMPERATURE) T A = +25 C T A = -4 C 25 = 2V = 4 8 2-7 TIME (ns) 6 2 8 4 ING TIME vs. BIPOLAR SUPPLY VOLTAGE t ON t OFF ±5 ± ±5 ±2 BIPOLAR SUPPLY VOLTAGE (V) -8 TIME (ns) 2 5 5 ING TIME vs. UNIPOLAR SUPPLY VOLTAGE t ON t OFF = 5 2 25 UNIPOLAR SUPPLY VOLTAGE (V) -9 2 = 5V = C L = nf CHARGE INJECTION vs. V D VOLTAGE - 5 = 2V = V C L = nf CHARGE INJECTION vs. V D VOLTAGE - Q (pc) Q (pc) - -5-2 -5-5 - 5 5 5
DIP/SO/TSSOP PIN THIN QFN NAME, 8, 9, 6 6, 7, 4, 5 IN IN4 Logic Control Input 2, 7,, 5 5, 8, 3, 6 D D4 Analog-Switch Drain Output 3, 6,, 4, 4, 9, 2 S S4 Analog-Switch Source Output 4 2 Negative-Supply Voltage Input 5 3 Ground 2 VL Logic-Supply Voltage Input FUNCTION 3 Positive-Supply Voltage Input Connected to Substrate EP PAD Exposed Pad. Connect PAD to. Pin Description Applications Information General Operation ) Switches are open when power is off. 2),, and should not exceed or, even with the power off. 3) Switch leakage is from each analog switch terminal to or, not to other switch terminals. Operation with Supply Voltages Other than ±5V Using supply voltages less than ±5V will reduce the analog signal range. The operates with ±4.5V to ±2V bipolar supplies or with a +4.5V to +4V single supply; connect to when operating with a single supply. Also, all device types can operate with unbalanced supplies such as +24V and -5V. VL must be connected to to be TTL compatible, or to for CMOS-logic level inputs. The Typical Operating Characteristics graphs show typical on-resistance with ±2V, ±5V, ±V, and ±5V supplies. (Switching times increase by a factor of two or more for operation at ±5V.) Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the devices. Always sequence on first, followed by VL,, and logic inputs. If power-supply sequencing is not possible, add two small, external signal diodes in series with supply pins for overvoltage protection (Figure ). Adding diodes reduces the analog signal range to V below and V above, but low switch resistance and low leakage characteristics are unaffected. Device operation is unchanged, and the difference between and should not exceed +44V. V g S Figure. Overvoltage Protection Using External Blocking Diodes D 6
LOGIC OUTPUT +3V V V 5% V OUT.8 x V OUT t ON t OFF tf < 2ns tr < 2ns.8 x V OUT LOGIC OUTPUT OUTPUT Timing Diagrams/Test Circuits +3V V V D V V D V V O2 V O 5% t D.9V O t D.9V O LOGIC WAVEFORM IS INVERTED FOR ES THAT HAVE THE OPPOSITE LOGIC SENSE. +5V LOGIC +3V +5V C L INCLUDES FIXTURE AND STRAY CAPACITANCE. R L C L V OUT R REPEAT TEST FOR CHANNELS 2, 3, AND 4. L V OUT = V D ( ) Figure 2. Switching Time R L + R DS(ON) V D = V V O V D = V V O2 RL R L2 C L2 LOGIC V R L = Ω C L = 35pF C L INCLUDES FIXTURE AND STRAY CAPACITANCE. LOGIC. Figure 3. Break-Before-Make Test Circuit C L Revision History Pages changed at Rev 3:, 9, 7
Timing Diagrams/Test Circuits (continued) V OUT V IN Q = ΔV OUT C L ΔV OUT SIGNAL GENERATOR NETWORK ANALYZER dbm R GEN = 5Ω or +2.4V R L nf +5V nf 5Ω or +2.4V +5V R GEN V OUT Figure 6. Crosstalk V GEN C L nf +5V V IN = +3V Figure 4. Charge Injection CAPACITANCE METER or +2.4V f = MHz nf nf +5V SIGNAL GENERATOR dbm Figure 7. Source/Drain-Off Capacitance R GEN = 5Ω or +2.4V nf +5V NETWORK ANALYZER R L nf CAPACITANCE METER f = MHz or +2.4V Figure 5. Off-Isolation Rejection Ratio V S nf Figure 8. Source/Drain-On Capacitance 8
TOP VIEW Pin Configurations (continued) IN D S 2 3 4 5 6 5 4 3 2 IN2 D2 S2 S4 6 S3 D4 7 D3 IN4 8 9 IN3 DIP/SO/QSOP/TSSOP LOGIC SW, SW 4 SW 2, SW 3 OFF ON ON OFF ES SHOWN FOR LOGIC "" Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) TSSOP4.4mm.EPS PACKAGE OUTLINE, TSSOP 4.4mm BODY 2-66 I 9
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 27 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.