Flexible CMOS Frequency Translation Circuits

Flexible CMOS Frequency Translation Circuits Eric Klumperink Zhiyu Ru, Michiel Soer, Bram Nauta 1

Outline Intro Analog Front Ends for SDR Interferer robust SDR Receiver analog part Interferer robust SDR Receiver digital part Mixing or Sampling? Mixer-first Receiver N-path Circuit Generalization Conclusion 2

Analog Front-End Interference strong: filtering Signal weak: amplification Frequency high: downconversion ADC speed and resolution are relaxed Channel-filter has better selectivity in baseband 3

Analog Front End Challenges Wanted for Software Defined Radio: Compatible with digital Flexible RF-frequency: wideband receiver with good NF Flexible channel-selection filtering: tunable LPF Be robust to in-band interference (often not so strong) Be robust to out-of-band interference: can be huge Wideband receiver wideband interference 4

Solutions: what has been proposed? International Solid-State Circuits Conference (ISSCC) 5

UCLA SDR Receiver [Bagheri, ISSCC06, UCLA] Wideband receiver: demonstrated at 800MHz & 2.4GHz Wideband CG-CS Balun-LNA (noise cancelling) Passive mixer Tunable baseband discrete-time filter Claim: no RF-filter needed, but room for doubts. 6

UCLA SDR Receiver: BB filter Tunable baseband filter with sufficient attenuation to support different standards, e.g. GSM WiFi (801.11g) 7

IMEC SDR Receiver 1 [Giannini, ISSCC09, IMEC] On-chip balun makes antenna interface simpler Two LNAs: to address both 1/f noise and high frequency Passive mixer for good linearity and 1/f noise Continuous-time tunable BB filter Rely on external filter for Out-of-Band Interference 8

Skyworks Multiband Transceiver [Pullela, ISSCC09, Skyworks] only receiver part shown here Multiband transceiver for GSM: 850/900/1800/1900MHz Share I/Q mixer & baseband Does not continuously cover bandwidth Not integrated: SAW filters, PAs and duplexers 9

IMEC SDR Receiver 2 [Ingels, ISSCC10, IMEC] In practice, multi-band antenna is a challenge, so LNA bank is a reasonable solution for short-term Similar to commercial multi-band receivers, but continuously covers a wide RF band Still each standard needs an external SAW filter 10

A Software-Defined Radio Receiver Architecture Robust to Out-of-Band Interference [Ru, ISSCC 2009, JSSC2009] 12

Wideband Interference: Nonlinearity Wideband LNA: also amplifies interference nonlinearity 13

Wideband Interference: Harmonic Mixing Switching mixer: square-wave LO harmonic mixing 14

Low Noise Transconductance at RF V-I instead of voltage gain at RF I-V together/after low-pass filter (LPF) to reduce blockers Keep low impedance over a wide band at node B 15

Realization: Wideband LNTA + Mixer + TIA LNTA: high G m & high R out low noise small voltage swing at node B good linearity Similar to [1], but now wideband and with blocker filtering [1] Redman-White & Leenaerts, ESSCIRC07 16

Harmonic Rejection (HR) Mixer: Remove 3LO and 5LO rd th cancel! Amplitude weighting + phase shifting emulate sine-lo [2] Weldon et. al., ISSCC01 17

Problem: Amplitude and Phase Errors 3 rd or 5 th harmonic vector diagram Amplitude and phase errors unwanted harmonic residue degrade HR ratio How to make irrational ratio, e.g. 2, on chip? 18

2-Stage Polyphase HR: Concept 41/29=1.4138, 2=1.4142 ε=0.03% 19

2-Stage Polyphase HR: Realization 50Ω 2G m +- - + +- - + 0 180 45 225 7 5 7 7 5 7 +- - + 50Ω 3G m +- - + 90 270 7 5 7 +- - + 2G m +- 135 7 5 - + 315 7 RF LNTA for 1 st -stage weighting (2:3:2) BB resistor for 2 nd -stage weighting (5:7:5) Nominally 2, what about influence of mismatch? 20

Reduced Effect of Amplitude Mismatch 2-stage polyphase product of relative errors E.g. 2:3:2 α=6% 1 st -stage only: HR3=40dB 5:7:5 β=1% 2-stage total: HR3=86dB NOTE: Also an accurate clock is needed (later) 21

RF Filtering is Relaxed! Low-pass filtering: attenuates interference around LO 2-stage polyphase HR: robustly attenuates 3LO and 5LO f 22

Zero-IF Receiver Prototype 23

Chip Photo 1mm 2 in 65nm CMOS VDD: 1.2V Current consumption: Analog 33mA Digital 17mA 24

Measured HR: 40 Chips HR Ratio @ 0.8G LO HR Ratio (db) 90 80 70 5th 3rd 60 1 10 20 30 40 Sample # No trimming & calibration, no RF filtering 25

Measured Performance Summary +3dBm / +46dBm / LO Frequency 0.4~0.9GHz Gain 34.4±0.2dB DSB NF 4dB±0.5dB S 11 < -10dB 80M~5.5GHz In/Out-of-band IIP3 1 +18dBm In/Out-of-band IIP2 2 +51dBm IF Bandwidth 12MHz 1/f noise 30kHz corner VDD 1.2V Current Consumption Analog: 33mA Digital (clock): 8mA @ 0.4GHz 17mA @ 0.9GHz Harmonic Rejection Ratio @ 0.8GHz LO 3 rd -order > 60dB (40 chips) 5 th -order > 64dB (40 chips) 2 nd, 4 th, 6 th > 62dB (20 chips) 1 Out-of-band IIP3: two tones = 1.61G & 2.40GHz, LO = 819MHz 2 Out-of-band IIP2: two tones = 1.80G & 2.40GHz, LO = 601MHz 26

Conclusion: A SDR Receiver Architecture Robust to Out-of-Band Interference Only voltage gain @ BB after low-pass filtering Blocking point enhanced by 10dB w.r.t. P 1dB In-band IIP3 +3dBm & out-of-band IIP3 +18dBm 2-stage polyphase harmonic rejection technique Robust: error = product of errors Accurate multiphase clock (discussed later) Minimum HR 60dB (40 chips) - NO calibration/rf filters 27

Digital Assisted approach Harmonic Rejection Exploiting Adaptive Interference Cancellation [Moseley, ISSCC 2009] 29

Only first stage of 2-stage HR receiver To Digital Harmonic Rejection Algorithm (Baseband processor) 30

The Basic Idea Subtract interference (residual harmonic image responses) from received signal. Need interference estimate signal. 31

Adaptive Interference Cancelling (AIC) Adaptive filter aligns phase & amplitude. Minimizes cross-correlation v(n) and e(n). 32

Two I/Q signals, 45 degrees rotated Chip +- - + ADC 2Gm 50Ω +- - + ADC RF + - 3Gm 50Ω +- - + ADC 2Gm CLK + - 100Ω 8 8 +- - + ADC 33

Interference estimate generation Contains unwanted harmonic responses, but desired signal 34

AIC Algorithm 1/5 35

AIC Algorithm 2/5 36

AIC Algorithm 3/5 37

AIC Algorithm 4/5 38

AIC Algorithm 5/5 39

Demonstration 40

Demonstration 41

Demonstration 42

Demonstration 43

Demonstration: FM signal at 3 rd harmonic 44

Comparison This work Z. Ru ISSCC 2009 12.8 Reject strongest >80 db (1) >60 db Reject the other >36 db >60 db (3 rd or 5 th ) Reject even >64 db >62 db Power frontend 45 ma @ 1.2 V (excl. ADCs) 50 ma @ 1.2 V (excl. ADCs) Power DSP <8.5 ma @ 1.2 V N/A (100 Msps) (simulated) # ADCs 4 / 2 if AIC off 2 (1) If one harmonic interference image band is dominating. 45

Adaptive Interference Cancellation: Conclusions Dual-domain Harmonic Rejection Mixer (HRM): Analog HRM + 4 ADCs + Digital AIC. Strongest correlating harmonic image is removed X-correlation -> independent of signal shape Stronger interferer -> more rejection Measurements: First stage (analog) HR > 36 db. Dual domain HR3 or HR5 > 80 db. 46

Mixing or Sampling? Is it a mixer or a sampler? 48

Frequency Conversion Classification Input Analog-CT Analog-DT Digital Principle Mixing CT Mixing DT Mixing Digital Mixing Sampling CT-to-DT Sampling DT Resampling Digital Resampling CT = Continuous-Time DT = Discrete-Time 49 49

Is this Mixing or Sampling? Can be both 50

Mixing or Sampling: Use of output? Rate? Use in a CT system Use in a DT system The distinction is NOT in the circuit itself Key question: how is the output signal used?? Does observation rate change or not? CT Mixing: RF(t) IF(t) No CT-to-DT Sampling: RF(t) IF(k) Yes! 51

Mixing or Sampling: Classification Input Principle Mixing (observation rate does not change) Sampling (observation rate does change) Analog-CT Analog-DT Digital CT Mixing DT Mixing Digital Mixing CT-to-DT Sampling DT Resampling Digital Resampling Notes: Mixing Output remains Analog-CT, Analog-DT or Digital (=input rate ) Analog is considered as infinite rate Sampling Output rate differs from input, e.g. CT to DT, decimate Sampling may but need not give down-conversion (aliasing) choose via pre-filtering 52

Receiver Architectures for SDR (a) CT-Mixing Receiver (b) RF-Sampling Receiver (c) Ideal-Software-Radio Receiver Trend of moving mixer-lpf into digital 53

Fit to Three Receiver Architectures Input Analog-CT Analog-DT Digital Principle Mixing (observation rate does not change) Sampling (observation rate does change) CT Mixing 1 DT Mixing Digital Mixing 3 CT-to-DT DT Re- Digital Re- Sampling 2 sampling 2 sampling 3 1 CT-mixing receiver 2 RF-sampling receiver 3 Ideal SWR receiver 54

Mixer-first receiver: A 0.2-to-2.0GHz 65nm CMOS Receiver Without LNA Achieving >11dBm IIP3 and <6.5dB NF [Soer, ISSCC2009] 56

Motivation: High Dynamic Range Goal: receiver for Software Defined Radio Spurious Free Dynamic Range (SFDR): Difference between strongest interferer and weakest detectable signal Determines filter requirements Limited both by noise and nonlinearity Assume noise figure NF and bandwidth B Linearity is usually limited by IIP3 Assuming noise and IM3 are equal: 2 SFDR 3 (IIP3 NF 10logB 174dBm) High SFDR low NF, high IIP3 57

LNA-first vs. Mixer-first LNA-first: Low noise LNA Feedback difficult @ RF Moderate LNA linearity active Active-mixer-first: Feedback amplifier @ IF Moderate mixer linearity Noise folding 58

Proposed Architecture passive Use passive mixer: High linearity No voltage gain before mixer: Noise folding? Conversion loss? Solve with: Harmonic cancellation Optimized mixer duty cycle 59

Mixer Operation RF LO IF -f S 0 f S -f S f S Linear Periodically Time Variant: LO frequency f S 0 -f S 0 f S Convolution with harmonics (not all shown) Noise folding increases NF 60

Mixing vs. Sampling Downconversion Pull to zero 1 + - R 1 R 2 R1 R 2 ½ -4f S -3f S -2f S -f S 0 f S 2f S 3f S 4f S Mixer conversion gain: -9.9dB T ON Hold! 1 + - T on R C R C ½ -4f S -3f S -2f S -f S 0 f S 2f S 3f S 4f S Sampler conversion gain: -3.9dB 61

Multiphase + - Balanced: 180 clock phase difference No RF- and DC feed-through Cancel even-order harmonics I Q In-phase / Quadrature: 90 clock phase difference Image rejection? Clocks overlap! 62

25% Quadrature Sampling Mixer (T on <<RC) A B C D A C B D T on I+ I- Q+ Q- R C -0.9dB 0-5f s -4f s -3f s -2f s -f s f s 2f s 3f s 4f s 5f s Balanced I/Q image rejection -0.9dB conversion gain 0.9dB NF 63

LPTV circuit Input Impedance Actual use: V S as input R S part of mixer Most power reflected Also moved to other different harmonics, reflected and dissipated in R S V S R S + - source Z IN High input impedance : Weired : f(r s )!! High, but not infinite Input current modulated by switching Duty cycle dependent 25% duty cycle : Z 4.2 IN R S [Cook, ISSCC 2006] 64

RF Filter RF Filter needed: Reject 3 rd harmonic and out-of-band interferers Not included in ICdesign 50Ω Design for high Z IN : No standard filter Z 4.2 IN R S 50 Ω Low pass example 210 Ω 65

Single-Ended to Differential Total Design Differential Four-phase Clocks Differential 5Ω Switches Feedback Amplifier 66

Chip Micrograph 65nm CMOS, active area 0.13mm 2 67

25 20 Gain, IIP3 and DSB NF vs. RF Gain 25 20 [db] 15 10 NF IIP3 15 10 [dbm] 5 5 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Lines: simulation Markers: measurement RF frequency [MHz] 68

Gain, IIP3 and DSB NF vs. IF 25 Gain 25 20 20 15 IIP3 15 [db] 10 10 [dbm] NF 5 5 0 Lines: simulation Markers: measurement 1 3 5 7 9 11 13 15 17 19 IF frequency [MHz] Note: out-of-band IIP3 is even higher ~+25dBm 0 69

This Work Benchmarking [Bagheri, ISSCC 2006] [van de Beek, ISSCC 2008] Tektronix RSA2200A RF Frequency 0.2-2.0 0.8-6 0.6-10 0-3 GHz IF -3dB Bandwidth 25 20 264 ~10 MHz Gain 19 20 14 db DSB NF 6.5 5 7 24 db IIP2 +65 +60 +20 dbm IIP3 +11-4 0 +30 dbm SFDR in 1MHz BW 79 70 71 80 db Power Dissipation 67 60 90 mw Supply Voltage 1.2 2.5 1.2 V Active Area < 0.13 3.8 < 0.2 mm 2 Technology 65nm 90nm 45nm CMOS 70

Mixer-first receiver: Conclusions Linear mixer-first downconverter Mixing before amplification @ IF Sampling passive mixer low conversion loss 25% duty cycle image rejection and balancing High SFDR demonstrated Multi-phase harmonic cancelling low NF Passive mixer + feedback amplifier high IIP3 71

Mixer-First Receiver States Single Ended series switch-rc Kernel in each clock-phase 73

Polyphase Kernels Shared properties of the circuits: Each Kernel = Switched series-r-c: Activated by Polyphase clocks: S1 S2 S3 Non-overlapping on-time Circuit state Capacitor voltage hold-phase! Output LTV combination of C-voltages 74

Outcome: Harmonic Transfer Functions Periodic time variant behaviour gives shape: H -2 (s) H -1 (s) H 0 (s) H 1 (s) H 2 (s) V i (f i ) V o (f o ) 1 e^ j2π n f s t Input signal components get: Filtered Shifted in frequency Added One input component gives multiple output contributions [Ström,CAS1977],[Soer, TCASI, 2010] 75

Result: Equivalent Model of Kernel-Behaviour [Soer, TCASI, 2010] f s After quite some math: G SE (f i ) Models behavior for any value of R, C, D(uty cycle), f i, f s, f o f i /f s 76

Crucial parameter: Small or Big =t on /RC Both show a hold, but only big tracks and samples input well For small : simplification for 0 and :, 1 Harmonic Mixing including a first-order low-pass filter defined by RC and D Big : Small : 77

Mixing and Sampling Region SE kernel noise in [10-17 V 2 /Hz] for f s =100MHz, f o =0Hz, D=1/4 100 C [pf] 10 1 4 2 Sampling Mixing Noise reduction: Sampler: high C Mixer: lower R SE Kernel Noise PSD Mixing Approx. Sampling Approx. 10 100 1000 R [ ] 78

Combining Kernels Reasons: LO-harmonic cancellation E.g. even LO-harmonics: IN OUT Image rejection: (I and Q signal) Better conversion gain, noise? 79

To Be or Not To Be? n = harmonic index f-shift n f s w = wanted harmonic (e.g. -1 for mixing RX) l = path index, l=1..l (L= # paths) NOT cancelled if: n = i L + w where i =..,-2,1,0, 1,2, Often: w=-1 (downconversion), so first non-cancelled is (L-1)f s 80

If present: Conversion Loss in db for n=-1 70 60 mixing region =2 6 sampling region 50 4 D [%] 40 30 20 10 2 1 0.5 0.1 0.1 0.1 1 10 f rc /f s D=25% Mixer-first receiver (0.9 db loss) 81

Noise Analysis A: Linear Time Invariant (LTI) B: Noise folding due to the time variance 82

70 60 50 Noise Figure versus RC and Duty Cycle mixing Mixing region Region =2 sampling Sampling region Region Mixing better Minimum for D=37% If multi-kernel and all contributions add up in phase: D [%] 40 30 20 7 8 10 10 10 12 12 0.1 1 10 D=25% Mixer-first receiver f rc /f s (D=25%: 6.9 db NF for single kernel; 0.9dB after I/Q Combination (L=4)) Best achievable: 83

Conclusions Samplers and mixers classified in two ways: High-level: based on information rate Circuit level: series-switch-r-c operating region Generalized LPTV analysis of switch-r-c circuits Kernels driven by non-overlapping multi-phase clocks On-time compared to RC crucial: =t on /RC If <2: Mixing: R mainly defines noise If >2: Sampling: C mainly defines noise Analytical expressions for conversion gain, aliasing, impedance, noise figure for mixers and N-path filters 84

References [Tayloe,P2001] D. Tayloe, Product detector and method therefor, US Patent 6 230 000, 2001. [Cook,JSSC2006] B. W. Cook, A. Berny, A. Molnar, S. Lanzisera, and K. S. J. Pister, Low-Power 2.4- GHz Transceiver With Passive RX Front-End and 400-mV Supply," IEEE Journal of Solid-State Circuits, vol. 41, no. 12, Dec 2006. [Ström,CAS1977] T. Ström and S. Signell, Analysis of Periodically Switched Linear Circuits, IEEE Trans. on Circuits and Systems, vol. CAS-24, no. 10, Oct 1977. [Soer, ISSCC2009] M. C. M. Soer, E. A. M. Klumperink, Z. Ru, F. E. van Vliet, and B. Nauta, A 0.2-to- 2.0GHz 65nm CMOS Receiver Without LNA Achieving >11dBm IIP3 and <6.5dB NF," IEEE ISSCC Dig. Tech. Papers, vol. 52, pp. 222-223, 2009. [Soer,TCASI, 2010] M. C. M. Soer, E. A. M. Klumperink, P. T. de Boer, F. E. van Vliet, and B. Nauta, Unified Frequency Domain Analysis of Switched-Series-RC Passive Mixers and Samplers," IEEE Trans. Circuits and Systems-I, pp. 2618-2631, 2010. [Ru,JSSC2009] Ru, Z. and Moseley, N.A. and Klumperink, E.A.M. and Nauta, B. (2009) Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference.Special Issue of the IEEE Journal of Solid-State Circuits on ISSCC2009, 44 (12), pp.3359-3375, december 2009. [Moseley,ISSCC2009] Moseley, N.A., Ru, Z., Klumperink, E.A.M., Nauta, B., "A 400-to-900 MHz Receiver with Dual-domain Harmonic Rejection Exploiting Adaptive Interference Cancellation", 2009 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, February 8-12, Digest of Technical Papers, pp. 232-233, 2009. [Ru,ISSCC2009] Ru, Z., Klumperink, E.A.M., Wienk, G.J.M., Nauta, B., "A Software-Defined Radio Receiver Architecture Robust to Out-of-Band Interference", 2009 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, February 8-12, Digest of Technical Papers, pp. 232-233, 2009. 85