Novel Small-Dimension Poly-Si TFTs with Improved Driving Current and Suppressed Short Channel Effects Hsiao-Wen Zan and Chun-Yen Chang Institute of Electronics, National Chiao Tung University, TAIWAN 1
Outlines Introductions Device Fabrication Results and Discussions SEM images Typical characteristics High voltage operation Effects of NH 3 passivation Conclusions 2
Introductions As peripheral driving circuits in AMLCD, poly-si TFTs need: large driving current good output current saturation characteristics Advantages of thin-channel poly-si TFTs : enhanced driving current sharp subthreshold swing punch-through suppression floating body effect suppression Disadvantages of thin S/D region: large S/D series resistances degraded driving ability 3
Introductions Disadvantages of prior raised S/D structure : Complex structure ( ex. need CMP process or additional masks ) Process incompatible with conventional poly-si TFT process Proposed selective W-raised S/D poly-si TFTs ( W-TFTs ) : Effectively reduce S/D resistance and improve ON characteristics Process is simple and compatible with LTPS process 4
Device Fabrication The fabrication procedures Channel Deposition : 30-nm-thick a-si Gate oxide : 60-nm-thick LPTEOS oxide Gate Electrode : 300-nm-thick a-si SPC (Solid Phase Crystallization) LDD implantation Oxide spacer : 20-nm-thick TEOS oxide S/D implantation and RTA activation Passivation : NH 3 plasma for 1 hr Selective CVD W deposition : 120-nm-thick W 5
Device Fabrication W-TFTs and conventional oxide-spacer TFTs 6
Results and Discussions The SEM image Self-limited Si reduction reaction : about 10 ~15-nmthick Si consumption ensuring small R C Selective Silane reduction reaction : Selectively deposited on nucleating W film surfaces Reaction equations: Silicon reduction : 2WF 6 (vapor) + 3Si(solid) 2W(solid) + 3SiF 4 (vapor) Silane reduction : 2WF 6 (vapor) + 3SiH 4 (vapor) 2W(solid) + 3SiF 4 (vapor) + 6H 2 (vapor) 7
Results and Discussions I D -V D characteristics Conventional TFTs : I D is limited by large S/D series resistance with increasing V G W-TFTs: Larger on current Improved output saturation characteristics and increasing I D spacing with increasing V G => W-TFTs effectively reduce S/D series resistance while conventional TFTs are dominated by large series resistance. Drain Current I D ( ma ) 0.5 0.4 0.3 0.2 0.1 0.0 30-nm-thick channel W / L =10 µm / 3 µm V G = 4 V, 7 V, 10 V, 13 V LDD W-TFTs LDD Conventional TFTs 0 2 4 6 8 10 12 Drain Voltage V D ( V ) 8
Results and Discussions I D -V G characteristics Similar V TH, S.S. comparable OFF current W-TFTs have larger ON current V TH ( V ) at V D = 5 V S. S. (V/decade) at V D = 0.1 V On/Off ratio at V D = 5V W-TFTs 0.68 0.28 2.7 10 7 Conventional TFTs 0.62 9.8 10 6 On current is measured at V G = 20 V and V D = 5 V. Off current is the minimum drain current at V D = 5 V. 0.3 D ( A ) Drain Current I 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 30-nm-thick channel W / L=10 µm / 3 µm VD = 0.1 V, 5 V LDD W-TFTs LDD Conventional TFTs -10-5 0 5 10 15 20 Gate Voltage V G ( V ) 9
10 Results and Discussions Gm comparison For long channel devices, W-TFTs have superior saturation gm especially under large V G Drain Current I D ( A ) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 30-nm-thick channel W / L = 10 µm / 5 µm V D = 0.1 V, 5 V gm extracted as V D = 5 V 0.00-10 -5 0 5 10 15 20 Gate Voltage V G ( V ) LDD W-TFTs LDD Conventional TFTs gm of LDD W-TFTs gm of LDD Conventional TFTs 1.75 1.50 1.25 1.00 0.75 0.50 0.25 Transconductance gm ( ms / mm )
11 Results and Discussions Gm comparison As channel length scaled down to 0.8 µm : Conventional TFTs are limited by R S gm is low W-TFTs still have large gm even under large V G Drain Current I D ( A ) 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 30-nm-thick channel W / L = 10 µm / 0.8 µm V D = 0.1 V, 5 V gm extracted as V D = 5 V 0-10 -5 0 5 10 15 20 Gate Voltage V G ( V ) LDD W-TFTs LDD conventional TFTs gm for LDD W-TFTs gm for LDD Conventional TFTs 10 9 8 7 6 5 4 3 2 1 Transconductance gm ( ms / mm )
Results and Discussions V TH roll-off As channel length decreasing : 1.0 V TH roll-off due to the impact ionization V TH shift of W-TFTs is less pronounced than that of conventional ones. Threshold Voltage V TH ( V ) 0.5 0.0-0.5 30-nm-thick channel W = 10 µm V D = 5 V LDD W-TFTs LDD Conventional TFTs LDD W-TFTs may suppress the floating body effect due to easily repelling the accumulated holes in body region -1.0 0 1 2 3 4 5 6 7 8 9 10 Channel Length L ( µm ) 12
Results and Discussions Long-channel devices 0.5 W / L =10µm / 10µm V G =12 V, 16 V, 20 V Under large V D, conventional TFTs with 50- nm-thick channel have severe kink effects even the channel length is 10 µm. Drain Current ID ( ma ) 0.4 0.3 0.2 0.1 30-nm-thick channel LDD W-TFTs 50-nm-thick channel LDD conventional TFTs 50-nm-thick channel NO LDD conventional TFTs 0.0 0 5 10 15 20 Drain Voltage V D ( V ) 13
Results and Discussions High voltage operation Output resistance 2.5 R out ( I D / V D VG = constant ) -1 30-nm-thick channel LDD W-TFTs have the largest R out. Output Resistance R out ( MΩ ) 2.0 1.5 1.0 0.5 30-nm-thick channel LDD W-TFTs 50-nm-thick channel LDD Conventional TFTs 50-nm-thick channel NO LDD Conventional TFTs W / L =10 µm / 10 µm V G =16 V 0.0 0 2 4 6 8 10 12 14 16 18 20 22 Drain Voltage V D ( V ) 14
15 Results and Discussions High voltage operation The voltage gain A V is an import parameter in analog circuit devices => A V = R out gm = 2R out I D / (V G -V TH ) 30-nm-thick channel LDD W-TFTs are suitable to be used as high-voltage operated peripheral circuits in AMLCD. Voltage Gain A V 50 40 30 20 10 0 30-nm-thick channel LDD W-TFTs 50-nm-thick channel LDD Conventional TFTs 50-nm-thick channel NO LDD Conventional TFTs A V = 2 R out I D / ( V G - V TH ) W / L=10 µm / 10 µm V G = 16 V 0 2 4 6 8 10 12 14 16 18 20 22 Drain Voltage V D ( V )
16 Results and Discussions NH 3 passivation effect Passivation before W deposition is better than passivation after W deposition. Because W block NH 3 molecules from entering channel region. Passivated bonds are stable since W deposition is at 300ºC. Drain Current I D ( A ) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 30-nm-thick channel W / L = 10 µm / 3 µm V D = 0.1 V, 5 V -10-5 0 5 10 15 20 Gate Voltage V G ( V ) W-TFTs ( plasma before W ) W-TFTs ( plasma after W )
17 Conclusions W-raised S/D poly-si TFTs ( W-TFTs ) are successfully fabricated. The related process is Simple : one-step selectively deposited W R-S/D Compatible : conventional top-gated oxide spacer structure and LTPS process Self-limited Si consumption : less than 15-nm-thick poly-si consumption ensuring good R C Compared to conventional oxide-spacer counterparts, W-TFTs have : Higher ON current Better output characteristics and transconductance Comparable V TH, S.S., and OFF current
18 Conclusions W-TFTs have superior performances than conventional ones especially when channel length is scaled down operated under large V G W-TFTs with thin channel and LDD structure can effectively suppress the floating body effects. They also have excellent output saturation characteristics under high voltage operation. Plasma passivation needs to be performed before W deposition for fear that W film around S/D block molecular from entering channel region.