l Logic-Level Gate Drive l dvanced Process Technology l Surface Mount (IRLZ24NS) l Low-profile through-hole (IRLZ24NL) l 75 C Operating Temperature l Fast Switching l Fully valanche Rated Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D 2 Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D 2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRLZ24NL) is available for lowprofile applications. bsolute Maximum Ratings PD - 9358E IRLZ24NS/L HEXFET Power MOSFET 2 D Pak TO-262 V DSS = 55V R DS(on) = 0.06Ω I D = 8 Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 8 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 3 I DM Pulsed Drain Current 72 P D @T = 25 C Power Dissipation 3.8 W P D @T C = 25 C Power Dissipation 45 W Linear Derating Factor 0.30 W/ C V GS Gate-to-Source Voltage ±6 V E S Single Pulse valanche Energy 68 mj I R valanche Current E R Repetitive valanche Energy 4.5 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 3.3 C/W R θj Junction-to-mbient ( PCB Mounted,steady-state)** 40 G D S 5/2/98
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.06 V/ C Reference to 25 C, I D = m 0.060 V GS = 0V, I D = R DS(on) Static Drain-to-Source On-Resistance 0.075 Ω V GS = 5.0V, I D = 0.05 V GS = 4.0V, I D = 9.0 V GS(th) Gate Threshold Voltage.0 2.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 8.3 S V DS = 25V, I D = I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 00 V GS = 6V n Gate-to-Source Reverse Leakage -00 V GS = -6V Q g Total Gate Charge 5 I D = Q gs Gate-to-Source Charge 3.7 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 8.5 V GS = 5.0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 7. V DD = 28V t r Rise Time 74 I D = ns t d(off) Turn-Off Delay Time 20 R G = 2Ω, V GS = 5.0V t f Fall Time 29 R D = 2.4Ω, See Fig. 0 L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 480 V GS = 0V C oss Output Capacitance 30 pf V DS = 25V C rss Reverse Transfer Capacitance 6 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 8 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 72 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S =, V GS = 0V t rr Reverse Recovery Time 60 90 ns T J = 25 C, I F = Q rr Reverse Recovery Charge 30 200 nc di/dt = 00/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L = 790µH R G = 25Ω, I S =. (See Figure 2) ƒ I SD, di/dt 290/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. Uses IRLZ24N data and test conditions ** When mounted on " square PCB ( FR-4 or G-0 Material ). For recommended footprint and soldering techniques refer to application note #N-994.
I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V 0V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE W IDTH 0. T J = 25 C 0. 0 00 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current () 00 0 VGS TOP 5V 2V 0V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE W IDTH 0. T J = 75 C 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J V DS= 5V 20µs PULSE W IDTH 0. 2 3 4 5 6 7 8 9 0 V GS T = 75 C J, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 2.5 2.0.5.0 0.5 I D = 8 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature
C, Capacitance (pf) 800 600 400 200 C iss C oss C rss V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd V, Gate-to-Source Voltage (V) GS 5 2 9 6 3 I D = V DS = 44V V DS = 28V 0 0 00 V DS, Drain-to-Source Voltage (V) FOR TEST CIRCUIT 0 SEE FIGURE 3 0 4 8 2 6 20 Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J I D, Drain Current () 000 00 0 OPERTION IN THIS RE LIMITED BY R DS(on) 0µs 00µs V GS = 0V 0.4 0.8.2.6 2.0 V SD, Source-to-Drain Voltage (V) T C = 25 C ms T J = 75 C Single P u lse 0ms 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating rea
20 V DS R D I D, D rain Current (m ps) 6 2 8 4 0 25 50 75 00 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0a. Switching Time Test Circuit V DS 90% R G V GS 5.0V Pulse Width µs Duty Factor 0. % D.U.T. 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms - V DD 0 Therm al Response (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) 2. Peak T J = P DMx Z thjc T C 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Notes:. Duty factor D = t / t 2 P DM t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case
L V DS D.U.T. R G V - DD 5.0 V I S t p 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD E S, Single Pulse valanche Energy (mj) 40 20 00 80 60 40 20 I D TOP 4.5 7.8 BOTTOM V DD = 25V 0 25 50 75 00 25 50 75 Starting T J, Junction Temperature ( C) V DS I S Fig 2b. Unclamped Inductive Waveforms Fig 2c. Maximum valanche Energy Vs. Drain Current Current Regulator Same Type as D.U.T. 50KΩ 0 V Q GS Q G Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit
Peak Diode Recovery dv/dt Test Circuit IRLZ24NS/L D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS
D 2 Pak Package Outline.40 (.055) M X. 0.54 (.45) 0.29 (.405) - - 2 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 0.6 (.400) REF. 6.47 (.255) 6.8 (.243).78 (.070).27 (.050) 3 5.49 (.60) 4.73 (.580) 2.79 (.0) 2.29 (.090) 5.28 (.208) 4.78 (.88) 2.6 (.03) 2.32 (.09) 3X.40 (.055).4 (.045) 5.08 (.200) 3X 0.93 (.037) 0.69 (.027) 0.55 (.022) 0.46 (.08).39 (.055).4 (.045) 8.89 (.350) REF. 0.25 (.00) M B M MINIMUM RECOMMENDED FOOTPRINT.43 (.450) NOTES: DIMENSIONS FTER SOLDER DIP. 2 DIMENSIONING & TOLERNCING PER NSI Y4.5M, 982. 3 CONTROLLING DIMENSION : INCH. 4 HETSINK & LED DIMENSIONS DO NOT INCLUDE BURRS. LED SSIGNMENTS - GTE 2 - DRIN 3 - SOURCE 8.89 (.350) 3.8 (.50) 7.78 (.700) 2.08 (.082) 2X 2.54 (.00) 2X Part Marking Information D 2 Pak INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE F530S 9246 9B M PRT NUMBER DTE CODE (YYW W ) YY = YER WW = WEEK
Package Outline TO-262 Outline Part Marking Information TO-262
Tape & Reel Information D 2 Pak TRR.60 (.063).50 (.059) 4.0 (.6) 3.90 (.53).60 (.063).50 (.059) 0.368 (.045) 0.342 (.035) FEED DIRECTION.85 (.073).65 (.065).60 (.457).40 (.449) 5.42 (.609) 5.22 (.60) 24.30 (.957) 23.90 (.94) TRL 0.90 (.429) 0.70 (.42) 6.0 (.634) 5.90 (.626).75 (.069).25 (.049) 4.72 (.36) 4.52 (.78) FEED DIRECTION 3.50 (.532) 2.80 (.504) 27.40 (.079) 23.90 (.94) 4 330.00 (4.73) MX. 60.00 (2.362) MIN. NOTES :. COMFORMS TO EI-48. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MESURED @ HUB. 4. INCLUDES FLNGE DISTORTION @ OUTER EDGE. 26.40 (.039) 24.40 (.96) 3 30.40 (.97) MX. 4 WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (30) 322 333 EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: 44 883 732020 IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 2Z8, Tel: (905) 475 897 IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: 49 672 96590 IR ITLY: Via Liguria 49, 007 Borgaro, Torino Tel: 39 45 0 IR FR EST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 7 Tel: 8 3 3983 0086 IR SOUTHEST SI: 35 Outram Road, #0-02 Tan Boon Liat Building, Singapore 036 Tel: 65 22 837 http://www.irf.com/ Data and specifications subject to change without notice. 5/98