A Comparative Analysis between Homodyne and Heterodyne Receiver Architecture Md Sarwar Hossain * & Muhammad Sajjad Hussain **

Similar documents
Receiver Architecture

Session 3. CMOS RF IC Design Principles

Radio Receiver Architectures and Analysis

RFIC Design ELEN 351 Lecture 2: RFIC Architectures

Receiver Architectures

CMOS Dual Band Receiver GSM 900-Mhz / DSS-GSM1800-GHz

TSEK38: Radio Frequency Transceiver Design Lecture 3: Superheterodyne TRX design

ELEN 701 RF & Microwave Systems Engineering. Lecture 2 September 27, 2006 Dr. Michael Thorburn Santa Clara University

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 678A 40MHZ TO 900MHZ DIRECT CONVERSION QUADRATURE DEMODULATOR

THE RECENT SURGE in applications of radio-frequency

RADIO RECEIVERS ECE 3103 WIRELESS COMMUNICATION SYSTEMS

A 900MHz / 1.8GHz CMOS Receiver for Dual Band Applications*

STUDY OF THREE PHASE DEMODULATOR BASED DIRECT CONVERSION RECEIVER

1 Introduction RF receivers Transmission observation receiver Thesis Objectives Outline... 3

Introduction to Receivers

Radio Research Directions. Behzad Razavi Communication Circuits Laboratory Electrical Engineering Department University of California, Los Angeles

INTRODUCTION TO TRANSCEIVER DESIGN ECE3103 ADVANCED TELECOMMUNICATION SYSTEMS

RF Integrated Circuits

Radioelectronics RF CMOS Transceiver Design

CMOS RFIC Design for Direct Conversion Receivers. Zhaofeng ZHANG Supervisor: Dr. Jack Lau

Introduction to CMOS RF Integrated Circuits Design

RF/IF Terminology and Specs

EECS 242: Receiver Architectures

Chapter 6. Case Study: 2.4-GHz Direct Conversion Receiver. 6.1 Receiver Front-End Design

Receiver Design. Prof. Tzong-Lin Wu EMC Laboratory Department of Electrical Engineering National Taiwan University 2011/2/21

Termination Insensitive Mixers By Howard Hausman President/CEO, MITEQ, Inc. 100 Davids Drive Hauppauge, NY

6.976 High Speed Communication Circuits and Systems Lecture 20 Performance Measures of Wireless Communication

TSEK38 Radio Frequency Transceiver Design: Project work B

Microwave Journal Page 1 of 12

Analog and RF circuit techniques in nanometer CMOS

Wideband Receiver for Communications Receiver or Spectrum Analysis Usage: A Comparison of Superheterodyne to Quadrature Down Conversion

A 60-dB Image Rejection Filter Using Δ-Σ Modulation and Frequency Shifting

4- Single Side Band (SSB)

DESIGN OF 2.4 GHZ LOW POWER CMOS TRANSMITTER FRONT END

Design of Single to Differential Amplifier using 180 nm CMOS Process

ADI 2006 RF Seminar. Chapter II RF/IF Components and Specifications for Receivers

High Speed Communication Circuits and Systems Lecture 10 Mixers

Feedback Linearization of RF Power Amplifier for TETRA Standard

Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED

Fully integrated UHF RFID mobile reader with power amplifiers using System-in-Package (SiP)

THE rapid growth of portable wireless communication

TSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation. Ted Johansson, EKS, ISY

A Modular Approach to Teaching Wireless Communications and Systems for ECET Students

A Wideband Precision Quadrature Phase Shifter

Flexible CMOS Frequency Translation Circuits

TSEK02: Radio Electronics Lecture 8: RX Nonlinearity Issues, Demodulation. Ted Johansson, EKS, ISY

DECIMATION FILTER FOR MULTISTANDARD WIRELESS RECEIVER SHEETAL S.SHENDE

A high-level VHDL-AMS model design methodology for analog RF LNA and Mixer

An All CMOS, 2.4 GHz, Fully Adaptive, Scalable, Frequency Hopped Transceiver

ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5

Transceiver Architectures (III)

Designing a 960 MHz CMOS LNA and Mixer using ADS. EE 5390 RFIC Design Michelle Montoya Alfredo Perez. April 15, 2004

Technical Article A DIRECT QUADRATURE MODULATOR IC FOR 0.9 TO 2.5 GHZ WIRELESS SYSTEMS

PROJECT ON MIXED SIGNAL VLSI

A low-if 2.4 GHz Integrated RF Receiver for Bluetooth Applications Lai Jiang a, Shaohua Liu b, Hang Yu c and Yan Li d

Down-Converter Gilbert-Cell Mixer for WiMax Applications using 0.15µm GaAs HEMT Technology

RF IC Design Challenges

RF, Microwave & Wireless. All rights reserved

Optimizing the Performance of Very Wideband Direct Conversion Receivers

A-1.8V Operation Switchable Direct-Conversion Receiver with sub-harmonic mixer

Co-existence. DECT/CAT-iq vs. other wireless technologies from a HW perspective

ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2

DSP Based Radio Receiver Architectures 2

Nonlinearities in Power Amplifier and its Remedies

ELT Receiver Architectures and Signal Processing Exam Requirements and Model Questions 2018

TSEK03: Radio Frequency Integrated Circuits (RFIC) Lecture 5-6: Mixers

A 60GHz Transceiver RF Front-End

Mixer. General Considerations V RF VLO. Noise. nonlinear, R ON

International Journal of Advance Engineering and Research Development. Comparitive Analysis of Two stage Operational Amplifier

Low-Voltage IF Transceiver with Limiter/RSSI and Quadrature Modulator

THE rapid growth of portable wireless communication

COMPACT HIGH PERFORMANCE ANALOG CMOS BASEBAND DESIGN SOLUTIONS FOR MULTISTANDARD WIRELESS TRANSCEIVERS

RF Receiver Hardware Design

CMOS Design of Wideband Inductor-Less LNA

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science

Interference Issues between UMTS & WLAN in a Multi-Standard RF Receiver

An experimental vital signs detection radar using low-if heterodyne architecture and single-sideband transmission

1 Introduction to Highly Integrated and Tunable RF Receiver Front Ends

Reconfigurable Low-Power Continuous-Time Sigma-Delta Converter for Multi- Standard Applications

A 1.9GHz Single-Chip CMOS PHS Cellphone

Tuesday, March 22nd, 9:15 11:00

PTX-0350 RF UPCONVERTER, MHz

Lecture 15: Introduction to Mixers

THE BASICS OF RADIO SYSTEM DESIGN

Wideband Receiver Design

NOISE FACTOR [or noise figure (NF) in decibels] is an

NOISE PERFORMANCE CHARACTERSITICS OF DIRECT CONVERSION RECEIVERS

Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED

Ka Band Radar Transceiver

RF transmitter with Cartesian feedback

On the Architecture and Performance of a Hybrid Image Rejection Receiver

Today s communication

Wideband Active-RC Channel Selection Filter for 5-GHz Wireless LAN

ANALYSIS AND DESIGN OF A LOW POWER ADC

TSEK38: Radio Frequency Transceiver Design Lecture 7: Receiver Synthesis (II)

ALTHOUGH zero-if and low-if architectures have been

Speed your Radio Frequency (RF) Development with a Building-Block Approach

Low Distortion Mixer AD831

A 3rd- and 5th-order intermodulation products generator for predistortion of base-station HPAs

A 1MHz-64MHz Active RC TI-LPF with Variable Gain for SDR Receiver in 65-nm CMOS

Transcription:

A Comparative Analysis between Homodyne and Heterodyne Receiver Architecture Manarat International University Studies, 2 (1): 152-157, December 2011 ISSN 1815-6754 @ Manarat International University, 2011 A Comparative Analysis between Homodyne and Heterodyne Receiver Architecture Md Sarwar Hossain * & Muhammad Sajjad Hussain ** ABSTRACT Two available choices for receiver architecture in wireless communications are Homodyne and Heterodyne receivers. Among them, heterodyne receiver was the leading choice in the past compared to homodyne receiver regarding facing challenges in suppressing interference and noise. However, Direct Conversion is becoming popular for wireless communications due to its lower cost. The goal of this paper is to discuss the key problems and tradeoffs in the design of Heterodyne and Homodyne receiver. Keywords: Homodyne, Heterodyne, Receiver, Architecture, Wireless, Communications. I. INTRODUCTION One of the most difficult design element in any communication system is the receiver. A receiver should have low noise figure, low intermodulation distortion, high dynamic range, satisfactory gain flatness across the band, low phase noise, sufficient selectivity and suitable BER [1]. Also every design has certain cost constrains. This can be considered the most critical specification for any architecture. The preferred receiver design should be lower in cost for successful implementation. II. Heterodyne Receiver Figure 1. Heterodyne Receiver * Assistant Professor, Department of EEE, United International University, Dhaka. ** Assistant Professor, Department of Computer Science and Engineering, Manarat International University, Gulshan, Dhaka. 152

Manarat International University Studies, 2 (1): 152-157, December 2011 In a heterodyne architecture the signal frequency is translated to a lower but nonzero intermediate frequency (IF) where signal processing operations are performed. There are two frequency conversions in Heterodyne receiver. One from RF to IF and the another one from IF to base band. Again the IF section may be multiple blocks with several intermediate frequencies. Most receivers in wireless mobile use one IF block. Sufficient selectivity is achieved by fixed IF filters which are designed based on special technologies such as Surface Acoustic Wave (SAW), ceramic or crystal. A. Image Frequency Figure 2. Image Frequency through mixer In a h eterodyne architecture, the bands symmetrically located above and below the LO frequency are down converted to the same center frequency. If the receiver band of interest is 1 = LO - IF, then the image is around 2 LO - 1 = LO + IF [2]. Most common approach to suppress the image is putting an image reject filter in the receiver. Both image reject filter and IF filter require highly selective transfer function[3] for conventional heterodyne architecture. Since the image reject filter is placed off-chip the LNA needs to drive 50Ω load for this architecture. B. Half IF Frequency In addition to the desired band of interest in, an interferer ( in + LO )/2 is also received by the Heterodyne receiver. If there is a second order distortion in the received signal and LO contains second order distortion as well, one of the component of IF signal will be ( in + LO )-2 LO = IF. This is the interference at the output of mixer caused by the half IF frequency[2]. 153

A Comparative Analysis between Homodyne and Heterodyne Receiver Architecture C. Third Order Distortion Figure 3. Third order product (2F1-F2) and (2F2-F1) from input frequencies F1 and F2 When two signals with different frequencies are applied to a nonlinear system, the output will show some non harmonic frequency components. This is called intermodulation (IM) In Heterodyne receiver linearity is measured based on third order distortion level of the receiver. If the difference between two interferer, 1 and 2, is small, the product (2 1-2 ) or (2 2-1 ) will appear very close to 1 and 2. Due to this fact it is very hard to reject this interference even with a filter[4]. Moreover, for every db increment of input power 3 rd order product will increase by 3 db. At low frequencies, it is common to quantify the nonlinearity of a circuit by indicating the distortion in the output signal [5]. III. Homodyne Receiver Figure 4. Homodyne Receiver It is also called direct conversion or zero IF architecture, since the received signal is directly down converted to baseband. In a homodyne receiver, the desired signal 154

Manarat International University Studies, 2 (1): 152-157, December 2011 is first selected by a filter, amplified by a LNA and then frequency translated by a mixer to DC. Direct conversion needs more linear mixer to attain the same performance as heterodyne [6]. Although the implementation looks much simpler than heterodyne, homodyne faces more challenges in noise suppression. The practical way to improve any receiver system performance is by improving the sensitivity and the selectivity to reduce interference from unwanted sources. [7] A. DC Offset Figure 5. DC Offset leakage through mixer As discussed above the homodyne receiver down converts the signal to zero frequency. As a result any additional DC offset voltage will corrupt the down converted signal[6]. Later stages in the receiver will be saturated due to this offset. DC offset in Homodyne Receiver is more severe than Heterodyne architecture since most of the signal gain in direct conversion is in the base band block[4]. DC-offset appears mainly due to LO leakage. Constant DC-offset can be compensated by measuring it without signal and then subtracting it during reception. However in TDMA systems, different channels may have different signal levels and DC-offsets, therefore compensation is difficult. B. I/Q Mismatch (a) (b) (b) Figure 6. Effect of I-Q mismatch. Constellation (a) with gain error, (b) with phase error. 155

A Comparative Analysis between Homodyne and Heterodyne Receiver Architecture A homodyne receiver requires quadrature mixing. Mismatches between the amplitude of I and Q signal corrupt the down converted signal. Eventually it will raise the bit error rate. Heterodyne receiver may also have I/Q mismatch but their mismatch requirements are much more relaxed than homodyne[2]. I and Q paths are less sensitive to mismatches in this case. C. Even-order Distortion Figure 7. Even order product ( 2-1 ) very close to DC Let s consider two strong narrowband interference x(t)=a 1 Cos 1 t + A 2 Cos 2 t. A device with weak linearity can be represented by y(t)=b 1 x(t)+b 2 x 2 (t) With input x(t), y(t) will contain a term B 2 A 1 A 2 Cos( 2-1 ). If 1 is very close to 2 it will introduce interference close to base band or zero frequency. Differential LNA and mixer can be designed to suppress second order distortion or IP2[4]. However it requires higher power dissipation than a single ended design. In heterodyne receivers 2nd-order products on the signal band are attenuated by the RF filter. IV. Conclusion Heterodyne Receiver will have higher power consumption, since more stages are required in the architecture. Additional IF and RF filter requirement makes the integration low. In spite of these disadvantages Heterodyne receiver has been the primary choice for designers due to its better selectivity and ability to suppress image and other spurious emissions. Homodyne Receiver, on the other hand, has simple design architecture. It requires lower power consumption. ADC Dynamic range will have more margin due to limited filtering and integration will be high in practical implementation[3]. To obtain cost saving, direct conversion or homodyne receiver has become a popular architecture nowadays for wireless communication systems. References [1] Cotter W. Sayre, Complete Wireless Design. McGraw-Hill, 2001. [2] Behzad Razavi, RF Microelectronics, Prentice Hall Communication Engineering, 1998. [3] B. Razavi, Design Consideration for Direct Conversion Receiver, IEEE Trans. Circuits and Systems-II, Analog and Digital Signal Processing, vol44,no.6,pp428-435, June 1997. 156

Manarat International University Studies, 2 (1): 152-157, December 2011 [4] Qizeng Gu, RF System Design of Transceiver for Wireless Communications, Springer Science, 2005. [5] Ken Kundert, Accurate and Rapid Measurement of IP2 and IP3,Designer s guide consulting Inc, 2002 [6] A. A. Abidi, Direct Conversion Radio Transceiver for Digital Communications, IEEE Journal of Solid State Circuits, Vol.30,pp.1399-1410,December 1995. [7] A. Bensky, Short-range Wireless Communication: Fundamentals of RF System Design and Application, 2nd Edition, Amsterdam, -Newnes-Elsevier 2004 157