A 12 bit 125 MHz ADC USING DIRECT INTERPOLATION

Transcription

1 A 12 bit 125 MHz ADC USING DIRECT INTERPOLATION Dr R Allan Belcher University of Wales Swansea and Signal Conversion Ltd, 8 Bishops Grove, Swansea SA2 8BE Phone Fax rabelcher@signalconversion.co.uk Abstract - This paper describes the use of a Signal Analysis and Test System (SATS [5]) ADC test and simulation software package to simulate a 12 bit Direct Interpolation (DI) Analogue to Digital Conversion system. The simulation uses practical measurements of analogue to digital converter (ADC) thresholds obtained from an experimental 8 bit 2 GHz ADC. Results indicate that applying Direct Interpolation can increase spurious free dynamic range by up to 20 db without using calibration. This compares with a reported increase of up to 10 db for calibration based linearity compensation methods. Keywords: linearity, compensation, simulation, ADC. 1. INTRODUCTION The present trend for measuring instruments to use digital signal processing places the burden of analogue performance on the analogue to digital converter. Signal processing can be applied to correct for imperfections found in practical ADCs. In particular, digital signal processing (DSP) offers cost reduction as it removes the need for periodic adjustment. A spectrum analyser is probably the instrument that places greatest demands on the ADC performance. The key specifications for a spectrum analyser are noise spectral density and linearity. If the spectrum of a periodic signal is to be analysed, averaging can enable the effect of random noise to be reduced. In practice, Spurious free Dynamic range (SFDR) is the specification that is most difficult to improve. With analogue Spectrum Analysers, mixer linearity limits the SFDR. With digital Spectrum Analysers, the dynamic non-linearity of the ADC limits the SFDR. As most ADCs use a track-hold, this is a further source of non-linearity. In a complete wide-band ADC system, however, the dynamic non-linearity of the ADC usually exceeds that of the trackhold. Conventional methods of correcting dynamic nonlinearity in track-hold and ADC include code-mapping and phase-plane error correction [1]. An accurately known calibration signal is applied to the ADC under test and a code-map is generated that consists of offsets from the ADC output code. In normal operation, these offsets are added to the output codes from the ADC. Computer simulations show that this approach can be effective in increasing SFDR by 10 db or more. Unfortunately, a practical ADC has linearity errors that are affected by temperature and drift over a period of time. As correction offsets are measured only during calibration, code-mapping usually produces much less than 10 db improvement in SFDR in practice. High-order nonlinearity products are more difficult to correct for than loworder ones as they are sensitive to small changes in ADC linearity. In theory, SFDR due to high order products can be increased by using dither. Dither may be able to decorrelate the high order linearity error and therefore make it more like random noise. [2] Most often, dither is applied at an amplitude of several least significant bits (LSBs). This paper describes the results of applying Direct Interpolation (DI) [3] to increase the resolution of an 8 bit ADC to 12 bits. The SFDR of the 8 bit ADC is also increased by up to 20 db. 2. DIRECT INTERPOLATION Fig.1 depicts the main components of a DI-ADC. The input signal is sampled at a Nyquist rate of f s. Either a ramp or a staircase waveform may be used as the interpolation signal. If a ramp is employed then the fast or flash ADC Input Sample hold Sampling clock Interpolation waveform Interpolation generator Flash ADC Sampling clock period Fig. 1 Direct Interpolation Conversion clock Adder Output must have an aperture time short enough for the amplitude of the ramp to change by less than 1 LSB during this time. The ADC samples the ramp at instants of 1/f p where f p is the conversion clock of the fast ADC. In practice it may be more convenient to use a staircase instead of a ramp as the treads on the staircase allow the aperture requirements of the ADC to be relaxed. The staircase can be generated using a counter and DAC. It is possible to select the m bits of the DAC to provide the required number of sample points across the ramp. During the hold time 1/f s, the staircase interpolation waveform is added to the input of the fast ADC. This ADC makes one conversion for each tread on the staircase. A digital accumulator provides the average value of the ADC output code over the period 1/f s. Discontinuities in the linearity error characteristics are reduced by averaging Reset

2 several ADC results during one sampling period of the analogue input signal. Linearity errors due to drift etc are therefore compensated for on a sample by sample basis. It can, in principle, be used in combination with conventional code-mapping and phase-plane error correction. As the internal ADC converts at a rate greater than the Nyquist rate the ratio of these two rates is an oversampling factor of f p /f s. It is important to note, however, that oversampling of the input signal does not take place. For an ideal fast ADC, Direct Interpolation can be used to increase the resolution of the ADC by one bit per octave increase in oversampling factor. A 12 bit result from an 8 bit fast ADC therefore requires m=4 or an oversampling factor of 16 or four octaves. In general, the theoretical maximum increase in resolution of m bits is given by the following equation: f p m = log 2 f s Where f s the Nyquist sampling rate and f p is the conversion rate of the fast ADC. 3. TEST ARRANGEMENTS Practical measurements of ADC thresholds were obtained from an experimental 8 bit 2 GHz ADC. This ADC is now available as a production part, so the results presented can be used in further applications. The ADC manufacturer provided threshold values in a data file for use in the SATS simulator. These were measured using sine-wave histogram analysis with a 500 MHz test signal [4] and therefore indicate the worst case performance. A SATS [5] ADC test and simulation software package was used to simulate a DI ADC. This is a commercially available ADC/DAC simulator that enables arbitrary waveforms to be used and takes ADC threshold values from a data file. Results were obtained by averaging 16 ADC codes per sampling period. In theory, averaging 16 codes increases the ADC resolution by 4 bits. As the 8 bit ADC samples at 2 GHz, this produces a DI ADC system with a Nyquist sampling rate of 125 MHz and 12 bit resolution. The simulator was used to determine the optimum amplitude of interpolation waveform and dither waveform. This required iterative simluations and the results presented are best case. Optimum amplitude of interpolation waveform was about half full scale of the ADC. There is therefore a 6 db loss in dynamic range, but this is more than offset by the increase due to the use of Direct Interpolation. Single tone tests are often specified for the measurement and spurious free dynamic range. It is often the case that harmonics are ignored in the result. This can lead to an overoptimistic assessment in a practical application. The results presented here therefore take into account all spectral components in measuring SFDR. As a two-tone signal is more sensitive to non-linearity at signal frequencies near the Nyquist limit, this type of test is used in preference to single tone. A two-tone test signal was used with frequencies selected to fall in odd numbered FFT bins [6]. This minimises correlation between quantising error and the test signals. An ideal ADC should then produce a noise like error spectrum. Third order intermodulation distortion (IMD) and SFDR are key specifications in radio communication systems. As there is not yet an International Standard defining these terms, the following explanation of their use is given: Third order IMD Two tones f 1 and f 2 spaced apart by f Hz are applied at equal level and the level of each one on an FFT plot is taken as the 0 db reference. The amplitude of either of the third order products at f 1 - f and f 2 + f, relative to the 0 db reference is the third order IMD value. Fig. 2 ILE and DLE

3 "SINAD" SFDR IMD Input db 0 Fig. 4 Standard ADC with Dither input level db Fig. 3 Standard ADC SFDR The amplitude in db of the largest unwanted signal, including harmonic and intermodulation products, relative to the 0 db reference defined in the two-tone test. 4. RESULTS Plots of terminal based integral (ILE) and differential linearity error (DLE) were produced from Rockwell supplied threshold data. The new ADC thresholds produced by using DI were obtained by applying a simulated ramp to the DI system and calculating thresholds from a histogram analysis. Plots of ILE and DLE were then calculated from these thresholds. Fig. 2 shows these four results. The top two are without DI and the bottom two with DI. On the left is ILE. harmonic and intermodulation products and the lower mean value of the quantising error should improve SFDR. Probably one of the most revealing ways to test an ADC is to make measurements over a wide range of input signal amplitudes. Ideally, the signal to noise and distortion ratio (SINAD) should vary linearly with input level so that it behaves like an analogue system. A further feature that It is clear that DI randomises the ILE and DLE error plots. The sawtooth like ILE error characteristic is no longer evident after using DI. Results show that the periodicity and mean error of the ILE and DLE plots has been reduced. Peak to peak ILE is reduced to about one sixth that of the original. Randomisation should reduce the amplitude of high order

4 Results in 1 db steps : ADC alone (Fig. 3) with dither (Fig. 4) with DI and dither. (Fig. 5) Input db Fig. 5 Direct Interpolation with Dither Fig. 6 8 bit ADC

5 Fig. 7 8 bit ADC with DI would be desireable is for the linearity to improve as the test signal amplitude decreased. The periodic nature of quantisation noise makes this effect difficult to measure. Intemodulation products are measured using the power at the expected frequency positions. As can be seen from Fig 7, there appear to be no obvious third order products. The practical IMD figure may therefore be better than those obtained in the simulation. Further simulations using longer record lengths would be needed to investigate the limits of IMD performance. Experiments indicated that with this ADC a large amplitude sine-wave dither (about -15 db relative to FSR) was required to improve small signal SFDR. By comparing fig. 3 and fig. 4 it is clear that sine wave dither reduces SFDR for large signals. This is probably due to intermodulation products between the dither and the test signal being significant for large input signals. Dither can also be seen to linearise the signal to noise and distortion ratio (SINAD) plot and extend the dynamic range below the fig. 3 threshold of 44 db. In contrast, fig. 5 shows that the DI system, with dither, provides an increased SFDR for both large and small inputs. This is due to the increased linearity provided by DI. Two 16 k point FFT plots are shown to indicate the near full scale ADC performance in the spectrum analyser application, without dither. Fig. 6 applies to the ADC alone and fig. 7 to the DI ADC. These plots show an improvement in two-tone SFDR of about 20 db. The simulated result of 5.9 effective bits at near full scale range agrees closely with practical measurements taken at 500 MHz. Discontinuities in the INL characteristic of the 8 bit ADC produce wide-band spurious products from the two-tone test signal. DI reduces the amplitude and frequency of the INL discontinuities and can be seen to increase the SFDR significantly. As DI also increases resolution, the effective number of bits is increased. It is likely that significant improvement in effective bits could be obtained if code-mapping error correction is used with DI. This is to be the subject of a future publication. 4. CONCLUSIONS A 12 bit resolution ADC with a sampling rate of 125 MHz has been simulated. The experimental 8 bit ADC used is now available as a commercial product so the simulation results can be used in further applications. Direct Interpolation has been shown to be able to increase the full scale SFDR of a high speed ADC, with dither, by 20 db and to increase the third order IMD by 35 db. Results without the use of dither show that DI produces an even larger increase in SFDR and IMD. As DI reduces the drift sensitive high order linearity errors, it may improve the effectiveness of conventional correction and calibration techniques in a practical application. The analogue and digital circuitry required for DI at a much lower sampling rate have be produced previously [7] using integrated circuits so full integration would be the natural next step. 5. ACKNOWLEDGEMENTS Support from the Defence Evaluation Research Agency in undertaking this work is gratefully acknowledged. The threshold results for the 8 bit ADC are reproduced with permission of Rockwell Science Centre and their sponsors.

6 6. REFERENCES [1] Larrabee J H, Hummels D H, Irons FH, ADC compensation using a sinewave histogram method, Proceedings IEEE IMT Conference, Ottawa May 1997 [2] Belcher R A, Use of Dither in high speed ADC, Proceedings of IEE International Conference ADDA94, July [3] Belcher R A and Deravi F, A Direct Interpolation method for analogue to digital conversion, IEE proceedings on Circuits Devices and Systems, Feb, 1994 [4] DARPA Analogue to Digital Converter Demonstration Program. [5] SATS: Signal Analysis and Test System software produced by Signal Conversion Ltd ( [6] Halbert J M and Belcher R A, Selection of test signals for DSP based testing of digital audio systems, Journal of Audio Engineering Society, Vol.34, No 7/8, pp , July 1986 [7] Belcher R A, A 14 bit 400 ns ADC,IEE Colloquium on Advanced ADC and DAC techniques, London, May 1989.