Analogue-to-Digital Conversion

Transcription

1 Digital-to-Analogue to Conversion Analogue-to-Digital Conversion Module: EE2C2 Digital Design Lecturer: URL: j.b.grimbleby reading.ac.uk Number of Lectures: 8 Reference text: Design with Operational Amplifiers and Analog Integrated Circuits (3rd edition) Sergio Franco McGraw-Hill 2001 ISBN School of Systems Engineering - Electronic Engineering Slide 1

2 Digital-to-Analogue to Conversion Analogue-to-Digital Conversion Reference text: Design with Operational Amplifiers and Analog Integrated Circuits (3rd ed) Sergio Franco McGraw-Hill 2001 ISBN School of Systems Engineering - Electronic Engineering Slide 2

3 DAC and ADC Syllabus This course of lectures deals with methods for converting between analogue and digital representations of signals The topics that will be covered include: The conversion equation Precision The Nyquist frequency Quantisation Noise Voltage references Errors in ADCs and DACs Various types of DAC Various types of ADC School of Systems Engineering - Electronic Engineering Slide 3

4 DAC and ADC Prerequisites You should be familiar with the following topics: SE1EB5: Computer and Internet Technologies Binary codes Counters and encoders SE1EA5: Electronic Circuits Circuit analysis using Kirchhoff s Laws Thévenin and Norton's theorems The Superposition Theorem Semiconductor devices Complex impedances Frequency response function gain and phase The infinite-gain approximation SE1EC5: Engineering Mathematics School of Systems Engineering - Electronic Engineering Slide 4

5 Digital-to-Analogue to Conversion Most transducers generate analogue signals Signals are usually processed digitally, for example by a microprocessor or a dedicated DSP device Signals are usually transmitted and stored digitally, for example: pe DAB, DVB, CD, DVD, flash memory There is a need for some means of conversion between analogue and digital form, and between digital and analogue form Natural binary code is used in most cases School of Systems Engineering - Electronic Engineering Slide 5

6 Conversion Equation The digital signal will consist of an n-bit binary word B: B = b b b where b 1 is the most-significant bit (MSB) and b n is the least- significant bit (LSB) b n The fractional binary value D of this string is: D = b + 2 b + 2 b Range: 0 ~1 (1-2 -n ) Precision (absolute and relative) : 2 -n n b n School of Systems Engineering - Electronic Engineering Slide 6

7 Conversion Equation Digital words represent dimensionless numbers, whereas analogue signals are voltages The equation relating the analogue voltage v a and the digital it signal B must contain a reference voltage v ref v a = v ref n { 2 b1 + 2 b2 + 2 b b n } The reference voltage v ref is typically in the range 1V to 10V, and must be accurate and stable v ref is usually generated by a voltage reference circuit School of Systems Engineering - Electronic Engineering Slide 7

8 Precision The smallest increment in output voltage of an n-bit DAC with reference voltage v ref is: 2 -n v ref The maximum output of the DAC is: v ref Thus the absolute precision of the DAC is 2 -n v ref and the relative precision of the DAC is 2 -n v ref /v ref = 2 -n A 10-bit DAC has a relative precision: = % School of Systems Engineering - Electronic Engineering Slide 8

9 Precision Suppose that the digitised output from a photo-sensor is required to be accurate to 0.05% This means that the relative precision of the DAC (2 -n ) must be better than : n n log log = 10 log 2 2 = Since 11-bit DACs are not generally available the natural choice for this application would be a 12-bit converter School of Systems Engineering - Electronic Engineering Slide 9

10 Precision Suppose that a digital voltmeter must measure voltages to an accuracy of 1 μv in 10 V This means that the relative precision of the DAC (2 -n ) must be better than : 2 n log n log = = log Thus an appropriate choice for this application would be a 24-bit converter School of Systems Engineering - Electronic Engineering Slide 10

11 Nyquist Frequency Digital systems process samples of continuous analogue signals at discrete intervals T s =1/f s Nyquist-Shannon Sampling Theorem: When sampling a signal at discrete intervals the sampling frequency f s must be greater than twice the highest frequency f 0 of the input signal in order to be able to reconstruct the original perfectly from the sampled version The minimum sampling frequency f s that allows reconstruction of the original signal is known as the Nyquist frequency Sampling at less than the Nyquist frequency causes aliasing School of Systems Engineering - Electronic Engineering Slide 11

12 Nyquist Frequency Correctly sampled: Input signal Aliased signal Under-sampled: Input signal f 0 2f 0 f s Aliased signal Aliasing f 0 f s 2f 0 School of Systems Engineering - Electronic Engineering Slide 12

13 Bipolar DACs and ADCs Unipolar DACs and ADCs operate over the analogue voltage range 0 to v : ref n bn v a = vref { 2 b1 + 2 b b Bipolar DACs and ADCs operate over the analogue voltage range -v ref to v ref } v ref v ref 0V Unipolar 0V -v ref Bipolar School of Systems Engineering - Electronic Engineering Slide 13

14 Bipolar DACs R R v ref B n v ref Unipolar DAC B v a 0 v ref v s ref v ref v v ref v + s = va vs = 2v 2 2 a v ref School of Systems Engineering - Electronic Engineering Slide 14

15 Bipolar ADCs v s v ref v ref R R v a 0 vref Unipolar ADC v a vref B n v ref v v v ref s a = School of Systems Engineering - Electronic Engineering Slide 15

16 Voltage Reference All DACs and ADCs require a voltage reference v ref Types of voltage reference: Band-gap Zener diode Considerations: Initial accuracy Long term stability Temperature coefficient Output noise Line and load regulation Cost School of Systems Engineering - Electronic Engineering Slide 16

17 Band-Gap Voltage Reference Band-gap voltage references are always integrated 2 bipolar transistors with unequal emitter areas are operated at the same current. The output is the voltage across one junction plus λ times the difference between the junction voltages If λ is correctly chosen then the output voltage temperature coefficient i is zero The output t voltage is related to the band-gap of the semiconductor material (1.2 V for Si) School of Systems Engineering - Electronic Engineering Slide 17

18 Band-Gap Voltage Reference Example: National Semiconductors LM4121 Nominal output voltage: v OUT 1.25 V Initial accuracy: Δv OUT : 0.2 % Long term stability Δv OUT : 100 ppm/1000 hrs Temperature coeff (Δv OUT / ΔT): 50 ppm/ºc Output noise: 20 μv pk-pk ( Hz) Line regulation (Δv OUT / Δv IN ): 90 ppm/v Load regulation (Δv OUT / Δi OUT ): 400 ppm/ma = 05Ω 0.5 Ω Cost: 0.4 School of Systems Engineering - Electronic Engineering Slide 18

19 Zener Diode Voltage Reference Zener diode voltage references are based on the reverse breakdown voltage of junction diodes The reverse breakdown voltage is relatively independent of current Zener diodes with breakdown voltages less than 5.6 V have negative temperature coefficients Zener diodes with breakdown voltages greater than 5.6 V have positive temperature coefficients Best stability obtained at breakdown voltages around 5.6 V School of Systems Engineering - Electronic Engineering Slide 19

20 Zener Diode Voltage Reference 1 r d = Slope Symbol: 5.6V Current i Z 10mA Forward conduction Voltage v Z Reverse 0.6V conduction -10mA School of Systems Engineering - Electronic Engineering Slide 20

21 Zener Diode Voltage Reference Zener diode Small-signal model i Z Dynamic resistance r d v Z r d = dv di Z Z v Z0 School of Systems Engineering - Electronic Engineering Slide 21

22 Zener Diode Voltage Reference Example: NTE5011A Nominal zener voltage v Z : 5.6V Operating current i Z : 20 ma Temperature coeff (Δv Z / ΔT): 380 ppm/ºc Dynamic resistance r d (Δv Z/ Δi Z ):11 Ω Cost: 0.05 Zener diodes require additional circuitry to act as voltage references School of Systems Engineering - Electronic Engineering Slide 22

23 Zener Diode Voltage Reference Temperature stabilised zener diodes use a thermostat to maintain the diode at a constant temperature Example: National Semiconductors LM399 Nominal zener voltage v Z : 6.95V Operating current i Z : 1 ma Temperature coeff (Δv Z / ΔT): 2 ppm/ºc Dynamic resistance r d (Δv Z / Δi Z ): 1 Ω Cost: 4.40 School of Systems Engineering - Electronic Engineering Slide 23

24 Simple Zener Diode Reference R i Z v s Voltage reference is powered by supply i out voltage v s v out Resistor R provides the zener current together with any load current School of Systems Engineering - Electronic Engineering Slide 24

25 Simple Zener Diode Reference Small-signal equivalent circuit: R r d v Z0 v s Δi out Δv out Load regulation: r Δvout = Δiout r Δv Δi out out r d d d Supply regulation: Δv Δ v Δv out out S = Δv rd R S r d r d + R + R R School of Systems Engineering - Electronic Engineering Slide 25

26 Simple Zener Diode Reference 12V Load regulation: 320Ω 5.6V Δv Δ i out Δ out = r d = 11 Ω = 11mV/mA 20mA Supply regulation: Δv Δv out v S r 11 d = = 3% R 320 School of Systems Engineering - Electronic Engineering Slide 26

27 Improved Zener Diode Reference 12V Load regulation: 320Ω 5.6V Δv out Δ i out 0 20mA Supply regulation: Δv Δv out v S r 11 d = = 3% R 320 School of Systems Engineering - Electronic Engineering Slide 27

28 Improved Zener Diode Reference R 0 IGA: v Z v OUT v Z = v out R 1 R + 2 R 1 R + R 1 v 1 out = v Z 1+ R2 v v R i out i Z Z R = 2 0 Z 2 School of Systems Engineering - Electronic Engineering Slide 28

29 Improved Zener Diode Reference 440Ω 5.6V 10V 44kΩ Load regulation: Δv out Δi out 0 10mA 56kΩ Supply regulation: Δv Δ v out Δ S 0 School of Systems Engineering - Electronic Engineering Slide 29

30 Integrated Zener Diode Reference Example: Analog Devices AD586 Nominal output voltage: v OUT 5.00 V Initial accuracy: Δv OUT 0.05 % Long term stability Δv OUT : 15 ppm/1000 hrs Temperature coeff (Δv OUT / ΔT): ) 10 ppm/ºc Output noise: 4 μv pk-pk ( Hz) Line regulation (Δv OUT/ Δv IN) ): 30 ppm/v Load regulation (Δv OUT / Δi OUT ): 30 ppm/ma = 0.15 Ω Cost: 3.80 School of Systems Engineering - Electronic Engineering Slide 30

31 Digital-to-Analogue to Converters DACs Resistor ratio DACs Mark/space DACs Weighted- R/2R ladder PWM resistor DAC DAC DAC Potentiomentric DAC Delta-sigma DAC School of Systems Engineering - Electronic Engineering Slide 31

32 Errors in DACs: Ideal Response Voltag ge v a v ref = 1.0 V gue Output Analo n vref Digital Input Word B School of Systems Engineering - Electronic Engineering Slide 32

33 Errors in DACs: Offset Voltag ge v a v ref = 1.0 V gue Output Analo Digital Input Word B School of Systems Engineering - Electronic Engineering Slide 33

34 Errors in DACs: Scaling Voltag ge v a v ref = 1.0 V gue Output Analo Digital Input Word B School of Systems Engineering - Electronic Engineering Slide 34

35 Errors in DACs: Non-Linearity Voltag ge v a v ref = 1.0 V gue Output Analo Digital Input Word B School of Systems Engineering - Electronic Engineering Slide 35

36 Errors in DACs: Non-Monotonicity Voltag ge v a v ref = 1.0 V gue Output Analo Digital Input Word B School of Systems Engineering - Electronic Engineering Slide 36

37 Errors in DACs: Differential Non-Linearity Differential non-linearity: maximum difference between an actual step size and the ideal step size (1 lsb) Ideal step Actual step n v 2 v ref Differential non-linearity School of Systems Engineering - Electronic Engineering Slide 37

38 Errors in DACs: Integral Non-Linearity Integral non-linearity: maximum difference between actual analogue voltage and straight line between endpoints ue Ou utput Analog Ideal Integral non-linearity it Actual Digital Input School of Systems Engineering - Electronic Engineering Slide 38

39 Single-Bit DAC Logic-level voltages are not accurate enough to be used directly in DACs For the HCT logic family: Logic 0 Logic V V By contrast the analogue voltages in a 12-bit DAC must be accurate to 0.024% 024% Instead the logic levels els are used to drive the gates of MOSFET switches School of Systems Engineering - Electronic Engineering Slide 39

40 Voltage-Mode Single-Bit DAC v ref Logic input b Q 1 Analogue output v a Q 2 Q 1 Q 2 v a b=0 off on 0 v a = b v ref b=1 on off v ref School of Systems Engineering - Electronic Engineering Slide 40

41 Weighted-Resistor DAC v ref 2R 4R 8R 2 n R b 1 b 2 b 3 b n R v a v v R a a b 1 v + ref b2v + ref b + 3vref b v n ref 0 2 R 4 R 8 R n 2 R = = v ref n b n { 2 b1 + 2 b b 3 } School of Systems Engineering - Electronic Engineering Slide 41

42 Voltage-Mode R-2R Ladder DAC R-2R ladder DACs have the advantage of only using a single value of resistance (2R=R+R) R R R v a 2R 2R 2R 2R 2R b 8 b 7 b 2 b 1 v ref School of Systems Engineering - Electronic Engineering Slide 42

43 Voltage-Mode R-2R Ladder DAC Derive Thevenin equivalent of left-most 1-bit DAC and parallel resistance: 2R R 2R b 8 v ref b 8 v ref /2 School of Systems Engineering - Electronic Engineering Slide 43

44 Voltage-Mode R-2R Ladder DAC R R 2R R b 8 v ref /2 b 7 v (b ref 7 V ref +b 8 V ref /2)/2 School of Systems Engineering - Electronic Engineering Slide 44

45 Voltage-Mode R-2R Ladder DAC R R 2R R b 6 v ref (b 7 v ref +b 8 v ref /2)/2 (b 6 v ref +(b 7 v ref +b 8 v ref /2)/2)/2 School of Systems Engineering - Electronic Engineering Slide 45

46 Voltage-Mode R-2R Ladder DAC R v a v a = = = ( b v v 1 ref v ref ref ( b (2 + ( b v + ( b b 1 ref b b 2 2 b v ref / 2)/ 2)/ 2)/ 2)/ 2)/ 2)/ 2)/ / 2)/ 2)/ 2)/ 2)/ 2)/ 2)/ 2)/ 2) 2 3 b b 8 ) 2) School of Systems Engineering - Electronic Engineering Slide 46

47 Current-Mode R-2R Ladder DAC R R R v ref 2R 2R 2R 2R 2R b 1 b 2 b 7 b 8 i a Output i a is connected to the virtual ground of an op-amp with feedback resistor R School of Systems Engineering - Electronic Engineering Slide 47

48 Current-Mode R-2R Ladder DAC Example: Analog Devices AD7545 Number of bits: 12 Integral latch: yes Differential non-linearity: ±1 lsb Gain error: ±10 lsb Settling time: 2 μs Gain temperature coeff: ±5 ppm/ºc Cost: 10 School of Systems Engineering - Electronic Engineering Slide 48

49 Potentiometric DAC Potentiometric DACs generate each of the possible 2 n output voltages by means of a resistor chain Potentiometric DACs have excellent linearity and are inherently monotonic Potentiometric DACs are complex, requiring 2 n resistors and 2 n+1-2 MOSFET switches Consequently they are expensive and are only available in a limited number of bits School of Systems Engineering - Electronic Engineering Slide 49

50 Potentiometric DAC R b 3 (lsb) b 2 b 1 (msb) v ref R R R R R R R Input word = v a School of Systems Engineering - Electronic Engineering Slide 50

51 Pulse-Width Modulation DAC PWM DACs use a counter to generate a digital waveform with a duty cycle proportional to the n-bit input B: 1 0 B clock cycles 2 n clock cycles This waveform is converted to an analogue signal by a single-bit DAC, and low-pass filtered PWM DACs are simple to implement, and have very good differential linearity School of Systems Engineering - Electronic Engineering Slide 51

52 Pulse-Width Modulation DAC Analogue waveform: v ref 0 B T c 2 n T c where T c = 1/f c is the period of the clock; then the average analogue voltage v a is: v a = c ref n n { B T v + (2 B ) T 0} /(2 T = v B / 2 ref Frequency of PWM waveform is f p = f c /2 n ; components at this frequency must be removed by low-pass filtering c n c ) School of Systems Engineering - Electronic Engineering Slide 52

53 Pulse-Width Modulation DAC Input B n Modulo-2 n counter Comparator B A<B n A 1-bit DAC Filter cut-off f 0 v a V r Clock f c Filter cut-off frequency f 0 must be much less than PWM frequency f p to achieve sufficient rejection of PWM component; it follows that signal frequency must also be much less than f p School of Systems Engineering - Electronic Engineering Slide 53

54 Pulse-Width Modulation DAC Clock A B A<B v a School of Systems Engineering - Electronic Engineering Slide 54

55 Pulse-Width Modulation DAC Digital input B: PWM waveform: School of Systems Engineering - Electronic Engineering Slide 55

56 Pulse-Width Modulation DAC The largest a.c. component occurs when the input word is 2 n-1 (or half full-scale): the output from the 1-bit dac is then a square wave of frequency f p = f c /2 n : v ref 0 2 n T c Amplitude of fundamental component: b 1 π 1 = π 0 v ref sint dt vref π 2v = [ cost] π 0 = π ref School of Systems Engineering - Electronic Engineering Slide 56

57 PWM DAC Output Filter Gain=1 log Gain Signal frequency Filter Cut-off PWM frequency n 0 n f Gain f (Butterworth) log Frequency f s f 0 f p 2f p 3f p School of Systems Engineering - Electronic Engineering Slide 57

58 PWM DAC Output Filter Design Example: 12-bit DAC with f c = 10 MHz PWM frequency: f p = 10 MHz / khz Worst-case amplitude before filtering: i 2v ref /π = V ref Worst-case pk-pk before filtering: 1.28v ref Maximum pk-pk after filtering: v ref /4096 = v ref Maximum filter gain at f p = / /1 28 = Filter: 3rd-order Butterworth, cut off frequency f 0 Gain of filter above cut-off = f 03 / f 3 f f f f 3 p = p 146 Hz School of Systems Engineering - Electronic Engineering Slide 58

59 Over-Sampling DACs Delta-Sigma DACs use over-sampling, together with a 1-bit converter Over-sampling means that the clock frequency f c is much greater than the Nyquist frequency 2f 0 : f 0 2f 0 f c This greatly simplifies the design of the analogue output filter School of Systems Engineering - Electronic Engineering Slide 59

60 Delta-Sigma DAC A Delta-Sigma DAC consists of an input digital filter, Delta- Sigma Modulator, 1-bit DAC and analogue output filter: B Digital Delta-Sigma Latch n n filter n Modulator 1 1-bit DAC v a Sampling Clock f s Converter Clock f c Bitstream b Output filter School of Systems Engineering - Electronic Engineering Slide 60

61 Delta-Sigma DAC Digital Delta-Sigma Modulator: DDC (0 or 2 n ) B (-2 n ) Q+B (-2 n ) n+1 Delta n section B n n+1 h + 1 Σ Σ D Q h n+1 n+1 n Comparator >= 2 n Sigma Clock f section c Q Q+B (-2 n ) b School of Systems Engineering - Electronic Engineering Slide 61

62 Delta-Sigma DAC Negative feedback keeps the output of the sigma section around 2 n The average input to the sigma section must therefore be zero: n B m 2 = 0 or m = B / 2 where m is the proportion of 1s in the digital output stream The average output voltage from the 1-bit DAC is given by: v = mv = v B / 2 a ref ref n n School of Systems Engineering - Electronic Engineering Slide 62

63 Delta-Sigma DAC The Delta-Sigma Modulator generates a 1-bit bitstream from the n-bit digital input The bitstream is a stream of pulses, one clock cycle wide where the average proportion of logic 1 pulses is B/2 n This waveform is converted to an analogue signal by a single-bit DAC, and low-pass filtered Delta-Sigma DACs have very good linearity and can handle higher signal frequencies than PWM DACs School of Systems Engineering - Electronic Engineering Slide 63

64 Delta-Sigma DAC The digital bit-stream repeats every 2 n clock cycles For example a 4-bit DAC, B=11: 1 0 T c 2 n T c =16T c Analogue waveform: v ref 0 T c 2 n T c = 16T c v = { 11 T v + 5 T 0} /(16 T ) = v a c ref c c ref School of Systems Engineering - Electronic Engineering Slide 64

65 Delta-Sigma DAC Digital input B: Delta-Sigma waveform: School of Systems Engineering - Electronic Engineering Slide 65

66 Delta-Sigma DAC The lowest frequency output component occurs at f p = f c/2 n when the input is 1 or 2 n -1: v ref 0 T c 2 n T c Amplitude of fundamental component: a n 1 2π / 2 1 = vref π 0 v = ref π cos t d t n 2π v v 2π / 2 [ sint] 0 = ref = ref n n 1 2 π 2 School of Systems Engineering - Electronic Engineering Slide 66

67 Delta-Sigma DAC Output Filter Design Example: 12-bit DAC with f c = 10 MHz PWM frequency: f p = 10 MHz / khz Worst-case amplitude before filtering: v ref /2048 = v00049v ref Worst-case pk-pk before filtering: v ref Maximum pk-pk after filtering: v ref /4096 = v ref Maximum filter gain at f p = / = 0.25 Filter: 3rd-order Butterworth, cut off frequency f 0 Gain of filter above cut-off = f 03 / f 3 f f f0 0.63f 3 p = p 1575 Hz School of Systems Engineering - Electronic Engineering Slide 67

68 Analogue-to-Digital Conversion ADCs do not operate continuously, but sample the analogue signal at discrete times and convert the sampled signal to digital form. The fastest ADCs are used, for example, to digitise television signals at a rate of 13 Msps, but have limited it precision i At the other extreme are very accurate ADCs which take up to 1 s to perform a conversion. All n-bit ADCs make use of one or more 1-bit ADCs ADCs should normally be preceded by a low-pass antialiasing filter School of Systems Engineering - Electronic Engineering Slide 68

69 Analogue-to-Digital Conversion ADCs Flash ADCs Feedback ADCs Slope ADCs Tracking ADC Singleslope ADC Sigma- delta ADC Successive approximation ADC Dualslope ADC School of Systems Engineering - Electronic Engineering Slide 69

70 Anti-Aliasing Aliasing Filters Anti-aliasing filters are used to limit the bandwidth of the incoming signal to prevent aliasing Filter cut-off frequency is determined by the highest frequency component f a of the required signal Worst-case situation: all signals above f s /2 must be reduced in amplitude to less than 1 lsb (2 -n ) Thus filter gain at f s /2 must be less than 2 -n s School of Systems Engineering - Electronic Engineering Slide 70

71 Anti-Aliasing Aliasing Filters Gain=1 log Gain Required signal frequency components Filter Cut-off Sampling frequency Gain 2 n log Frequency f a f s /2 f s School of Systems Engineering - Electronic Engineering Slide 71

72 Anti-Aliasing Aliasing Filters Suppose that t a 12-bit ADC is required to digitise iti an audio signal with frequency components up to 12 khz The Nyquist frequency is therefore 24 khz Clearly the sampling frequency must be more than 24 khz, but how much more? Choice of sampling frequency is a compromise between: - reducing conversion speed and digital data rate, and - complexity of the anti-aliasing filter School of Systems Engineering - Electronic Engineering Slide 72

73 Anti-Aliasing Aliasing Filters Choose sampling frequency to be 32 khz Low-pass filter specification: Pass-band edge: Hz Min pass-band gain: -3 db Stop-band edge: Hz Min stop-band gain: -72 db (2-12 ) This specification can be met by a 7-th order Elliptic filter This is quite complex it may be preferable to increase the sampling frequency to simplify the anti-aliasing filter School of Systems Engineering - Electronic Engineering Slide 73

74 Quantisation Noise v ref Sampled analogue signal Analogue signal -v ref School of Systems Engineering - Electronic Engineering Slide 74

75 Quantisation Noise v ref Quantised sampled signal (9-bit ADC) Quantisation error -v ref School of Systems Engineering - Electronic Engineering Slide 75

76 Quantisation Noise +1lsb v ref /2 n Quantisa ation error 0-1lsb -v n ref /2 School of Systems Engineering - Electronic Engineering Slide 76

77 Quantisation Noise An n-bit ADC has 2 n quantisation levels and the interval between levels (the quantisation step) is q = v ref /2 n The maximum quantisation error is ±q/2 The quantisation error ε for each sample is assumed to be random and evenly distributed in the range ±q/2 Probability p(ε) -q/2 0 +q/2 Error ε School of Systems Engineering - Electronic Engineering Slide 77

78 Quantisation Noise The rms quantisation noise voltage e rms is therefore: e rms = = = = 1 + q / 2 q q / ε q 3 3 ε 2 d + q / 2 q / 2 3 ε 1 q q + q q 12 School of Systems Engineering - Electronic Engineering Slide 78

79 Signal-to-Quantisation-Noise Ratio Maximum sinusoidal signal voltage: v Amplitude of sinusoid = ref 2 v v = ref 2 2 v ref rms 0 Signal-to-noise i ratio: v rms e rms rms = v = v ref ref n /(2 /( n 2) 12) n 3 = 2 ( = 6.02n db) 2 School of Systems Engineering - Electronic Engineering Slide 79

80 Signal-to-Quantisation-Noise Ratio Audio CDs use 16-bit encoding of the audio signal, which leads to a signal-to-noise ratio of: S/N = 6.02 n db = 98 db An audio signal is required to have a signal-to-noise ratio of 60 db: 6.02n = 60 n = = 9.67 A 10-bit converter would provide the required signal-to-noise ratio School of Systems Engineering - Electronic Engineering Slide 80

81 Quantisation Noise When a signal is sampled at frequency f s = 1/T all of its power folds into the frequency band 0 f s /2 If the quantisation noise is white then the spectral noise density E(f) is: e E ( f ) = rms f / 2 = e = 2 s rms v ref n 12 2 f s v 2 = ref n s 2 f 6f s (V rms / Hz) School of Systems Engineering - Electronic Engineering Slide 81

82 Input Multiplexing Some ADCs incorporate input mutiplexing i This allows a single ADC to convert analogue voltages from a number of sources v a1 v a2 v a3 v a Analogue- to-digital converter n B v a4 School of Systems Engineering - Electronic Engineering Slide 82

83 Single-bit ADC The single bit ADC is simply a voltage comparator, and has the same symbol as an operational amplifier: v p v n b v p and v n are analogue voltages; b is a digital signal: v p > v n : b = 1 v p v n : b =0 A typical comparator is the type LM311 School of Systems Engineering - Electronic Engineering Slide 83

84 Flash ADC Flash converters are so-called because they are the fastest type of ADC (up to 1 Gsps) Flash ADCs can only be obtained with a limited precision (up to about 8 bits), are expensive and consume a considerable amount of power Flash ADCs perform 2 n -1 single-bit conversions in parallel, where n is the number of bits The output of the comparators is converted to n-bit parallel form by combinational logic (a priority encoder) School of Systems Engineering - Electronic Engineering Slide 84

85 Flash ADC Analogue input Reference voltage v a v ref R 0.875v ref R R R R R R R Y v ref Y 6 Pi Priorityit 0.625v ref encoder 0.500v ref 0.375v ref Y 5 Y 4 Y v ref Y 2 A b v ref Y 1 B b 2 1 Y 0 C b 1 2 School of Systems Engineering - Electronic Engineering Slide 85

86 Flash ADC Example: Maxim Max104 Number of bits: 8 Conversion time: 1 ns (1 Gsps) Differential non-linearity: ±0.25 lsb Integral non-linearity: ±0.25 lsb Gain error: ±2 lsb Offset error: ±2 lsb Power consumption (v s= ±5 V): 5 W Integral sample-and-hold: no Digital interface: positive ECL Analogue input multiplexing: no Cost: 495 School of Systems Engineering - Electronic Engineering Slide 86

87 Half-Flash ADC By performing the conversion in two steps it is possible to reduce the complexity of flash converters, at the expense of some loss of speed 4-bit flash 4-bit + 4-bit v - a flash ADC DAC ADC v ref v ref b 1.. b 4 b 5.. b 16 8 This half-flash converter uses 30 comparators to achieve an 8-bit precision, compared with 255 comparators for a full 8-bit flash ADC School of Systems Engineering - Electronic Engineering Slide 87

88 Half-Flash ADC v ref =1 V ref V V v a =0.7 V V V v ref =1/16 V v ref Voltage difference ( V) is applied to second converter 0 V 0 V 1st ADC DAC output 2nd ADC 1011 (11 dec) 11/16 v ref 0011 (3 dec) School of Systems Engineering - Electronic Engineering Slide 88

89 Half-Flash ADC Example: Maxim MAX118 Number of bits: 8 Conversion time: 660 ns (1.5 Msps) Differential non-linearity: ±1.0 lsb Integral non-linearity: ±1.0 lsb Gain error: ±1.0 lsb Offset error: ±1.0 lsb Power consumption (v s=5 V): 40 mw Integral sample-and-hold: no Digital interface: parallel tri-state Analogue input multiplexing: yes (8 channels) Cost: 5.85 School of Systems Engineering - Electronic Engineering Slide 89

90 Tracking ADC The tracking ADC is one of a number of techniques which employ a DAC in a negative-feedback loop v a v b - u/d Up/dn + counter DAC v b Clock b 1.. b n v ref When the DAC output v b is below v a the u/d input is 1 and the counter counts up School of Systems Engineering - Electronic Engineering Slide 90

91 Tracking ADC v a 1 lsb v b u/d clk School of Systems Engineering - Electronic Engineering Slide 91

92 Tracking ADC Clock frequency enc must be chosen to let DAC output t and comparator settle after change in digital word Typical DAC settles in 1 μs f clk = 1 MHz Advantages: Simplicity - constructed from standard logic devices Digital output tracks slow input voltage changes Disadvantages: Up to 2 n clock periods required before digital output is valid following a large change in analogue input School of Systems Engineering - Electronic Engineering Slide 92

93 Successive-Approximation ADC The successive-approximation ADC is one of a number of techniques which employ a DAC in a feedback loop. SC EOC v b - + SAR DAC v b v a Clock b1.. bn v ref School of Systems Engineering - Electronic Engineering Slide 93

94 Successive-Approximation ADC When SC goes high (active) the SAR sets EOC low (inactive) and sets all the bits b 1..b n to 0. Over the next n clock periods the SAR performs the following operations: b 1 = 1: if v a < v b = v ref {1/2} then b 1 =0 b 2 = 1: if v a < v b = v ref {b 1 /2 + 1/4} then b 2 =0 b 3 = 1: if v a < v b = v ref {b 1 /2+b 2 /4+1/8} then b 3 = Finally EOC is set high (active) School of Systems Engineering - Electronic Engineering Slide 94

95 Successive-Approximation ADC V V V V v V a V V V V V V V V V V V 0000 v b School of Systems Engineering - Electronic Engineering Slide 95

96 Successive-Approximation ADC Successive-approximation ADCs require n operations to perform the complete conversion The conversion must be initiated, and during the conversion period the data on the lines b 1..b n are invalid The input must not change during the conversion o process: successive approximation ADCs are often preceded by an analogue sample-and-hold circuit. A typical 12-bit successive approximations ADC takes 12 μs to perform a complete conversion School of Systems Engineering - Electronic Engineering Slide 96

97 Analogue Sample and Hold Control signal H S H S H S H S H S H Input Output During sample period the output follows the input During hold period the output remains constant School of Systems Engineering - Electronic Engineering Slide 97

98 Analogue Sample and Hold R Input C Output When switch is closed the output voltage follows the input voltage (sample) When switch is open the voltage on the capacitor, and therefore the output voltage remains constant (hold) School of Systems Engineering - Electronic Engineering Slide 98

99 Successive-Approximation ADC Example: Texas Instruments t TLC2543 Number of bits: 12 Conversion time: 10 μs (10 5 sps) Differential non-linearity: ±1 lsb Integral non-linearity: ±1 lsb Gain error: ±1 lsb Offset error: ±1.5 lsb Power consumption (v s =5V): 5mW Integral sample-and-hold: yes Digital interface: serial Analogue input multiplexing: yes (11 channels) Cost: 7.94 School of Systems Engineering - Electronic Engineering Slide 99

100 Over-Sampling ADCs Sigma-delta ADCs use over-sampling, together with a 1-bit converter Over-sampling means that the clock frequency f c is much greater than the Nyquist frequency 2f 0 : f 0 2f 0 f c This greatly simplifies the design of anti-aliasing filter School of Systems Engineering - Electronic Engineering Slide 100

101 Sigma-Delta ADC A Sigma-Delta ADC consists of a delta-sigma modulator, digital filter/decimator and output latch: Bitstream b v a Delta-Sigma Modulator 1 Digital filter n Latch n B Converter Clock f c Sampling Clock f s School of Systems Engineering - Electronic Engineering Slide 101

102 Δ-Σ Modulator Analogue delta-sigma modulator: v a + - Σ (0 or v ref ) Comparator 1 1-bit DAC 1 D Q 1 Bitstream b Voltage integrator Clock f c School of Systems Engineering - Electronic Engineering Slide 102

103 Δ-Σ Modulator Input v a v a - b.v ref Integrator Bitstream b Clock f c School of Systems Engineering - Electronic Engineering Slide 103

104 Δ-Σ Modulator Over a large number M of clock cycles: ( v - b. v ) dt 0 a b =1 for m of these cycles, and b=0 for M-m cycles: mt c ref ( va - vref ) ( M m) Tcva mt v + MT v 0 c ref MT v m c a T v = c ref + 0 c a v M v So the proportion m/m of cycles for which b =1 is directly proportional to the input voltage v a a ref School of Systems Engineering - Electronic Engineering Slide 104

105 Linearised Δ-Σ Modulator Noise Linearised Δ Σ Modulator Noise Model Quantisation noise Integrator X(jω) h Σ - + Σ + jωt 1 Y(jω) E(jω) + jωt j Y j X j E j Y ω ω ω ω + = ) ( ) ( ) ( ) ( (j ) j Y j X j E T j j T Y j T j j E j Y ω ω ω ω ω ω ω ω ω + = + ) ( ) ( ) (. ) (. ) ( ) ( T j j X j E T j j Y j j j j j j ω ω ω ω ω + + = 1 ) ( ) (. ) ( ) ( ) ( ) ( ) ( School of Systems Engineering - Electronic Engineering Slide 105 jωt 1+

106 Linearised Δ-Σ Modulator Noise I t t l f db k t l filt t th i l Linearised Δ Σ Modulator Noise Model Integrator plus feedback acts as a low-pass filter to the signal and a high-pass filter to the quantisation noise: 1 ) ( ) ( T j T j j E j Y + = ω ω ω ω 2 1 where : / 1 / ) ( ) ( f T f f j f f j f E f Y = + = π / ) ( 2 / f f f E f f f j + π / 1 ) ( f f f E + = Hz) / (V / 1 / 6 2 rms f f f f f v c ref + = School of Systems Engineering - Electronic Engineering Slide c

107 Linearised Δ-Σ Modulator Noise Model Signal Shaped-spectrum quantisation noise RMS Voltage Y(f) f s Frequency f c/2 School of Systems Engineering - Electronic Engineering Slide 107

108 Sigma-Delta ADC 1-bit DAC 1 b 1.. b n v a + - Σ 1 D Q 1 Digital filter Clock f c The output filter performs two functions: Low-pass filter (to reduce the shaped quantisation noise) Decimation (reducing the data rate from f c to f s ) School of Systems Engineering - Electronic Engineering Slide 108

109 Sigma-Delta ADC The output filter converts the 1-bit data stream to an n-bit word It also filters out quantisation noise and performs decimation to reduce the output t data rate A typical Sigma-Delta ADC might clock at 64 times the sample frequency The output filter will then provide 64:1 decimation so that the output rate is equal to the sample frequency In its simplest form the output filter could be a counter School of Systems Engineering - Electronic Engineering Slide 109

110 Sigma-Delta ADC Most of the circuitry it in Sigma-Delta converters is digital it Sigma-Delta converters are inherently monotonic Sigma-Delta converters are inherently linear and exhibit little differential non-linearity Sigma-Delta converters do not require an external sample and hold Sigma-Delta converters are capable of very high precision, but have a limited sampling rate School of Systems Engineering - Electronic Engineering Slide 110

111 Sigma-Delta ADC Example: Maxim Max1132 Number of bits: 16 Conversion time: 5 μs (200 ksps) Differential non-linearity: ±1 lsb Integral non-linearity: ±2 lsb Gain error: ±120 lsb Offset error: ±20 lsb Power consumption (v s =5V): 50 mw Digital interface: serial Analogue input multiplexing: no Cost: 8.50 School of Systems Engineering - Electronic Engineering Slide 111

112 Sigma-Delta ADC Example: Burr-Brown B ADS1211 Number of bits: 24 Conversion time: 100 ms (10 sps) Differential non-linearity: ±1 lsb Integral non-linearity: ±2500 lsb Gain error: ±4 lsb Offset error: ±4 lsb Power consumption (v s =5V): 10 mw Digital interface: serial Analogue input multiplexing: no Cost: School of Systems Engineering - Electronic Engineering Slide 112

113 Single-Slope Slope ADC Slope converters avoid the use of a DAC, and instead use an integrator to produce a voltage ramp v -v ref R + - C v b v a R S CE b 1.. b n Counter Clock School of Systems Engineering - Electronic Engineering Slide 113

114 Single-Slope Slope ADC Clock v b v a 0V S R CE t 1 t 2 School of Systems Engineering - Electronic Engineering Slide 114

115 Single-Slope Slope ADC An integrator is used to integrate the reference voltage -vv ref thus generating a linear ramp of well-defined slope: v a 1 t t2 vref ( t2 t ref ref = RC t1 RC = v d t = [ v t ] RC t 1 ) The number stored in the counter at the end of conversion, B, is given by: B = f ) = c( t2 t1 v RCf v a ref c School of Systems Engineering - Electronic Engineering Slide 115

116 Dual-Slope ADC The accuracy of a dual-slope converter is independent of resistor or capacitor values or the clock frequency: -v ref v a h h h R h + - C h v b + - CE b 1.. b n Counter Clock b 0 School of Systems Engineering - Electronic Engineering Slide 116

117 Dual-Slope ADC Clock 0V v b v c CE t 1 t 3 b 0 t 2 School of Systems Engineering - Electronic Engineering Slide 117

118 Dual-Slope ADC As the counter is enabled (time t 1 ) the integrator voltage is zero Suppose that the voltage on the output of the integrator reaches v c as b 0 goes to 1 (time t 2 ): v c = RC t 1 1 C t1 2 v t t v t a( ad 2 = RC t ) where v a is the mean value of v a over the interval t 1 to t 2 School of Systems Engineering - Electronic Engineering Slide 118

119 Dual-Slope ADC During the period t n: 1 to t 2 the counter counts to 2 n 2 = f c ( t 2 t1) Combining with previous equation gives: v c = va2 f RC During the second part of the operation the integrator charges back from V c, reaching zero at time t 3 : c t 1 3 v t t v v t v ref ( 0 c ref d 3 = 2 c = RC t RC 2 n ) School of Systems Engineering - Electronic Engineering Slide 119

120 Dual-Slope ADC The counter value B (bits b 1..bb n ), which was zero at time t 2, will be given by: B = fc ( t 3 t2 ) Combining these equations: v c = vref B f RC Finally, eliminating V c : v a 2 B = v c ref n School of Systems Engineering - Electronic Engineering Slide 120

121 Dual-Slope ADC Example: Maxim MAX132 Number of bits: 18 Conversion time: 63 ms (16 sps) Integral non-linearity: ±4 lsb Gain error: ±40 lsb Offset error: ±20 lsb Power consumption (v s =5 V): 0.3 mw Digital interface: serial Analogue input multiplexing: no Cost: 5 School of Systems Engineering - Electronic Engineering Slide 121

122 Digital-to-Analogue to Conversion Analogue-to-Digital Conversion J. B. Grimbleby, 20 October 2008 School of Systems Engineering - Electronic Engineering Slide 122