Low Capacitance, +12 V / +5 V / +3 V, Triple SPDT (Triple 2:1) Analog Switch / Multiplexer

Transcription

1 Low apacitance, +12 V / +5 V / +3 V, Triple SPDT (Triple 2:1) nalog Switch / Multiplexer DESRIPTION The is a high precision triple SPDT (triple 2:1) analog switch / multiplexer with enhanced performance on low power consumption. The part features low parasitic capacitance, low leakage, and low charge injection over the full signal range which make it an ideal switch for healthcare, data acquisition, and instrument products. Its compact size, light weight, low power consumption, and low voltage control capability are of advantages in portable consumer applications such as goggles. The is designed to operate from a 3 V to 16 V supply at, and 2.5 V to 5.5 V at, while guarantees 1.8 V logic compatible over the full operation voltage range. Processed with advanced MOS technology, the conducts equally well in both directions, offers rail to rail analog signal handling and can be used both as a multiplexer as well as a de-multiplexer. The operating temperature is specified from -4 to It is available in ultra-compact 1.8 mm x 2.6 mm miniqfn16 package of lead (Pb)-free nickel-palladium-gold device termination. It is represented by the lead (Pb)-free -E4 suffix. The nickel-palladium-gold device terminations meet all JEDE standards for reflow and MSL ratings. FETURES Operates with = 3 V to 16 V, = 2.5 V to 5.5 V Guaranteed 1.8 V logic control at full range Low power consumption, both I+ and I L < 1 μ Low parasitic capacitance: D(ON) : 8.8 pf D(OFF) : 4 pf S(OFF) : 3.1 pf High bandwidth: 356 MHz Low charge injection over the full signal range ompact miniqfn16 package (1.8 mm x 2.6 mm x.55 mm) Material categorization: for definitions of compliance please see PPLITIONS Medical and healthcare systems Data acquisition systems Meters and instruments Games and Goggles utomatic test equipment Process control and automation ommunication systems attery powered systems FUNTIONL LOK DIGRM ND PIN ONFIGURTION Y mqfn-16 Y1 Y ENEFITS Low power consumption Precision switching Low voltage logic interface i-directional rail to rail signal switching ompact package option Extended operation temperature range Z X Yxx Z Z Enable X1 X Pin 1 Device Marking: Jxx for (miniqfn16) xx = Date/Lot Traceability ode VL Top View S Rev., 18-pr-16 1 Document Number: 67172

2 TRUTH TLE ENLE SELET INPUTS ON SWITHES INPUT H X X X ll Switches Open L L L L X to X, Y to Y, Z to Z L L L H X to X1, Y to Y, Z to Z L L H L X to X, Y to Y1, Z to Z L L H H X to X1, Y to Y1, Z to Z L H L L X to X, Y to Y, Z to Z1 L H L H X to X1, Y to Y, Z to Z1 L H H L X to X, Y to Y1, Z to Z1 L H H H X to X1, Y to Y1, Z to Z1 ORDERING INFORMTION TEMP. RNGE PKGE PRT NUMER MIN. ORDER / PK. QUNTITY -4 to +85 lead (Pb)-free 16-Pin miniqfn EN-T1-GE4 Tape and reel, 3 units SOLUTE MXIMUM RTINGS (T = 25, unless otherwise noted) PRMETER LIMIT UNIT Digital Inputs a -.3 to () +.3, V S, V D, or 3 m, whichever occurs first V to -.3 to +18 ontinuous urrent (any terminal) 3 Peak urrent, S or D (pulsed 1 ms, 1 % duty cycle) 1 m Storage Temperature -65 to +15 Power Dissipation b 16-Pin miniqfn c, d 525 mw Thermal Resistance b 16-Pin miniqfn d 152 /W Latch-Up (per JESD78) 1 m ESD Human ody Model (HM); per NSI / ESD / JEDE JS-1 25 V Notes a. Signals on SX, DX, or INX exceeding will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. ll leads welded or soldered to P board. c. Derate 6.6 mw/ above 7. d. Manual soldering with iron is not recommended for leadless components. The miniqfn-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S Rev., 18-pr-16 2 Document Number: 67172

3 SPEIFITIONS FOR UNIPOLR SUPPLIES PRMETER SYMOL TEST ONDITIONS UNLESS OTHERWISE SPEIFIED = 12 V, = 2.7 V V IN(,, and enable) = 1.8 V,.5 V a TEMP. b TYP. c -4 to to +85 MIN. d MX. d MIN. d MX. d nalog Switch nalog Signal Range e V NLOG Full V On-Resistance R ON I S = 1 m, V D =.7 V, 6 V, 11.3 V On-Resistance Match R ON I S = 1 m, V D =.7 V, 11.3 V On-Resistance Flatness R FLTNESS I S = 1 m, V D =.7 V, 6 V, 11.3 V Switch Off Leakage urrent hannel On Leakage urrent Digital ontrol Room Full Room Full Room Full I S(off) = 13.2 V, = 2.7 V Room Full ± I D(off) V D = 1 V / 12.2 V, V S = 12.2 V / 1 V Room ± Full I D(on) = 13.2 V, = 2.7 V V D = V S = 1 V / 12.2 V Room ± Full Logic Low Input Voltage V INL Full = 2.7 V Logic High Input Voltage V INH Full Logic Low Input urrent I L V IN(, 1, 2 and enable) under test =.5 V Full V Logic High Input current I IN(, 1, 2 and enable) H under test = 1.8 V Full Dynamic haracteristics Transition Time t TRNS Room Full Room Enable Turn-On Time t ON(EN) R L = 3, L = 35 pf Full Enable Turn-Off Time t OFF(EN) see Fig. 1, 2, 3 Room Full reak-efore-make Time Delay t D Room Full harge Injection e Q L = 1 nf, R GEN =, V GEN = V Full p 1 khz Room Off Isolation e OIRR 1 MHz Room f = 1 MHz, 1 MHz Room R L = 5, L = 5 pf 1 khz Room d rosstalk e X TLK 1 MHz Room MHz Room andwidth, -3 d e W R L = 5 Room MHz Source Off apacitance e S(off) Room Drain Off apacitance e D(off) f = 1 MHz Room hannel On apacitance e D(on) Room Total Harmonic Distortion e THD Signal = 1 V RMS, 2 Hz to 2 khz, R L = 6 UNIT Room % n V μ ns pf S Rev., 18-pr-16 3 Document Number: 67172

4 SPEIFITIONS FOR UNIPOLR SUPPLIES TEST ONDITIONS -4 to to +85 PRMETER SYMOL UNLESS OTHERWISE SPEIFIED TEMP. b TYP. c = 12 V, = 2.7 V MIN. d MX. d MIN. d MX. d UNIT V IN(,, and enable) = 1.8 V,.5 V a Power Supply Room Power Supply Range I+ Full V IN(,, and enable) = V or 12 V Room Ground urrent I μ Full Logic Supply urrent I L = 2.7 V Room Full Notes a. V IN = input voltage to perform proper function. b. Room = 25, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN ID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet. e. Guaranteed by design, not subject to production test. S Rev., 18-pr-16 4 Document Number: 67172

5 SPEIFITIONS FOR UNIPOLR SUPPLIES PRMETER SYMOL TEST ONDITIONS UNLESS OTHERWISE SPEIFIED = 5 V, = 2.7 V V IN(,, and enable) = 1.8 V,.5 V a TEMP. b TYP. c -4 to to +85 MIN. d MX. d MIN. d MX. d nalog Switch nalog Signal Range e V NLOG Full V On-Resistance R ON I S = 1 m, V D = V, 3.5 V On-Resistance Match R ON I S = 1 m, V D = 3.5 V On-Resistance Flatness R FLTNESS I S = 1 m, V D = V, 3 V Switch Off Leakage urrent hannel On Leakage urrent Digital ontrol Room Full Room Full Room Full I S(off) Room ± = 5.5 V, V- = V Full I D(off) V D = 1 V / 4.5 V, V S = 4.5 V / 1 V Room ± Full I D(on) = 5.5 V, V- = V V D = V S = 1 V / 4.5 V Room ± Full V IN(,, and enable) Low V IL = 2.7 V Full V IN(,, and enable) High V IH = 2.7 V Full Input urrent, V IN Low I L V IN(,, and enable) under test =.6 V Full Input urrent, V IN High I H V IN(,, and enable) under test = 1.8 V Full Dynamic haracteristics Transition Time t TRNS Room Full Room Enable Turn-On Time t ON R L = 3, L = 35 pf Full Enable Turn-Off Time t OFF see Fig. 1, 2, 3 Room Full reak-efore-make Time Delay t D Room Full harge Injection e Q V g = V, R g =, L = 1 nf Full p Off Isolation e OIRR Room R L = 5, L = 5 pf hannel-to-hannel f = 1 khz rosstalk e X TLK Room d Source Off apacitance e S(off) Room Drain Off apacitance e D(off) f = 1 MHz Room pf hannel On apacitance e D(on) Room Power Supply Room Power Supply urrent I+ Full V IN(,, and enable) = V or 5 V Room Ground urrent I μ Full Logic Supply urrent I L = 2.7 V Room Full Notes a. V IN = input voltage to perform proper function. b. Room = 25, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN ID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet. e. Guaranteed by design, not subject to production test. S Rev., 18-pr-16 5 Document Number: UNIT n V μ ns

6 SPEIFITIONS FOR UNIPOLR SUPPLIES PRMETER SYMOL TEST ONDITIONS UNLESS OTHERWISE SPEIFIED = 3 V, = 2.7 V TEMP. b TYP. c V IN(,, ND ENLE) = 1.5 V,.6 V a -4 to to +85 MIN. d MX. d MIN. d MX. d nalog Switch nalog Signal Range e V NLOG Full V On-Resistance R ON I S = 1 m, V D = 1.5 V Switch Off Leakage urrent hannel On Leakage urrent Digital ontrol Room Full I S(off) = 3.3 V, = 2.7 V Room Full ± I D(off) V D =.3 V / 3 V, V S = 3 V /.3 V Room ± Full I D(on) = 3.3 V, = 2.7 V V S = V D =.3 V / 3 V Room ± Full Logic Low Input Voltage V INL Full = 2.7 V Logic High Input Voltage V INH Full Logic Low Input urrent I L V IN(, 1, 2 and enable) under test =.6 V Full V Logic High Input urrent I IN(, 1, 2 and enable) H under test = 1.8 V Full Dynamic haracteristics Transition Time t TRNS Room Full Room Enable Turn-On Time t ON(EN) R L = 3, L = 35 pf Full Enable Turn-Off Time t OFF(EN) see Fig. 1, 2, 3 Room Full reak-efore-make Time Delay t D Room Full harge Injection e Q L = 1 nf, R GEN =, V GEN = V Full p Off Isolation e OIRR f = 1 MHz, R L = 5, 1 khz Room rosstalk e X TLK L = 5 pf 1 khz Room d Source Off apacitance e S(off) Room Drain Off apacitance e D(off) f = 1 MHz Room pf hannel On apacitance e D(on) Room Power Supply Room Power Supply Range I+ Full V IN (,, and enable) = V or 3 V Room Ground urrent I μ Full Logic Supply urrent I L = 2.7 V Room Full Notes a. V IN = input voltage to perform proper function. b. Room = 25, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN ID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet. e. Guaranteed by design, not subject to production test. UNIT n V μ ns S Rev., 18-pr-16 6 Document Number: 67172

7 TYPIL HRTERISTIS (25, unless otherwise noted) R ON -On-Resistance (Ω) = +3 V, V- = V = +5 V, V- = V = +12 V, V- = V T = 25 I S = -1 m = +16 V, V- = V R ON -On-Resistance (Ω) = +5 V v- = V I S = 1 m V D - nalog Voltage (V) On-Resistance vs. V D and Signal Supply Voltage V D - nalog Voltage (V) On-Resistance vs. nalog Voltage and Temperature R ON -On-Resistance (Ω) = +12 V v- = V I S = 1 m V D - nalog Voltage (V) On-Resistance vs. nalog Voltage and Temperature t ON(EN), t OFF(EN) - Switching Time (ns) 175 = +3 V, V- = V, t ON 15 = +5 V, V- = V, t ON 125 = +3 V, V- = V, t OFF 1 = +12 V, V- = V, t ON = +16 V, V- = V, t ON 75 5 = +5 V, V- = V, t OFF = +12 V, V- = V, t OFF 25 = +16 V, V- = V, t OFF Temperature ( ) Switching Time vs. Temperature 1n 1n = V V- = - V I D(ON), V D = 12.2 V -1-2 Loss Leakage urrent () 1n 1p 1p I D(OFF), V D = 12.2 V, V S = 1 V I S(OFF), V D = 12.2 V, V S = 1 V Loss, OIRR, X TLK (d) X TLK OIRR = 12 V = 2.7 V R L = 5 Ω -9 1p Temperature ( ) Leakage urrent vs. Temperature -1 1K 1M 1M 1M 1G Frequency (Hz) Insertion Loss, Off-Isolation, rosstalk vs. Frequency S Rev., 18-pr-16 7 Document Number: 67172

8 TYPIL HRTERISTIS (25, unless otherwise noted) V T - Switching Threshold (V) to +125 V IH = -4 V IL = Supply Voltage (V) Q INJ - harge Injection (p) = 12 V = 5 V = 3 V = 2.7 V V S - nalog Voltage (V) Switching Threshold vs. Logic Supply Voltage harge Injection vs. nalog Voltage 1m I L - Supply urrent (μ) 1m 1m 1n 1n 1n 1p = 12V = 2.7 V T = 25 1p 1p V IN (V) I L vs. V IN SHEMTI DIGRM (typical channel), X, Y, Z V- V- Level shift Decode/ drive ody snatcher V- X, Y, Z EN V- V- X1, Y1, Z1 S Rev., 18-pr-16 8 Document Number: 67172

9 TEST IRUITS V,, 1.8 V V 5 % 5 Ω or or ENLE X or Y or Z X1 or Y1 or Z1 X or Y or Z V X or V Y or V Z V X1 or V Y1 or V Z1 3 Ω 35 pf V X or V Y or V Z V X7 V X3 or V Y3 V X1 or V Y1 or V Z1 t TRNS 5 % 9 % 9 % ttrns V or Y or Z ON X1 or Y1 or Z1 ON (DG9454) Fig. 1 - Transition Time 1.8 V or or X or Y or Z X1 or Y1 or Z1 V ENLE V V X or V Y or V Z 5 % 5 % 9 % ENLE X or Y or Z 5 Ω 3 Ω 35 pf V t OFF Enable X or Y or Z 9 % Disable X or Y or Z t ON Fig. 2 - Enable Switching Time 1.8 V 5 Ω or or X, X1 or Y, Y1 or Z, Z1 V,, V V X or V Y or V Z 5 % 8 % ENLE X or Y or Z 3 Ω 35 pf V t D Fig. 3 - reak-efore-make S Rev., 18-pr-16 9 Document Number: 67172

10 TEST IRUITS hannel Select R g Xx V ENLE V OFF ON t r < 5 ns t f < 5 ns OFF V g ENLE X Δ 1 nf Fig. 4 - harge Injection Network nalyzer Network nalyzer X V IN V g R g = 5 Ω X V IN V g R g = 5 Ω ENLE X UT ENLE X UT 5 Ω 5 Ω Insertion Loss = 2 log UT V IN Fig. 5 - Insertion Loss Off Isolation = 2 log UT V IN Fig. 7 - Off Isolation Network nalyzer X 5 Ω ENLE Xx X V IN UT V g 5 Ω R g = 5 Ω hannel Select ENLE X to Xx X Impedance nalyzer rosstalk = 2 log VOUT V IN Fig. 6 - rosstalk Fig. 8 - Source, Drain apacitance maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see S Rev., 18-pr-16 1 Document Number: 67172

11 Thin miniqfn16 ase Outline Package Information D Terminal tip (4) 16 x b.1.5 M M E L Pin #1 identifier (5) 15 x L e Top view ottom view Seating plane Side view DIMENSIONS MILLIMETERS (1) INHES MIN. NOM. MX. MIN. NOM. MX ref..6 ref. b D e.4 S.16 S E L L N (3) Nd (3) 4 4 Ne (3) 4 4 Notes (1) Use millimeters as the primary measurement. (2) Dimensioning and tolerances conform to SME Y14.5M (3) N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively. (4) Dimensions b applies to plated terminal and is measured between.15 mm and.3 mm from terminal tip. (5) The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. (6) Package warpage max..5 mm. EN: T Rev., 9-May-16 DWG: 623 Revision: 9-May-16 1 Document Number: 64694

12 PD Pattern REOMMENDED MINIMUM PDS FOR MINI QFN 16L.562 (.221).4 (.157) (.89) 2.9 (.1142).463 (.182) 1.2 (.472) 2.1 (.827) Mounting Footprint Dimensions in mm (inch) Document Number: Revision: 5-Mar-1 1

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