Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

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Hollie Cummings
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1 Serial :. ND_NW_EC_Analog Electronics_658 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph: CLASS TEST 8-9 ELECTONICS ENGINEEING Subject : Analog Electronics Date of test : 6/5/8 Answer Key. (c) 7. (a) 3. (c) 9. (a) 5. (d). (d) 8. (c) 4. (c). (c) 6. (b) 3. (a) 9. (d) 5. (a). (a) 7. (d) 4. (d). (c) 6. (b). (c) 8. (c) 5. (a). (c) 7. (b) 3. (c) 9. (b) 6. (b). (d) 8. (d) 4. (d) 3. (c)

2 CT-8 EC Analog Electronics 9 Detailed Explanations. (c) The maximum efficiency of the class A amplifier can be reached by using a transformer coupled load. It can approximately reach to 5%.. (d) k k k 99 k Set, then F 99k where ( ) 99k k so, Now, set 9 k k k 99 k then hence 9 A 9, A

3 Electronics Engineering 3. (a) 5 9 I L(max) z(min) k i.6.6 ma 4. (d) When the cathode voltage of two parallel diodes is same, the diode with more forward biasing anode voltage will be in ON state and the other diode will be in OFF state. Hence D will be in OFF state and D will be in ON state. Thus I.3.3 ma kω 5. (a) The feedback element ( F ) is directly connected to both input and output. So, voltage-shunt type of feedback. 6. (b) Since there is a D.C level shift in the output waveform, the circuit must be a clamper circuit and when the diode is conducting, the voltage at the output must be 5 as seen from the output waveform hence option (b) is correct. 7. (a) From the circuit it is clear that D will always be off. Thus.7 kω kω kω (.7) kω kω 8. (c) dt C i t 3 5 C 5 i t C.5 mf

4 CT-8 EC Analog Electronics 9. (d) For the Hartly oscillator shown, L A L A L or 4 L 48 L L 48 µh L max 48 µh to produce sustained oscillations. (c) Maximum power dissipation P Dmax Tjmax TA θ W (θ Thermal resistance) CE max P D max max A 4. (c) kω kω 3 5 kω kω v 3 5 kω kω v C. µ F. µ F C. µ F. µ F figure-i figure-ii alue of A corresponding to figure-i is kω and value of B is 5 kω. alue of A corresponding to figure-ii is 5kΩ and value of B is kω. So, kω A 5 kω kω B 5 kω f max f max.693 C ( ) A B ( ) f max.7 khz

5 Electronics Engineering. (d) Assume that the gain is very large i.e. A v >> thus A v for unbypassed E and for large values of E g m E >> thus, the voltage gain of above circuit will become βc gmc re βc A v gm β E r β r 3. (c) now, since β is very large thus, C A v A v k Ω kω 5 E E e E e 4 k 5 Ω.5 5 Ω.5 b i b 5 Ω 5 Ω 5 Ω 5 Ω b 3 i b 4.3k and i b for b k b and for b egulation.39 egulation 4.545% %

6 CT-8 EC Analog Electronics 3 4. (c) Maximum power dissipation P Dmax Tjmax TA θ W (θ Thermal resistance) CE max P D max max A 4 5. (a) Base emitter loop.5 kω 5 kω I B IE kω in 5 ki B.7 k (I B ) I B I E I B from here I B 8.88 µa r π T T 6 β k Ω.383 k Ω I I 8.8 C B in r π ( β) E.383k k.383 kω 6. (b) Small signal circuit is i G g m gs D 7 kω gs g m gs D gs i i g m D W g m µ ncox I D.5.44 m L A v i g m D

7 4 Electronics Engineering 7. (b) For ve half cycle ωt π I AB sinωt k I AB sinωt D kω I AB sinωt ma For ve half cycle π ωt π I AB sinωt k I AB sinωt kω kω I AB sinωt ma form here I AB sinωt ma for all ωt AB I AB AB sinωt kω 3 sinω t 8. (d) (6 ma)(6 kω) 36 I 6 ma K I 6 ma ma 4 ma I 9. (a) D γ eq kω i eq 3 eq volts.

8 CT-8 EC Analog Electronics 5 eq 6 3 kω. 9 i ; as i > eq, D is ON and the voltage across the diode will be γ. γ i (c) 9 5 kω B I B.7 I B B.5 ma EC 4.7 kω E C I B 9 β 49(.5) ( I E) ma.49 ma β 5.5 ma µa 5 E I B B EB (.) (5).7. C EC P Q C 9 (.49)(4.7) (6.697 ) EC (.49)(7.897) mw 3.87 mw. (a) kω kω i kω kω kω i k Ω k Ω k k Ω Ω i ( ) i kω k Ω i i so, i i (sinωt cosωt) m i (sinωt) m and i (cosωt) m sin( ωt 45 ) m

9 6 Electronics Engineering. (c) For M to operate in saturation; dsi gs tn i i Also, I D kn( gs ) ( ) tn kn gs tn gs gs 5 i 5 i 5 i > i i 6 i 3 Thus, maximum input that can be applied is (c) At t, circuit is open, and no input is connected, hence c ( ) c ( ) At t C i i o o t dt C i i i t o o C t 4. (d) For S < ; Diode is ON, and the positive terminal of op-amp is forced to O. S For S > ; Diode is off and the positive terminal of op-amp now follows S since no current flows in resistor, so must follow S. S s

10 CT-8 EC Analog Electronics 7 5. (d) Let us assume M is in saturation I D W µ n Cox ( gs Th) (.36) µ A L.8 I D µa Now, D DD D I D.8 DS Assumption is correct when g. I D 6.7 D.766 Drain voltage changes by 34 m. 6. (b) Current through photodiode I (.8) () ma ma β 8.7 I E kω I I I o kω ref I 8 ma I E ( β ) IC 8.mA β 8 β BE.7 so, I kω.7 ma I I E I 8. (.7) ma 8.8 ma 7. (d) f.693( ) A B C (5) ( ) 5 5 khz 5.77 khz (c) 3 4 i i 4 i 4 i 8 i gain i 8

11 8 Electronics Engineering 9. (b) We obtain the operating point in following steps: Step : To determine the operating point we redraw the given circuit as shown below. 5 5 kω 5 kω Q TH.7 kω I B BE TH 3.57 loop CEQ I E.5 kω Loop TH.7 kω TH 3.57 I E CEQ.5 kω loop Step : The modified circuit parameters are kω, kω, Th k k.7kω Th Step 3: Applying KL in input loop, 3.57 I BQ Th BE (.5k) I EQ 5 [Put I EQ (β )I BQ ] I BQ Q.4 ma 4 µa 3. (c) As drain is connected to gate for both T and T, they will be in saturation mode of operation. ID ID K n (5 o ) K n ( o ) K n W So, K n K n W W ( o ) ( o ) ( ) 4 o ( o ) o 4.7

EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7

EE 140 / EE 240A ANALOG INTEGRATED CIRCUITS FALL 2015 C. Nguyen PROBLEM SET #7 Issued: Friday, Oct. 16, 2015 PROBLEM SET #7 Due (at 8 a.m.): Monday, Oct. 26, 2015, in the EE 140/240A HW box near 125 Cory. 1. A design error has resulted in a mismatch in the circuit of Fig. PS7-1.