Analog Electronics Laboratory

Transcription

1 Circuit Diagram a) Center tap FWR without filter b) Center tap FWR with C filter AC Supply AC Supply D2 c) Bridge Rectifier without filter d) Bridge Rectifier with C filter AC Supply AC Supply Waveforms Vi Vm π 2π ωt Vo without filter V m VDC π 2π ωt V O with C filter V m Vrpp VDC π 2π ωt Department of ECE, CIT, Gubbi Page no. 1

2 Experiment No: 1 Rectifiers with and without Filters Aim: To design and verify the performance of center tap full wave rectifier with and without C filter Date: rectifier and bridge Apparatus Required : Sl. No. Particulars Range Quantity 1. Transformer As per design Diode (BC 547) Resistors & Capacitors As per design - 4. Multimeter CRO Probes - 2 Set 6. Spring board and connecting wires - - Theory: Rectifier is a circuit which converts AC to pulsating DC. Rectifiers are used in construction of DC power supplies. There are three types of rectifiers namely Half wave rectifier, Center tap full wave rectifier and bridge rectifier. In half wave rectification, either the positive or negative half of the AC wave is passed, while the other half is blocked. Because only one half of the input waveform reaches the output, it is very inefficient if used for power transfer. A full-wave rectifier converts the whole of the input waveform to one of constant polarity (positive or negative) at its output. Full-wave rectification converts both polarities of the input waveform to DC (direct current), and is more efficient. Full wave rectification can be obtained either by using center tap transformer or by using bridge rectifier. The output of a rectifier is not a smooth DC it consists of ac ripples therefore to convert this pulsating DC in to smooth DC we use a circuit called filter. There are many types of filters like C filter, L filter, LC filter, multiple LC filter, π filter etc., of which C filter is the most fundamental filter. Applications: 1. Rectifier converts incoming AC to pulsating DC voltage which should be filtered and regulated to get pure DC voltage. All electronic devices require DC, so rectifiers are used inside the power supplies of all electronic equipments like television, laptops, refrigerators, etc., 2. Used for detection of amplitude modulated radio signals. Department of ECE, CIT, Gubbi Page no. 2

3 Note: Do not measure the input and output through two channels of CRO simultaneously for a bridge rectifier. Design: Center Tap Full Wave Rectifier / Bridge Rectifier Without filter V DC = 2V m / π for FWR (both center tap and bridge rectifier) For the given V DC calculate V m and V rms = V m / 2 Choose the transformer of rating V rms 0 V rms I DC for Center tap full wave rectifier and 0 V rms I DC for Bridge rectifier The value of load resistance, R L = V DC / I DC, P RL = V DC 2 / R L Full Wave Rectifier with C filter V DC = V m (I DC / 4fC) γ = 1 / (4 3 fcr L ) ( f = 50 Hz ) For the given value of VDC and IDC Calculate RL = V DC / I DC, P RL = V DC 2 / R L For the given γ Calculate the value of capacitor C For the given value of V DC and I DC, Calculate V m and V rms = Vm 2 Choose the transformer of rating, V rms 0 V rms I DC for Center tap full wave rectifier and 0 V rms I DC for Bridge rectifier Choose the capacitor of value C V m Example - 1: Design an FWR for an output DC voltage of 10 V and load current of V DC = 10 V 10 ma. (Bridge and Center tap rectifier) V m = (V DC X π) / 2 = 15.7 V V rms = V m / 2 = 11.1 V 12 V Choose a transformer of rating 12V 0 12V / 10 ma for Center tap full wave rectifier Choose a transformer of rating 0 12V / 10 ma for Bridge rectifier R L = V DC / I DC = 1 kω P RL = V DC 2 / R L = 0.1 W Choose R L = 1 kω / 0.1 W Department of ECE, CIT, Gubbi Page no. 3

4 Procedure: 1. Components / Equipment are tested for their good working condition 2. Connections are made as shown in the circuit diagram 3. Observe different waveforms on CRO 4. Measure V DC using multimeter in dc mode and V m on CRO 5. Calculate output V rms from V m using formula V rms = V m / 2 for Half wave rectifier V rms = V m / 2 for full wave rectifier 6. Calculate the efficiency, ripple factor and regulation. Compare the results with the theoretical values. Department of ECE, CIT, Gubbi Page no. 4

5 Example 2: Design a full wave rectifier for V DC = 16 V, I DC = 16mA, γ = (Bridge and center tap full wave rectifier) R L = V DC / I DC = 1 kω, P RL = V 2 DC / R L = 0256 W From γ = 1 / (4 3 fcr L ), C = 481 µf, ( 470µf) (f = 50 Hz ) From V DC = V m (I DC / 4fC), V m = V, V rms = V, ( 12 V) Choose transformer of rating 12V V / 16mA for center tap full wave rectifier and 0 12V / 16mA for bridge rectifier Choose R L = 1 kω / W, C = 470 µf / 16.17V Tabular Column: Without filter Circuit V DC V m V rms 2 2 η=v DC / V rms Center tap full wave rectifier Bridge Rectifier γ = (V rms 2 / V DC 2 )-1 Note : V rms = V m / 2 for Half wave rectifier V rms = V m / 2 for full wave rectifier With filter: Circuit Center tap full V DC full load V rpp V rrms V DC no load % Regulation γ = V rrms / V DC wave rectifier Bridge Rectifier Note: V rrms = V rpp / 2 3 % Regulation = (V DC no load V DC full load) / V DC full load Department of ECE, CIT, Gubbi Page no. 5

6 Result: Without filter: Type of rectifier γ - theoretical γ - practical η - theoretical η - practical Center tap full wave rectifier Bridge Rectifier % % With filter: Type of rectifier γ theoretical γ practical % Regulation Center tap full wave rectifier Bridge Rectifier Department of ECE, CIT, Gubbi Page no. 6

7 Circuit Diagram: Clipping circuits 1. To remove positive peak above V γ level A K V O 10 V p-p 1 khz V γ V i V i V γ V O V m π 2π ωt V γ π 2π ωt 2. To remove positive peak above some reference level (V R +V γ ) V O 10 V p-p 1 khz V R + V γ V i V i V R +V γ V O V m π 2π ωt V R +V γ π 2π ωt Department of ECE, CIT, Gubbi Page no. 7

8 Experiment No: 2 Part A: Clipping circuits Clipping and Clamping Circuits Date: Aim: To design and study the clipping circuits using diodes. Apparatus Required: Sl. No. Particulars Range Quantity 1. Diode ( 1N4007 / BC547 ) Resistor As per design - 3. Multimeter CRO Probes - 3 set 5. Spring Board and Connecting wires - - Theory: A clipper is a circuit that removes either positive or negative portion of a waveform. This kind of processing is useful for signal shaping, circuit protection and communications. The clippers are usually constructed by using diodes and resistors and sometimes to adjust the clipping level DC power supplies are also used. There are two types of clippers namely series clippers and shunt clippers. If the clipping element (diode) is in series with the source then we call it as series clippers and if the clipping device is in parallel with the source then we call such circuit as shunt clippers. Further based on the portion of a waveform clipped the clippers can be classified as positive clippers, negative clippers and two level clippers (combination clippers). Procedure: 1. Components / Equipment are tested for their good working condition. 2. Connections are made as shown in the circuit diagram 3. Apply a sine wave of amplitude greater than the designed clipping level with frequency 500 Hz. Observe the output wave form on the CRO 4. Observe the transfer characteristic curve on CRO by applying input waveform to channel X and output waveform to channel Y. 5. Measure the clipped voltage and compare with the designed value. Department of ECE, CIT, Gubbi Page no. 8

9 3. To remove negative peak above -V γ level V O 10 V p-p 1 khz -V γ V i V i V m -V γ π 2π ωt V O -V γ π 2π ωt 4. To remove negative peak above some reference level (-V R -V γ ) V O 10 V p-p 1 khz -V R -V γ V i V i V m π 2π ωt -V R -V γ V O π 2π ωt -V R -V γ Department of ECE, CIT, Gubbi Page no. 9

10 Applications: 1. Series clippers are employed as noise limiters in FM transmitters by clipping excessive noise peaks above a specified level. 2. Used in television receivers and transmitters. 3. Diode clipper can be used for the protection of different types of circuit against transients which may cause considerable damage. 4. They are employed for different wave generation such as trapezoidal, square or rectangular waves. Department of ECE, CIT, Gubbi Page no. 10

11 5. To remove positive peak above some reference level (V R1 +V γ ) and negative peak above some reference level (-V R2 -V γ ) V O V R1 +V γ 10 V p-p 1 khz Vo V i -V R2 -V γ Vi VR1+Vγ V m π 2π ωt -VR2-Vγ Vo VR1+Vγ -VR2-Vγ π 2π ωt Department of ECE, CIT, Gubbi Page no. 11

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13 Design: Example 1: Design a clipping circuit to pass the positive peak above the reference level 2V (Circuit 2) V R + V γ = 2V Assume the diode to be silicon make then V γ = 0.6 V Then V R = = 1.4 V Assume R r = 100 KΩ and R f = 10 Ω Then R = R r R f = 1 KΩ Example 2: Design a clipping circuit to remove positive peak above + 3 V negative peak above 4 V (Circuit 5) V R1 +V γ = + 3 V Assume the diode to be silicon make then V γ = 0.6 V V R1 = = 2.4 V -V R2 -V γ = - 4 V -V R2 = = V V R2 = 3.4 V Assume R r = 100 KΩ and R f = 10 Ω Then R = R r R f = 1 KΩ Similarly assume clipping level and design other circuits. Department of ECE, CIT, Gubbi Page no. 13

14 Result: Sl. Designed Circuit No. Clipping level 1. To remove positive peak above V γ level V γ = To remove positive peak above some 2. reference level (V R +V γ ) V R +V γ = 3. To remove negative peak above -V γ level -V γ = To remove negative peak above some 4. reference level (-V R -V γ ) -V R -V γ = To remove positive peak above some 5. reference level (V R1 +V γ ) and negative V R1 +V γ = peak above some reference level (-V R2 -V γ ) -V R2 -V γ = Observed Clipping level Department of ECE, CIT, Gubbi Page no. 14

15 Circuit Diagram: Clamping Circuits Positive Clampers: 1. Negative peak clamped to -V γ level V i V O V t -V γ V t 2. Negative peak clamped to positive reference level (V R -V γ ) V i V O V t V R -V γ V t 3. Negative peak clamped to negative reference level (-V R -V γ ) V i V O V t -V R -V γ V t Department of ECE, CIT, Gubbi Page no. 15

16 Part B: Clamping Circuits Aim: To design a clamping circuit for the given specification. Apparatus Required: Sl. No. Particulars Range Quantity 1. Diode ( 1N4007 / BC547 ) Resistors & Capacitors As per design - 3. CRO Probes - 3 set 4. Spring board and connecting wires Theory: Clamper is a circuit which adds DC level to an AC waveform. There are two types of clampers namely positive clampers and negative clampers. In positive clampers positive DC level will be added to the AC waveform or the negative peak will be clamped to some other level. In Negative peak clampers negative DC level will be added to the AC waveform or the positive peak will be clamped to some other level. Clampers are very much used in communication systems for example clampers are used in analog television receivers for the purpose of restoring the dc component of the video signal prior to its being fed to the picture tube. Procedure: 1. Components / Equipment are tested for their good working condition. 2. Connections are made as shown in the circuit diagram 3. Apply a square wave / triangular wave / sine wave input of amplitude 10 V peak to peak and frequency of 1 khz 4. Observe the input and output waveform keeping CRO in DC position 5. Measure the clamping level and compare with the designed value Applications: 1. Clamping circuits are often used in television receivers as dc restorers. 2. Clamping can be used to adapt an input signal to a device that cannot make use of or may be damaged by the signal range of the original input. Department of ECE, CIT, Gubbi Page no. 16

17 Negative Clampers: 4. Positive peak clamped to V γ level V i V O V γ V t V t 5. Positive peak clamped to positive reference level (V R +V γ ) V i V O V R +V γ V t V t 6. Positive peak clamped to negative reference level (-V R +V γ ) Vi V O -VR+Vγ R γ V V t t Department of ECE, CIT, Gubbi Page no. 17

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19 Design: Example 1: Design a clamping circuit to clamp the negative peak to +3V ( Circuit 2 ) V R - V γ = 3 V Let the diode be silicon make then V γ = 0.6 V Then V R = = 3.6 V For a clamper RC >> T let RC = 10 T Assume f = 1 khz, hence T = 1 ms, choose C = 1 µ f Then R = 10 KΩ Example 2: Design a clamping circuit to clamp the positive peak to -2V ( Circuit 6 ) -V R +V γ = - 2V Let the diode be silicon make then V γ = 0.6 V -V R = V R = V V R = 2.6 V For a clamper RC >> T, let RC = 10 T Assume f = 1 khz, hence T = 1 ms, choose C = 1 µ f Then R = 10 kω Similarly design for other circuits. Department of ECE, CIT, Gubbi Page no. 19

20 Result: A. Positive Clampers Sl. Designed Circuit No. Clamping level 1. Negative peak clamped to -V γ level - V γ = 2. Negative peak clamped to positive reference level (V R -V γ ) V R -V γ = 3. Negative peak clamped to negative reference level (-V R -V γ ) -V R -V γ = Observed Clamping level B. Negative Clampers 4. Positive peak clamped to V γ level V γ = Positive peak clamped to positive reference level (V R +V γ ) Positive peak clamped to negative reference level (-V R +V γ ) V R +V γ = -V R +V γ = Department of ECE, CIT, Gubbi Page no. 20

21 Circuit Diagram: Zener Voltage Regulator Ideal Graph Line Regulation Vo (volts) Vi Vo Load Regulation 10 V Vo (volts) Vi (volts) VNL VFL 500 ma IL (ma) Department of ECE, CIT, Gubbi Page no. 21

22 Experiment No: 3 Date: Zener Voltage Regulator Aim: To plot line and load regulation characteristics using Zener diode and find percentage regulation. Apparatus required: SL NO Particulars Range Quantity Theory: 1 Zener diode Resistor 100Ω,800 Ω 2 3 Ammeter 0-20/200mA 1 4 Digital multimeter Power supply 0-30V 1 The Zener diode is like a general-purpose signal diode. When biased in the forward direction it behaves just like a normal signal diode, but when a reverse voltage is applied to it, the voltage remains constant for a wide range of currents. The function of a regulator is to provide a constant output voltage to a load connected in parallel with it in spite of the ripples in the supply voltage or the variation in the load current and the zener diode will continue to regulate the voltage until the diodes current falls below the minimum I Z(min) value in the reverse breakdown region. It permits current to flow in the forward direction as normal, but will also allow it to flow in the reverse direction when the voltage is above a certain value - the breakdown voltage known as the Zener voltage. The Zener diode specially made to have a reverse voltage breakdown at a specific voltage. Its characteristics are otherwise very similar to common diodes. The purpose of a voltage regulator is to maintain a constant voltage across a load regardless of variations in the applied input voltage and variations in the load current. The main application Zener diodes are as voltage regulator. Overvoltage protection is done by using Zener diodes because there is current flowing through the diode after the reverse bias voltage exceeds a certain value. Department of ECE, CIT, Gubbi Page no. 22

23 Tabular column Line Regulation RL= Ω Load Regulation Vin= V Sl.No Vi (volts) Vo (volts) Sl. No IL(mA) Vo (volts) Design Maximum Ranges: V CB =100V, V CE =60V, V BE =7V, I C max =15A, P=115W Nominal Ratings: V CE =4V, I C =4A, h FE =20 to 70. Selection of Zener diode: We know that Vo =8.5V, V z =Vo+0.6V=9.1V. Select (SZ9.1) zener diode. Design of Load resistance: R L =Vo/I L =8.5V/500mA=17Ω The power rating of resistor=i 2 R L = (0.5) 2 17=4.25W Use 17 Ω, 5W resistor or 800 Ω, 1A rheostat (DRB). I B = I L /20=500mA/20=25mA. Current through the series resistor R B =I Z +I B =35mA since the current through the zener diode IZ to keep it in the breakdown region is 10mA. Design of R B : R B should be selected considering Vi max and Vi min R B max = (Vimax-V Z ) / (I Z +I B ) =311 Ω R B min = (Vimin-V Z ) / (I Z +I B ) =26Ω, Select R B =100 Ω, Vi max=20v and Vi min=10v. Department of ECE, CIT, Gubbi Page no. 23

24 Procedure: 1. Connections are made as shown in the circuit diagram To find Line Regulation: 2. RL is kept constant and the unregulated input is varied in steps and at each step, the corresponding regulated output is measured. All the readings are tabulated and the graph Vin versus Vout is plotted to obtain the line Regulation. Percentage line regulation=( ( V0/ Vin) * 100) To find Load regulation: 3. Vin kept constant (at a value adequately more than the designed value of Vout) and the load resistance RL is varied (decreased)in steps and at each step, the regulated output Vout is measured against the load current IL. 4. All the readings are tabulated and graph of IL versus Vout is plotted to obtain the load regulation characteristics. 5. Measure no load voltage VNL by removing load resistor. 6. Measure full load voltage VFL by connecting load resistor and calculate % Load Result: regulation using formula VR= ((VNL-VFL)/VNL) 100%. Percentage load regulation= %. Percentage line regulation= %. Department of ECE, CIT, Gubbi Page no. 24

25 Circuit Diagram: Without boot strapping C E B C 2N3055 Design: Given VCC = 5 V, IE2 = 3mA, β1 = β2 = 60 Assume VCE = 50% VCC =5 / 2 = 2.5V VE = IE RE = VCC - VCE = 2.5V RE = 2.5 / IE, R E = 833ohms, Choose R E = 1 kω I B2 = I E2 / ( 1 + β2 ) = 49 µa I B1 = I E1 / ( 1 + β1 ) = I B2 / ( 1 + β1 ) = 0.8 µa RB = ( Vcc - V BE1 - V BE2 - V E ) / I B1 RB = 1.62 MΩ, Choose RB = 1.6 MΩ Assume C C1 = C C2 = 0.1 µf Department of ECE, CIT, Gubbi Page no. 25

26 Experiment No: 4 Date: Darlington Emitter Follower Aim: To conduct an experiment to plot the frequency response of a Darlington emitter follower amplifier with and without bootstrapping and to find the input impedance, output impedance and the voltage gain. Apparatus Required: Sl. No. Particulars Range Quantity 1. Transistor SL 100 and 2N each 2. Resistors & Capacitors As per design - 3. Multi meter CRO probes - 3 set 5. DRB Spring board and connecting wires - - Theory: When high input impedance and low output impedance requirements are to be met the natural choice is common collector configuration the common collector configuration of transistor has high input impedance, low output impedance and high current gain although no phase inversion. The common collector transistor amplifies is termed as emitter follower for the simple reason that the o/p voltage follows the input voltage ( A V 1 ). The important application of emitter follower is as buffer amplifier for impedance matching. A single stage emitter follower provides an input impedance of 500 kω. But for the requirement of i/p impedance beyond 500 kω we employ Darlington emitter follower. The voltage gain of Darlington Emitter Follower is less than but very nearly equal to unity. The coupling of the two stages of emitter follower amplifier, this cascaded connection of two emitter follower is called Darlington connections. In this connection, since two stages of transistor are connected it improves the current gain and input resistance of the circuit. In Darlington connections of two transistor emitter of the first transistor is directly connected to the base of the second transistor. The leakage current of the first transistor is amplified by the second transistor and overall leakage current may be high which is not desired. For further high i/p impedance requirement bootstrapping can be employed. Bootstrap circuit is an arrangement of components used to boost the input impedance of a circuit by using a small amount of positive feedback, usually over two stages. Department of ECE, CIT, Gubbi Page no. 26

27 Circuit Diagram: With boot strapping Circuit to find input impedance ( Zi ) : Circuit to find output impedance ( Zo ) : Department of ECE, CIT, Gubbi Page no. 27

28 Procedure: (With and without bootstrapping) 1. Check all the components and equipments for their good working condition. 2. Connections are made as shown in the circuit diagram. 3. By keeping the voltage knobs in minimum position and current knob in maximum position switch on the power supply. 4. By disconnecting the AC source measure the quiescent point (VEC2 and IE2 = VRE / RE) To find frequency response: 1. Connect the AC source. Keeping the frequency of the Ac source in mid band region (say 10 khz) adjust the amplitude to get the distortion less output. Note down the amplitude of the input signal. 2. Keeping the input amplitude constant, Vary the frequency in suitable steps and note down the corresponding output amplitude. 3. Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in db. From the graph calculate f L, f H and band width. 4. Calculate figure of merit. To find the input impedance ( Zi ) : 1. Connections are made as shown in the diagram. 2. Keeping the DRB in its minimum position, apply input signal at mid band frequency (say 10 khz) and adjust the amplitude of the input signal to get distortion less output. Note down the output amplitude. 3. Vary the DRB until the output amplitude becomes half of its previous value. The corresponding DRB value gives the input impedance. To find the output impedance ( Zo ) : 1. Connections are made as shown in the diagram. 2. Keeping the DRB in its maximum position, apply input signal at mid band frequency (say 10 khz) and adjust the amplitude of the input signal to get distortion less output. Note down the output amplitude. 3. Vary the DRB until the output amplitude becomes half of its previous value. The corresponding DRB value gives the output impedance. Department of ECE, CIT, Gubbi Page no. 28

29 Tabular Column: V i = V F in Hz Vo in Volt A V = Vo / Vi Gain in db = 20*log A V Ideal Graph: Gain in db f L f H f in Hz 3dB Band Width f L = Lower cutoff frequency f H = Higher cutoff frequency Department of ECE, CIT, Gubbi Page no. 29

30 Applications: 1. Impedance matching. 2. LED and Display drivers: Darlington transistor arrays contained within IC packages are widely used for driving loads from standard logic families. 3. Audio power output stages: Sometimes audio amplifier power output stages may require significant levels of current gain to enable them to drive low impedance speakers. 4. The Darlington circuit configuration is ideal for use in linear power regulators. 5. End applications for Darlington transistor devices include inverter circuits, AC motor control, DC motor control circuits and emergency power supplies, etc., Result: Without bootstrapping 1. Quiescent point : V EC2 = V, I E = ma. 2. Voltage Gain ( A V ) = ( in mid band region ) 3. Bandwidth (BW) = HZ 4. figure of merit ( FM = A V * BW ) = Hz 5. Input impedance (Z i ) = Ω, Output Impedance (Zo) = Ω With bootstrapping 1. Input impedance (Z i ) = Ω Department of ECE, CIT, Gubbi Page no. 30

31 Circuit Diagram: RC coupled Single stage BJT amplifier without feedback C B E SL100 or CL100 Design: Given, V CE = 2.5 V and I C = 1 ma Assume β = 100 V CC = 2V CE = 2 X 2.5 = 5 V Let V RE = 10% V CC =0.5 V R E = V RE / ( I C + I B ) I B = I C / β = 1 ma / 100 = 10 µa R E = 0.5 / ( 1 m + 10 µ ) = 495 Ω Choose R E = 470 Ω Apply KVL to collector loop V CC I C R C V CE V E = 0 R C = ( V CC V CE V E ) / I C = ( ) / 1 m R C = 2 kω Choose R C = 1.8 kω Let I R1 = 10 I B = 10 X 10 µa = 100 µa V R2 = V BE + V E = = 1.1 V ( Since transistor is silicon make V BE = 0.6 V ) R 2 = V R2 / ( I R1 I B ) = 1.1 / ( 100 µa - 10 µa ) R 2 = 12.2 kω Choose R 2 = 13 kω R 1 = ( V CC V R2 ) / I R1 = ( ) / 100 µa R 1 = 39 KΩ Choose R 1 = 38 kω X CE < < R E ; X CE = R E / 10 Department of ECE, CIT, Gubbi Page no. 31

32 Experiment No: 5 Date : RC Coupled Single Stage BJT Amplifier Aim : To conduct an experiment to plot the frequency response of an RC coupled amplifier and to find the input impedance, output impedance and the voltage gain. Apparatus Required: Theory: Sl. No. Particulars Range Quantity 1. Transistor SL Resistors & Capacitors As per design - 3. CRO Probes - 3 Set 4. Multi meter DRB Spring board and connecting wires - - An amplifier is a circuit which increases the voltage, current or power level of i/p signal where the frequency is maintained constant from o/p to i/p signal. The common emitter amplifier is basically a current amplifier ( I C = β I B ) where I B is input current and IC is output current and β is a non unity value, in turn it provides voltage amplification. The ratio of collector current to base current is noted as the current amplification factor and is denoted as β i.e.[β = I C /I B ], β is very large. In RC coupled CE amplifier R 1, R 2 and R C are selected in such a way that transistor operates in active region and the operating point will be in the middle of active region. R E is used for stabilization of operating point. Coupling capacitors C C1 and C C2 are used to block dc current flow through load and the source. The emitter by-pass capacitor C E is connected to avoid negative feedback. Input signal increases base current and the collector current increases by a factor β. [i.e., I c = βi b ]. Hence output voltage is large compared to input voltage which is known as amplification. An amplifier in which resistance-capacitance coupling is employed between stages and at the input and an output point of the circuit is known as RC coupled amplifier. A capacitor provides a path for signal currents between stages, with resistors connected from each side of the capacitor to the power supply or to ground. Applications: 1. Common-emitter amplifiers are used in radio frequency circuits, for example to amplify faint signals received by an antenna. Department of ECE, CIT, Gubbi Page no. 32

33 1 / ( 2 π f C E ) = 470 / 10 Let f = 100 Hz C E = 33 µf Choose C E = 47 µf Choose C C1 = C C2 = 0.1 µf Tabular Column: V i = V F in Hz Without Feedback Vo in Volt A V = Vo / V i Gain in db = 20*log A V With Feedback Vo in Volt A Vf = Vo / V i Gain in db = 20*log A Vf Department of ECE, CIT, Gubbi Page no. 33

34 Procedure: 1. Components / Equipment are tested for their good working condition. 2. Connections are made as shown in the circuit diagram. 3. By keeping the voltage knobs in minimum position and current knob in maximum position switch on the power supply. 4. By disconnecting the AC source measure the quiescent point (VCE and IC = V RC / R C ) To find frequency response: 1. Connect the AC source. Keeping the frequency of the AC source in mid band region (say 10 khz) adjust the amplitude to get the distortion less output. Note down the amplitude of the input signal. 2. Keeping the input amplitude constant, vary the frequency in suitable steps and note down the corresponding output amplitude. 3. Calculate A V and gain in decibels. Plot a graph of frequency Vs gain in db. From the graph calculate f L, f H and band width. 4. Calculate figure of merit (gain-bandwidth product). Department of ECE, CIT, Gubbi Page no. 34

35 Ideal Graph Gain db 3dB Band width f in Hz f L f L = Lower cutoff frequency f H f H = Higher cutoff frequency Department of ECE, CIT, Gubbi Page no. 35

36 Result: 1. Quiescent point : V CE = V, I C = ma 2. Voltage Gain ( A V ) = ( in mid band region ) 3. Bandwidth (BW) = Hz 4. Figure of merit ( FM = A V * BW ) = Hz Department of ECE, CIT, Gubbi Page no. 36

37 Circuit Diagram: Drain and Transfer Characteristics of JFET Ideal Graph Transfer characteristics ID(mA) Drain Characteristics V DS2 VDS ID V GS2 V DS2 > V DS1 V DS1 V GS1 V GS ID V GS2 > V GS1 Constant resistance region V T V GS (V) V DS (V) Department of ECE, CIT, Gubbi Page no. 37

38 Experiment No: 6 Date : Drain and Transfer Characteristics of JFET Aim: To plot drain and Transfer characteristics of JFET Apparatus required: Theory: Sl no Particulars Range Quantity 1 JFET BFW Ammeter 0-20/200 1 ma 3 Resistor 1KΩ 2 4 Power supply 0-30V 2 5 Digital multimeter - 1 The junction gate field-effect transistor (JFET or JUGFET) is the simplest type of field-effect transistor. They are three-terminal semiconductor devices that can be used as electronically-controlled switches, amplifiers, or voltage-controlled resistors. Unlike bipolar transistors, JFETs are exclusively voltage-controlled in that they do not need a biasing current. Electric charge flows through a semiconducting channel between source and drain terminals. By applying a reverse bias voltage to a gate terminal, the channel is "pinched", so that the electric current is impeded or switched off completely. A JFET is usually on when there is no potential difference between its gate and source terminals. If a potential difference of the proper polarity is applied between its gate and source terminals, the JFET will be more resistive to current flow, which means less current would flow in the channel between the source and drain terminals. Thus, JFETs are sometimes referred to as depletion-mode devices. JFETs can have an n-type or p-type channel. In the n-type, if the voltage applied to the gate is less than that applied to the source, the current will be reduced (similarly in the p- type, if the voltage applied to the gate is greater than that applied to the source). A JFET has a large input impedance (sometimes on the order of ohms), which means that it has a negligible effect on external components or circuits connected to its gate. Department of ECE, CIT, Gubbi Page no. 38

39 Tabular Column Drain Characteristics Transfer Characteristics At V GS = V At V GS = V At V DS = V At V DS = V V DS (V) I D (ma) V DS (V) I D (ma) V GS (V) I D (ma) V GS (V) I D (ma) Procedure: Department of ECE, CIT, Gubbi Page no. 39

40 1. Check the components for their working condition. 2. Connect the components as shown in the circuit diagram. To plot drain characteristics: 3. Keep the voltage V GS at constant value (say 0 V) by varying V DS supply. 4. Vary the voltage V GS by varying V DS in steps of 0.5 V and note down I D. 5. Repeat the same procedure for different values of V GS. 6. Plot the graph V DS v/s I D. To plot Transfer characteristics: 1. Keep the voltage V DS at constant value (say 2 V) by varying V DD supply. 2. Vary the voltage V GS in increments of 1 V and note down I D. 3. Repeat the same procedure for different values of V DS. 4. Plot the graph V GS v/s I D. Calculations: 1. Transconductance g m = I D / V GS = mho 2. Drain Resistance r d = V DS / I D = Ω 3. Amplification factor µ=g m r d =. Results: 1. The transconductance g m = mho 2. The drain resistance r d = Ω 3. The amplification factor µ=. Department of ECE, CIT, Gubbi Page no. 40

41 Circuit Diagram: RC Coupled Single Stage FET Amplifier G D Substrate S BFW 10 Design Given V DD = 10 V, V GS (off) = -4 V I DSS (max) = 12 ma R G = 2 MΩ Formulae I D = I DSS.(1 V GS / V GS (off)) (1) When V G = 0, Then V S = -V GS But V S = I D. R S When V G = 0, I D = I DSS V S = I DSS.R S I DSS.R S = -V GS (off) R S = -(-4) / 12mA = 333 Ω Choose R S = 330 Ω From (1) I D = I DSS.(1 I D.R S / V GS (off)) 2 I D = I DSS.(1 + I 2 2 D.R S / 16 - I D.R S /2) I D = 12 x 10-3 x (1 + I 2 D / 16 - I D.330 /2) I 2 D I D +12 x 10-3 = 0 I D = 4.6 ma or I D = 31.9 ma Since I D cannot be greater than I DSS, Choose I D = 4.6 ma Assume V DS = 50 % V DD ---- V DS = 5V Applying KVL to output circuit V DD = I D. R D + V DS + I D.R S Department of ECE, CIT, Gubbi Page no. 41

42 Experiment No: 7 RC Coupled Single Stage FET Amplifier Date: Aim: To conduct an experiment to plot the frequency response of an RC coupled amplifier and to find the input impedance, output impedance and the voltage gain. Apparatus Required: Sl. No. Particulars Range Quantity 1. FET BFW Resistors & Capacitors As per design - 3. CRO Probes - 3 Set 4. Multi meter DRB Spring board and connecting wires - - Theory: An amplifier is a circuit which increases the voltage, current or power level of i/p signal where the frequency is maintained constant from o/p to i/p signal. In FET amplifier the output current ( I D ) is a function of input voltage V GS. That is as V GS varies the drain current varies. V GS varies as input signal varies in turn the drain current varies hence amplification takes place. In R C coupled FET amplifier R D and R S are selected in such a way that FET operates in active region and the operating point will be in the middle of active region. Coupling capacitors C C1 and C C2 are used to block dc current flow through load and the source. The source by-pass capacitor C S is connected to avoid negative feedback. An amplifier in which resistance-capacitance coupling is employed between stages and at the input and output point of the circuit is known as RC coupled amplifier. A capacitor provides a path for signal currents between stages, with resistors connected from each side of the capacitor to the power supply or to ground. Procedure: 1. Components / Equipment are tested for their good working condition. 2. Connections are made as shown in the circuit diagram. 3. By keeping the voltage knobs in minimum position and current knob in maximum position switch on the power supply. 4. By disconnecting the AC source measure the quiescent point (VDS and ID = VRD / RD) Applications: 1. FET amplifiers are low noise amplifiers used for front-end applications. 2. They are used in Oscillators. 3. These are faster and are less noisy compared to BJT amplifiers. Department of ECE, CIT, Gubbi Page no. 42

43 R D = ( x 10-3 x 330) / 4.6 x 10-3 R D = 756 Ω Choose R D = 820 Ω X CS < < R S X CS = R S / 10 1 / ( 2 π f C S ) = 470 / 10 Let f = 100 Hz C S = 33 µf Choose C S = 47 µf Choose C C1 = C C2 = 0.1 µf Tabular Column : V i = V f in Hz V o in Volt A V = V o / V i Gain in db = 20*log A V Department of ECE, CIT, Gubbi Page no. 43

44 To find frequency response: 5. Connect the AC source. Keeping the frequency of the AC source in mid band region (say 10 khz) adjust the amplitude to get the distortion less output. Note down the amplitude of the input signal. 6. Keeping the input amplitude constant, Vary the frequency in suitable steps and note down the corresponding output amplitude. 7. Calculate AV and gain in decibels. Plot a graph of frequency Vs gain in db. From the graph calculate f L, f H and band width. 8. Calculate figure of merit. Department of ECE, CIT, Gubbi Page no. 44

45 Ideal Graph Gain db 3dB Band width f in Hz f L f L = Lower cutoff frequency f H f H = Higher cutoff frequency Department of ECE, CIT, Gubbi Page no. 45

46 Result: 1. Quiescent point : V DS = V, I D = ma, VGS = V 2. Voltage Gain ( A V ) = ( in mid band region ) 3. Bandwidth (BW) = Hz 4. Figure of merit ( FM = A V * BW ) = Hz Department of ECE, CIT, Gubbi Page no. 46

47 Circuit diagram: Drain and Transfer Characteristics of MOSFET Ideal Graph: Transfer Characteristics: Drain Characteristics ID(mA) ID(mA) Constant current region V DS2 VDS ID V GS2 V DS1 V GS1 V DS2 > V DS1 ID V GS2 > V GS1 V GS Constant resistance region V T V GS (V) V DS (V) Department of ECE, CIT, Gubbi Page no. 47

48 Experiment No: 8 Date: Drain and Transfer Characteristics of MOSFET Aim : To conduct an experiment to study and plot the transfer characteristics, drain characteristics of a MOSFET, and to find the transconductance and drain resistance. Apparatus Required: Theory: Sl. No. Particulars Range Quantity 1. MOSFET (IRF 540) Milliammeter 0-20/200mA 1 3. Multimeter - 1 The metal oxide semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, [1] the body (or substrate) of the MOSFET is often connected to the source terminal, making it a three-terminal device like other field-effect transistors. Because these two terminals are normally connected to each other (short-circuited) internally, only three terminals appear in electrical diagrams. The MOSFET is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common. The main advantage of a MOSFET over a regular transistor is that it requires very little current to turn on (less than 1mA), while delivering a much higher current to a load (10 to 50A or more). Procedure: Transfer Characteristics: 1. Check the components / Equipment for their working condition. 2. Connections are made as shown in the circuit diagram Initially both RPS-1 and RPS-2 are kept at zero output position. 4. By varying the RPS-2, set V DS around 3V 5. Now increase V GS by varying the RPS-1 gradually and note down the corresponding drain current. 6. Repeat the steps 4 and 5 for some other V DS value 7. Draw the graph between V GS and I D Department of ECE, CIT, Gubbi Page no. 48

49 Tabular Column: Transfer Characteristics V DS1 = V V DS2 = V V GS in Volt I D in ma V GS in Volt I D in ma Output/Drain Characteristics: V GS1 = V V GS2 = V V DS (V) I D (ma) V DS (V) I D (ma) Department of ECE, CIT, Gubbi Page no. 49

50 Output Characteristics: 1. Check the components / Equipment for their working condition. 2. Connections are made as shown in the circuit diagram Both RPS-1 and RPS-2 should be in zero output position and supply switch is ON 4. By varying RPS-1, set V GS to some value (slightly greater than the Threshold voltage determined from the transfer characteristics) 5. Now increase the V DS by varying the RPS-2 gradually and note down the corresponding drain current. 6. Repeat the steps 4 and 5 for some other V GS value. 7. Graph between V DS Vs I D is plotted Calculations: 1. Trans conductance g m = I D / V GS = mho 2. Drain Resistance r d = V DS / I D = Ω 3. Amplification factor µ=g m r d =. Results: The transconductance g m = mho The drain resistance r d = Ω The amplification factor µ=g m r d =. Department of ECE, CIT, Gubbi Page no. 50

51 Circuit Diagram: Class B Push Pull Power Amplifier C TR1 TR2 OC µf E B C 2N3055 / OC26 Vo t Cross over distortion Tabular Column: V i = V, V CC = V Sl. No. R L in Ω I c in ma V o in Volt P dc = V CC. I C P ac =V o 2 / 8R L % η=p ac / P DC Department of ECE, CIT, Gubbi Page no. 51

52 Experiment No: 9 Class B Push Pull Power Amplifier Date: Aim: To determine the efficiency of class B push pull amplifier and to find the optimum load. Apparatus Required: Sl. No. Particulars Range Quantity 1. Transistor AD149 and 2N each 2. Resistors as per design Milli ammeter 0-20 ma Multimeter CRO Probes - 3 Set 6. Spring Board and Connecting wires - - Theory: To improve the full power efficiency of the Class A type amplifier it is possible to design the amplifier circuit with two transistors in its output stage producing a "push-pull" type amplifier configuration. Push-pull operation uses two "complementary" transistors, one an NPN-type and the other a PNP-type with both power transistors receiving the same input signal together that is equal in magnitude, but in opposite phase to each other. This results in one transistor only amplifying one half or of the input waveform while the other transistor amplifies the other half or remaining of the waveform with the resulting "twohalves" being put back together at the output terminal. This pushing and pulling of the alternating half cycles by the transistors gives this type of circuit its name but they are more commonly known as Class B Amplifiers. The transistor base inputs are in "anti-phase" to each other as shown in circuit diagram, thus if TR1 base goes positive driving the transistor into heavy conduction, its collector current will increase but at the same time the base current of TR2 will go negative further into cut-off and the collector current of this transistor decreases by an equal amount and vice versa. Hence negative halves are amplified by one transistor and positive halves by the other transistor giving this push-pull effect. Unlike the DC condition, these AC currents are ADDITIVE resulting in the two output half-cycles being combined to reform the sinewave which then appears across the load. Class B Amplifiers have the advantage over Class A amplifier so that no current flows through the transistors when they are in their quiescent state (ie, with no input signal), therefore no power is dissipated in the output transistors when there is no signal present, unlike Class A amplifier stages that require significant --- Department of ECE, CIT, Gubbi Page no. 52

53 Ideal Graph % η η max Optimum load R L in Ω --- base bias thereby dissipating lots of heat - even with no input signal. So the overall conversion efficiency ( η ) of the amplifier is greater than that of the equivalent Class A with efficiencies reaching as high as 75% possible resulting in nearly all modern types of pushpull amplifiers operated in this Class B mode. While Class B amplifiers have a much high gain than the Class A types, one of the main disadvantages of class B type push-pull amplifiers is that they suffer from an effect known commonly as Crossover Distortion. This occurs during the transition when the transistors are switching over from one to the other as each transistor does not stop or start conducting exactly at the zero crossover point even if they are specially matched pairs. This is because the output transistors require a base-emitter voltage greater than 0.7v for the bipolar transistor to start conducting which results in both transistors being "OFF" at the same time. One way to eliminate this crossover distortion effect would be to bias both the transistors at a point slightly above their cut-off point. This is commonly called as Class AB Amplifier circuit. Department of ECE, CIT, Gubbi Page no. 53

54 Procedure: 1. Connections are made as shown in circuit diagram 2. Keep RL = 1KΩ, and adjust the amplitude of input signal for distortion less output waveform. 3. RL is varied in convenient steps and corresponding Vo and IC are recorded. 4. Calculate PDC and Pac and calculate efficiency 5. Plot a graph of %η versus RL and obtain the optimum load. Applications: 1. Class B operated amplifier is used extensively for audio amplifiers that require high power outputs. 2. It is also used as the driver and power amplifier stages of transmitters. Result: Maximum efficiency = %, Optimum load, R L opt = Ω Department of ECE, CIT, Gubbi Page no. 54

55 Circuit Diagram: RC Phase Shift Oscillator Vo T Design Given V DD = 10 V, V GS (off) = -4 V I DSS (max) = 12 ma R G = 2 MΩ Formulae I D = I DSS.(1 V GS / V GS (off)) (1) t When V G = 0, Then V S = -V GS But V S = I D. R S When V G = 0, I D = I DSS V S = I DSS.R S I DSS.R S = -V GS (off) R S = -(-4) / 12mA = 333 Ω Choose R S = 330 Ω From (1) I D = I DSS.(1 I D.R S / V GS (off)) 2 I D = I DSS.(1 + I 2 2 D.R S / 16 - I D.R S /2) I D = 12 x 10-3 x (1 + I 2 D / 16 - I D.330 /2) I 2 D I D +12 x 10-3 = 0 I D = 4.6 ma or I D = 31.9 ma Since I D cannot be greater than I DSS, Choose I D = 4.6 ma Assume V DS = 50 % V DD ---- V DS = 5V Applying KVL to output circuit V DD = I D. R D + V DS + I D.R S Department of ECE, CIT, Gubbi Page no. 55

56 Experiment No: 10 Date: RC Phase Shift Oscillator Aim: To design and test an RC phase shift oscillator for the given frequency of oscillations using FET. Apparatus Required: Theory: Sl. No. Particulars Range Quantity 1. FET BFW Resistors & Capacitors As per design - 3. CRO Probes - 3 Set 4. Multi meter DRB Spring board and connecting wires - - An oscillator is an electronic circuit that produces a repetitive electronic signal, often a sine wave or a square wave. RC-phase shift oscillator is used generally at low frequencies (Audio frequency). It consists of a CE amplifier as basic amplifier circuit and three identical RC networks for feedback, each section of RC network introduces a phase shift of 60 and the total phase shift by feedback network is 180. The CE amplifier introduces 180 phase shift hence the overall phase shift is 360. The feedback factor for an RC phase shift oscillator is 1/29, hence the gain of amplifier (A) should be 29 to satisfy Barkhausen criteria. The Barkhausen criteria states that in a positive feedback amplifier to obtain sustained oscillations, the overall loop gain must be unity (1) and the overall phase shift must be 0 or 360. When the power supply is switched on, due to random motion of electrons in passive components like resistor, capacitor a noise voltage of different frequencies will be developed at the collector terminal of transistor, out of these the designed frequency signal is fed back to the amplifier by the feedback network and the process repeats to give suitable oscillation at output terminal Applications: 1. Mostly used at audio frequencies, used in equipments that emits beeps. e.g., GPS units. 2. Used in electronic organs like voice synthesizers and electronic musical instruments like pianos. Department of ECE, CIT, Gubbi Page no. 56

57 R D = ( x 10-3 x 330) / 4.6 x 10-3 R D = 756 Ω Choose R D = 820 Ω X CS < < R S X CS = R S / 10 1 / ( 2 π f C S ) = 470 / 10 Let f = 100 Hz C S = 33 µf Choose C S = 47 µf Choose C C1 = C C2 = 0.1 µf Tank Circuit : Assume f o = 1 khz f o = 1/[(2 x π x 6 x R x C] Choosing R = 10 k Ω C =1/[2 x π x f o x R x 6 ] C = 6.5 nf Department of ECE, CIT, Gubbi Page no. 57

58 Procedure: 1. Components / equipment are tested for their good working condition. 2. Connections are made as shown in the diagram 3. The quiescent point of the amplifier is verified for the designed value. 4. Observe the output wave form on CRO and measure the frequency. 5. Verify the frequency with the designed value. Result: Q Point: VDS = V, I D = ma f o Theoretical = Hz f o Practical = Hz Department of ECE, CIT, Gubbi Page no. 58

59 Circuit Diagram: Hartley Oscillator C B E Vo SL100 or CL100 Circuit Diagram: Colpits Oscillator t T fo = 1 / T Hz Design: Given, V CE = 2.5 V and I C = 1 ma Assume β = 100 V CC = 2V CE = 2 X 2.5 = 5 V Let V RE = 10% V CC =0.5 V R E = V RE / ( I C + I B ) I B = I C / β = 1 ma / 100 = 10 µa Department of ECE, CIT, Gubbi Page no. 59

60 Experiment No: 11 Date : Aim: Hartley and Colpitt s Oscillator To design and test Hartley and Colpitt s oscillator for the given frequency of oscillations crystal oscillator using BJT. Apparatus Required: Theory: Sl. No. Particulars Range Quantity 1. Transistor SL Resistors & Capacitors As per design - 3. CRO Probes - 3 Set 4. Multi meter DCB, DIB - 2 each 6. Spring board and connecting wires - - An oscillator is an electronic circuit that produces a repetitive electronic signal, often a sine wave or a square wave. The Hartley oscillator is an LC electronic oscillator that derives its feedback from a tapped coil in parallel with a capacitor (the tank circuit). A Hartley oscillator is essentially any configuration that uses a pair of series-connected coils and a single capacitor. It was invented by Ralph Hartley. A Colpitt s oscillator, named after its inventor Edwin H. Colpitt s, is one of a number of designs for electronic oscillator circuits using the combination of an inductance (L) with a capacitor (C) for frequency determination, thus also called LC oscillator. One of the key features of this type of oscillator is its simplicity (needs only a single inductor) and robustness. A Colpitt s oscillator is the electrical dual of a Hartley oscillator. Fig. 1 shows the basic Colpitt s circuit, where two capacitors and one inductor determine the frequency of oscillation. The feedback needed for oscillation is taken from a voltage divider made by the two capacitors, where in the Hartley oscillator the feedback is taken from a voltage divider made by two inductors (or a tapped single inductor). The basic CE amplifier provides 180 phase shift and the feedback network provides the remaining 180 phase shift so that the overall phase shift is 360 to satisfy the Barkhausen criteria. The Barkhausen criteria states that in a positive feedback amplifier to obtain sustained oscillations, the overall loop gain must be unity ( 1 ) and the overall phase shift must be 0 or 360. Department of ECE, CIT, Gubbi Page no. 60

61 R E = 0.5 / ( 1 m + 10 µ ) = 495 Ω Choose R E = 470 Ω Apply KVL to collector loop V CC I C R C V CE V E = 0 R C = ( V CC V CE V E ) / I C = ( ) / 1 m R C = 2 kω Choose R C = 1.8 kω Let I R1 = 10 I B = 10 X 10 µa = 100 µa V R2 = V BE + V E = = 1.1 V ( Since transistor is silicon make V BE = 0.6 V ) R 2 = V R2 / ( I R1 I B ) = 1.1 / ( 100 µa - 10 µa ) R 2 = 12.2 kω Choose R 2 = 13 kω R 1 = ( V CC V R2 ) / I R1 = ( ) / 100 µa R 1 = 39 KΩ Choose R 1 = 38 kω X CE < < R E ; X CE = R E / 10 => 1 / ( 2 π f C E ) =470 / 10 Let f = 100 Hz C E = 33 µf Choose C E = 47 µf Choose C C1 = C C2 = 0.1 Hartley oscillator: Design of tank circuit: Assume fo = 100 khz Formula f o = 1 / 2π (L T. C) Where L T = L 1 + L 2 Barkhausen s criterion is A.β = 1 Therefore β = 1/A = L 1 / L 2 For this circuit, A = 75 because gain of the amplifier is 75 L 2 = 75. L 1 Assume L 1 = 100 µh, therefore L 2 = 7 mh, then C = 0.4 nf Colpitt s oscillator: Design of tank circuit: Assume f o = 100 khz Formula f o = 1 / 2π (C T. L) Where C T = C 1. C 2 / (C 1 + C 2 ) Barkhausen s criterion is A.β = 1 Therefore β = 1/A = C 2 / C 1 For this circuit, A = 75 because gain of the amplifier is 75 C 1 = 75 C 2 Assume C 2 = 100pf, therefore C 1 = 7.5 nf, then L = 25.6 mh Department of ECE, CIT, Gubbi Page no. 61

62 When the power supply is switched on, due to random motion of electrons in passive components like resistor, capacitor a noise voltage of different frequencies will be developed at the collector terminal of transistor, out of these the designed frequency signal is fed back to the amplifier by the feedback network and the process repeats to give suitable oscillation at output terminal Procedure: 1. Components / equipment are tested for their good working condition. 2. Connections are made as shown in the diagram 3. The quiescent point of the amplifier is verified for the designed value. 4. Observe the output wave form on CRO and measure the frequency. 5. Verify the frequency with the crystal frequency. Applications: 1. The Hartley/ Colpitt s oscillators are extensively used on all broadcast bands including the FM MHz band. Result: Hartley Oscillator: Q Point: V CE = V, I C = ma, Gain (A) = f o Theoretical = Hz, f o Practical = Hz Colpitt s Oscillator: Q Point: V CE = V, I C = ma, Gain (A) = f o Theoretical = Hz, f o Practical = Hz Department of ECE, CIT, Gubbi Page no. 62