An Analysis Methodology for Dynamic Power Gating

Transcription

1 An Analysis Methodology for Dynamic Power Gating Ken Choi and Jerry Frenkil Sequence Design Inc. 469 El Camino Real, Suite 202, Santa Clara CA 95050, USA Abstract High leakage current in deep-submicrometer designs have become a significant contributor to total power dissipation of CMOS circuits, as short-channel transistors require lower power supply levels to reduce power consumption. This forces a reduction in the threshold voltage that causes a substantial increase of weak inversion current. As evidence of this effect, the 2006 Edition of the International Technology Roadmap for Semiconductors (ITRS) states that Leakage will become a major industry crisis, threatening the survival of CMOS itself. Among the leakage-control techniques that have been proposed so far, power gating, also known as MTCMOS, has traditionally been the most effective way to lower the leakage. This article describes a novel dynamic analysis methodology for power gated circuits which can be used as an electrical sign-off method for a full chip in deep sub-micrometer technology. The proposed methodology can achieve spice-comparable accuracy and full-chip-level performance for modern VLSI chip designs. 1. Introduction Historically, power has been one of the primary drivers of the evolution of modern electronic devices: from vacuum tubes (1906, Le De Forest) to transistors (1947, William Shockley), from BJTs (bipolar transistors) to FETs (field effect transistors), and from MOSFET (metal-oxide-semiconductor field-effect transistor) to CMOS (complementary metal-oxide-silicon) MOSFET. Moreover, as the scale of integration expands, more transistors, faster and smaller than their predecessors, are being packed into smaller chips and the steady growth in clock frequency and processing capacity per chip have dramatically increased power consumption. As the power consumption becomes critical, the chip designer should consider the power sources and the powerreduction methods in a more detailed manner than before, especially for leakage power because technology scaling results in leakage power increases. With respect to total power consumption, leakage power has increased from an almost negligible level to nearly 20 percent in 130-nanometer (nm) designs, 40 percent in 90-nm designs, and over 50 percent in 65-nm designs. Now, managing leakage power effectively is critical to the success of VLSI chip design, especially for mobile applications [1]. Several techniques have been proposed to reduce leakage power such as dual-vth [4], mixed-vth [5], off-off MOS stacking [6], input-vector control [7], multi-threshold (MT) CMOS [8], selective MTCMOS (SMT) [9], Zigzag super cut-off CMOS (ZSCCMOS) 1

2 [10], optimal Zigzag CMOS (OZ) [11], body-bias control [12], transistor width sizing [13], transistor channel scaling [14], and voltage islands [15]. Among the leakage-control techniques, power gating is one of the most effective ways to lower the leakage of a VLSI circuit in the leakage dominant era. Power-gating uses a PMOS transistor or an NMOS transistor to disconnect the circuit s supply voltage from the logic when the logic is inactive. This technique can reduce leakage by more than two orders of magnitude with negligible speed degradation. However, since the power-gating scheme was introduced in 1993 [16], designers have had difficulty deploying it due to the additional design complexity. One of the difficulties has been verification because the power-gating circuit impacts several critical design parameters directly such as virtual rail voltage drop, wake-up time, rush current, area, and delay. Therefore, verification of these effects is essential for avoiding the chip failure and increasing yield after fabrication. In this paper, first, leakage current in the sub-threshold region and the power-gating technique for leakage reduction are explained. Secondly, a proposed methodology for analyzing power-gated circuits and our analysis results with this methodology are presented. Finally, future directions of this approach are discussed and summarized. 2. Background 2.1 Leakage Current in Sub-threshold Region Leakage currents in NMOS or PMOS transistors depend substantially on: i) the voltage at the four transistor terminals (gate, source, drain, and substrate) and ii) geometrical dimensions of the four terminals as shown in Figure 1. Source Gate Drain n+ n+ p-substrate Substrate Figure 1. Four Terminals in MOSFET to Determine Leakage Current Generally, the components of the leakage current can be categorized as i) junction leakage due to interaction between drain (source) and substrate, ii) gate Leakage due to gate oxide thickness and electric field, and iii) sub-threshold leakage when gate voltage is in sub-threshold region. Sub-threshold leakage is the largest portion of the total leakage power for modern technology. When the gate voltage is below the threshold voltage, weak inversion current flows between the source and drain in an MOS transistor, and is referred to as subthreshold leakage current. The threshold voltage is the gate-to-source voltage when strong inversion (Vds > Vgs Vth) occurs and is a function of the work function between 2

3 gate and substrate, oxide thickness, Fermi voltage, the charge of impurities, and the dosage of ions implanted. The sub-threshold leakage current is represented as Isub leak = K V e e V V γv + ηv V W 2 1 ( T ) 1 L eff gs th0 s ds ds nvt VT where, V th0 is the zero bias threshold voltage, γ is the linearized body effect coefficient, V s is the source to bulk voltage, η is the DIBL (drain induced barrier lowering) coefficient, n is the sub-threshold swing coefficient of the transistor, V T =KT/q is the thermal voltage, and K 1 is a process constant. Most leakage reduction techniques focus on controlling one or more terms in the equation. Basically, the methods of the leakage reduction techniques are categorized as reducing W (transistor width), increasing L eff (channel length), cooling down V T (thermal voltage), reducing or making negative V gs (gate to source voltage), increasing V th0 (zero bias threshold voltage), increasing V s (source to bulk voltage), and reducing V ds (drain to source voltage) [17]. 2.2 Power Gating Mechanism Power-gating circuitry is shown in Fig. 2. In such a circuit, the supply voltage is turned off during the standby mode by using a PMOS transistor or an NMOS transistor; with proper switch sizing leakage-power can be reduced by more than two orders of magnitude. In active mode, the sleep transistor is on and the circuit functions as usual. In standby mode, the switch transistor is turned off, which disconnects the logic gate from power or ground. The basic mechanism by which the switch transistor reduces the leakage current of the power gated logic transistors is the increased body effect: the increased source voltage of the logic transistors, relative to their bodies, raises their thresholds. The resulting current flow from the power or to the ground is substantially reduced. (1) 3

4 sleep Virtual Vdd Low Vth Cells in Virtual Gnd sleep P N out High Vth SW 2 2 sleep Self Reverse Biasing A Self Reverse Biasing A sleep Off Off Off Off B 1 High Vth SW 3 SW Size B 1 High Vth SW 3 SW Size (a) Power Gating Circuit (b) Leakage Reduction Mechanisms Figure 2. Power Gating Circuit and Mechanisms 2.3 Rush Currents and Wakeup Time During standby mode, the virtual rails in the power-gated logic cells float to the nonpower gated supply level. When the power switch is turned on, all the current due to the charged floating nodes (rush current) in the power-gated block rushes into the virtual rail, resulting in a voltage bounce on that rail. This bounce takes some time (wakeup time) to settle down all the logic cells in the block, according to the power-switch structure and turn-on sequence as shown in Fig. 3. In active mode, the power-switch operates in linear region, in standby mode the power-switch operates in cut-off region, and in wake-up mode the power-switch operates in saturation region. Wake-up Current Source Low-Vth Logic Current Source Figure 3. Wakeup Mode Analysis SW: Saturation Fig 4 shows the general design requirements for rush current and wakeup time in modern chip design. The rush current, which is related to the noise margin of the circuit, is required to be less than ten percent of total discharge current and the wakeup time is required to be less than two or three clock cycles [18]. 4

5 Curren t [ ma ] V SS V [V] Figure 4. Design Requirements for Rush Current and Wakeup Time Rush current during wakeup is a critical issue in power-gating implementations, as it can cause large voltage drops and short term VDD collapse resulting in logical malfunctions. The designer must decide how much current flow and settling time are acceptable. It is basically a problem of the trade off between the rush current and the wakeup time as shown in Fig. 5. Therefore, an accurate and fast CAD tool and methodology to verify these phenomena for full-chip design are required for dependable sign-off. 2.4 Power Switch Sequence Impact Figure 5. Rush Current and Wakeup Time Trade-Off There are several ways to minimize the rush current during wakeup, but two of the more common approaches are i) step-wise turn-on [19] and ii) two pass power-switch control [20] as shown in Fig. 6. The step-wise-turn-on approach turns on the power switches consecutively in a daisy chain style. In this case, the rush current gradually increases as the number of switches is turned on. However, the rush current can be large unless the daisy chain is very slow. On the other hand, such a long daisy chain can cause long propagation delay and the slowly rising voltage can introduce other problems such as hot electron effects. Another approach is to separate the power switches into two passes: a weak transistor pass and a strong transistor pass. At wakeup, the weak transistors are turned on first so as to slowly turn on the rush currents. When the design is discharged (charged) to a voltage close to zero (VDD), the strong transistor pass is turned on ready for normal operation. 5

6 Figure 6. Rush Current Control Methods CoolTime, Sequence s timing and voltage drop analysis tool, can guide the designer in setting power switch structure and sequence for controlling wakeup (rush current and wakeup time). The following section illustrates the methodology and flow of powergating analysis with CoolTime. 3. CT-PGA (CoolTime-PowerGatingAnalysis) 3.1 CT-PGA Overview The goals of Power Gating Analysis are to determine the rush current and wake up time for particular power gating structures. More specifically, when PG switches are being turned on, to perform the following analyses: i) rush current analysis: determine the peak currents through the switches and the voltage impact of these currents on the power grid for rest of the design, and ii) wake-up time analysis: determine the amount of time before the instances in the PG block see a steady supply voltage and the instances in the alwayson block see a steady supply voltage. To achieve SPICE-like accurate rush currents and settling time for the power-gated block, an effective simulation and analysis flow using CoolTime has been developed as shown in Fig 7; this flow already has been used successfully with 65-nm full-chip-level designs. In this flow, CoolTime utilizes its built-in event simulator to achieve SPICE-level accuracy with extraordinary capacity and performance for full chip-level designs. Inputs for this solution are SPICE sub-circuits for the logic cells and switch cells, design data (lib, netlist, lef, def, etc.), user specified design constraints, and switch resistance models. CoolTime generates the circuit for an embedded spice-like simulator and analyzes the detailed time-variant behavior of the power-gated circuit during wakeup. The analysis results report rush current at the virtual power rail (header switch case), ground current, wakeup time, switch peak current, voltages of the power, ground, and virtual rails, and whole-chip-level voltage drop. In addition, during power up, it is extremely critical that the nearby logic continues to perform at speed without interruption. First, a contour map of the power up region must be generated. That data is then plugged into the next level of hierarchy. The worst case effective voltage is identified and instances located. Then the timing analysis report is scanned to find the presence of these instances within any critical path report. The most 6

7 important part of PGA is the report of how the near by logic is affecting by comparing before and after timing reports. Figure 7. CT-PGA Overview 3.2 CT-PGA Procedure CT-PGA enables the designer to rapidly obtain detailed information on rush currents and wake up times. First, CT-PGA internally checks the circuit operations after circuit simulation as shown in Fig.8 and then calculates the currents. 7

8 Figure 8. Circuit Operation Checking After calculating the rush currents, CoolTime calculates dynamic voltage drop on the real and virtual rails, along with the wakeup time. Then finally all the results are displayed graphically such as rush current, ground current, wakeup time, peak current for each switch, and whole-chip-level voltage drop. 3.3 CT-PGA Results Currents though the power switches The time-varying behavior of the currents though the power switches are analyzed as shown in the Fig. 9. Current (Ampere) 0.0ns 1.0ns 2.0ns 3.0ns 4.0ns Figure 9. Rush Currents 8

9 3.3.2 Ground current during wakeup Ground bounce during wakeup is shown in Fig. 10. When each switch is turned on, a rippling effect on the ground rail can be seen according to the power-switch topology and its turn-on sequence. In this case, the ripples are caused by the switching units of the delay elements in the switch timing chain. Current (Ampere) 0.0ns 1.0ns 2.0ns Figure 10. Ground Currents 3.0ns 4.0ns Wakeup time CT-PGA generates a list of the top-10 instances with the longest wakeup times and provides a graphical view of the wakeup time as shown in Fig. 11. Here, we see that the block woke up in ~2.0ns. Voltage (Volt) 0.0ns 1.0ns 2.0ns Figure 11. Wakeup Time 3.0ns 4.0ns 9

10 3.3.4 Power-switch peak currents CT-PGA generates a list of the first 10 switches in a sequential chain and provides a graphical view of each switch s peak current as shown in Fig. 12. Peak Current Location Switch_Header_i1:GVDD , 5000 Switch_Header_i4:GVDD , Switch_Header_i8:GVDD , Switch_Header_i7:GVDD , Switch_Header_i10:GVDD , Switch_Header_i11:GVDD , Switch_Header_i5:GVDD , Switch_Header_i2:GVDD , Switch_Header_i14:GVDD , 7000 Switch_Header_i17:GVDD , Current (Ampere) At 1.06ns (106 steps, 10 ps / each time step) 0.0ns 1.0ns 2.0ns 3.0ns Figure 12. Power Switch Peak Currents 4.0ns Supply, virtual rail, and ground voltages The first graph in Fig. 13 shows supply voltages over time and the stair-step effect is adjustable by setting up simulation time-step in CoolTime. The second graph shows voltages of logic cells at virtual rail over time. And the last graph shows ground voltages over time and the ripples represents the switch turn-on sequence. 10

11 Figure 13. Supply, Ground and Virtual-Rail Voltages Chip-level voltage drop CoolTime displays the whole-chip-level voltage drop in an animated VCR over time as shown in Fig. 14. This enables the user to see how the voltage drop results over time. Figure 14. Chip Level Voltage Drop 4. Summary and Conclusions Optimum power-switch design and implementation is a complicated design task in each advanced technology generation. Chip designers should evaluate the effectiveness and overhead of power-switch structures and turn-on sequencing based on the following criteria: i) leakage reduction, ii) performance, iii) mode transition overhead, and iv) reliability. So far, there are few solutions and methodologies to verify the power-gating design after implementing the power switches. In this paper, we have described an effective, accurate, and run-time efficient sign-off methodology, and demonstrated with an industrial full-chip-level design. The main benefits of this approach are i) accurate rush current and wake-up time analysis, and ii) the speed and accuracy of CoolTime event simulation based full-chip-level dynamic voltage drop analysis. 11

12 References [1] International Technology Roadmap for Semiconductor (ITRS), 2006 Edition, Executive Summary [2] Sequence Design CoolTime TM User s Guide [3] Sequence Design CoolTime TM Reference Manual [4] L.Wei, Z.Chen, M.Johnson, and K.Roy, Design and optimization of low voltage high performance dual threshold CMOS circuits, DAC 98, pp , Jun [5] L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De, Mixed Vth CMOS circuit design methodology for low power applications, DAC, 1999 [6] J.P.Harter and F.Najm, A gate-level leakage power reduction method for ultra-low-power CMOS circuits, CICC 1997, pp , Oct [7] A. Abdollahi, F. Fallah, and M. Pedram, Leakage current reduction in CMOS VLSI circuits by input vector control, IEEE Transaction on VLSI, Feb [8] S.Mutoh, T.Douseki, Y.Matsuya, T.Aoki, S.Shigematsu, and J.Yamada, 1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS, IEEE J. Solid-State Circuits, vol. 30, pp , Aug [9] K.Usami, N.Kawabe, and M.Koizumi, Automated selective multi-threshold design for ultra-low standby applications, ISLPED 02, pp , Aug [10] K.Min, H.Kawaguchi, and T.Sakurai, Zigzag super cut-off CMOS (ZSCCMOS) block activation with selfadaptive voltage level controller: An alternative to clock-gating scheme in leakage dominant era, IEEE International Solid-State Circuits Conference, pp , Feb [11] K-w Choi, Y. Xu, and T. Sakurai, "Optimal zigzag (OZ): an effective yet feasible power-gating scheme achieving two orders of magnitude lower standby leakage," Proceeding of 2005 Symposium on VLSI Circuits, pp , June 14-18, [12] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, IEEE International Solid-State Circuits Conference, February 2002, Vol.1, p [13] M. Hashimoto and H. Onodera, Post-Layout transistor sizing for power reduction in cell-based design, Proc. of ACM/IEEE Design Automation Conference. (ASP-DAC), pp , [14] P. Gupta, A.B. Kahng, P. Sharma, and D. Sylvester, Selective gate-length biasing for cost-effective runtime leakage control, IEEE/ACM Design Automation Conference, pp , [15] J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, Architecting voltage islands in Core-based System-on-a-Chip Designs, International Symposium on Low Power Electronics and Design, [16] M. Horiguchi, T. Sakata, and K. Itoh, Switched-source-impedance CMOS circuit for low standby subthreshold current gigascale LSI s, Proceeding of 2005 Symposium on VLSI Circuits, pp , May 19-21, [17] J. Frenkil and S. Venkatraman, Power Gating Design Automation, Closing the Power Gap Between ASIC and Custom, Springer, 2007, Chapter 10. [18] J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, and S. Borker, Dynamic sleep transistor and body bias for active leakage power control of microprocessors, IEEE J. Solid-State Circuits, vol. 38, pp , Nov [19] S. Kim, S. Kosonocky, and D. Knebel, Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures, International Symposium on Low Power Electronics and Design, August 2003, pp [20] P. Royannez, et. al., 90nm Low Leakage SoC Design Techniques for Wireless Applications, IEEE International Solid-State Circuits Conference, February 2005, pp Authors Kyu-won (Ken) Choi received the PhD. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, USA in During the PhD. from 1996 to 2003 he had proposed and conducted several projects supported by NASA (National Aeronautics and Space Administration), DARPA (Defense Advanced Research Projects Agency) and NSF (US National Science Foundation) regarding power-aware computing/communication (PACC). Since 2004, he has been with the Takayasu Sakurai Lab. in the University of 12

13 Tokyo, Japan as a post-doc researcher, working on leakage-power-reduction circuit techniques. In the past, he had sixyear working experience as a full-time engineer in industries such as Samsung Electronics, Broadcom, and Korea Telecom Research Center. Dr. Choi worked with Sequence Design Inc. from as a senior engineer and a technical consultant for low-power designs, and now is on staff at IIT in Chicago. Jerry Frenkil is currently CTO and VP of Engineering for Sequence Design and has over 25 years of experience in the semiconductor and EDA industries. Mr. Frenkil was a co-founder of Sente which later merged with Frequency Technology to form Sequence Design. At Sente, Mr. Frenkil was the Vice President of Low Power Design, where he architected Watt Watcher, the predecessor of PowerTheater. Prior to co-founding Sente, Mr. Frenkil was an independent consultant focused on IC design. He also held management positions at VLSI Technology and Mostek. Mr. Frenkil holds a BSEE from the University of Texas. He has published several papers on IC and Low Power Design, has contributed chapters to three books, and holds several patents on circuit design and design automation. 13