DITHERING OPTIONS FOR INTEGRATED RELAXATION OSCILLATORS

Transcription

1 Rev. Roum. Sci. Techn. Électrotechn. et Énerg. Vol. 62, 1, pp , Bucarest, 2017 Électronique et transmission de l information DITHERING OPTIONS FOR INTEGRATED RELAXATION OSCILLATORS ȘERBAN MIHALACHE 1, FLORIN-SILVIU DUMITRU 1, ADRIANA FLORESCU 2, SEVER VIOREL PAȘCA 2 Key words: Dithering, Frequency modulation, Noise spread, Relaxation oscillator, Spread-spectrum. This paper presents an extensive look at dithering, a form of frequency modulation, commonly used for integrated relaxation oscillators in order to achieve a wideband spread of output noise. A particular relaxation oscillator topology is chosen as a reference. Linear dithering, step dithering and sinusoidal dithering are analyzed in terms of the dithering frequency and dithering percentage. A discussion on the implementation of these techniques is made. Simulation results for applying these techniques to the proposed oscillator show roughly the same baseband amplitude reduction, but a lower total spectral power for sinusoidal dithering. An experimental version using discrete devices is implemented and tested, confirming the simulated results. 1. INTRODUCTION When it comes to supplying power to integrated circuits such as microprocessors, the first key aspect is efficiency. The best power-supplies for these applications will be switched-mode power supplies [1]. Several topologies available for the control method of these converters exist, but the most common by far are voltage-mode control and peak or valley current-mode control [2]. By its nature, this mixed-signal system will only require a simple digital clock for its functionality, so a simple square wave will suffice. However, a sinusoidal oscillator [3, 4] can also be used, which has the advantage of much lower noise being injected into the load system. Still, square wave oscillators are more common and easier to implement, and there are several ways this can be done [5 8], but this paper will be focusing on using a dual-comparator relaxation oscillator topology [9] as the basis for all further analysis. Like any non-sinusoidal wave, however, this digital clock s frequency spectrum extends over a relatively wide band. This can become a problem, because the oscillator s spectrum will be translated to the entire system s output as noise. Since the goal is to aim for higher and higher switching frequencies, this brings forth the risk of injecting noise into the load within its own operating band, and compromising the data or the processes therein [10]. One solution to this problem consists of spreading out the output noise, by spreading out the oscillator s spectrum, that is, by using a form of frequency modulation called dithering. The name is derived from audio and video signal processing [11] and it refers to an intentional and controlled adding of noise in order to reduce the perceived effect of quantization noise in the desired signal. For integrated circuits, the term was borrowed to refer to a controlled spreading of the noise spectrum in order to reduce the noise magnitude within a certain frequency band. In Section 2, the principle of operation and specific design considerations for this type of oscillator are outlined and different dithering options and implementations are discussed and reviewed in Section 3. Section 4 presents the simulation and experimental results. Section 5 offers a discussion on the different dithering mechanisms and comparisons are made between all versions based on the obtained results. Conclusions are drawn. 2. PRINCIPLES OF OPERATION FOR RELAXATION OSCILLATORS The basic topology used as a reference for relaxation oscillator design is one of the most widely used in the industry. It is illustrated in Fig. 1. The simplified version requires two voltage references, two comparators, two current sources, a load capacitor and a set-reset latch (SR latch) and some minimal switch logic. The functionality of this type of oscillator can easily be explained by observing the states in which the circuit can find itself in: 1) Start-up: When the circuit is starting up for the first time, the load capacitor C L will be fully discharged, and the voltage on it, V cap, will be zero. This means that the set comparator output will be logical 0, while the reset comparator output will be logical 1, thus holding the latch in reset. In turn, this means we start with the oscillator output, V osc, at logical 1. 2) Charging: With the oscillator output high, switches S1 and S2 will be OFF and ON, respectively, opening a path for the top current, I C, to charge the capacitor. Note that, once V cap becomes higher than V refl, both comparators are outputting logical 0, equivalent to the STORE state for the latch. The capacitor will continue charging until V cap reaches V refh. Once this happens, the set comparator will trigger and V osc will go low. 3) Discharging: With the oscillator output low, switches S1 and S2 will now be ON and OFF, respectively, closing the top current path and opening the path for the bottom current, I D, to discharge the capacitor. Once V cap goes lower than V refl, the reset comparator will trigger and V osc will go high. This astable behavior is the essence of any square wave oscillator. By selecting the two voltage references (obviously V refh should be higher than V refl ), the charge and the discharge currents I C and I D, and the value of the capacitance, C L, both 1 Politehnica University of Bucharest, Faculty of Electronics, Telecommunication and Information Technology, Department of Electronic Devices, Circuits and Architectures, smihalache@gmail.com, florinsdumitru@gmail.com 2 Politehnica University of Bucharest, Faculty of Electronics, Telecommunication and Information Technology, Department of Applied Electronics and Information Engineering, adriana.florescu@upb.ro, pasca@elmed.pub.ro

2 62 Șerban Mihalache et al. 2 the frequency, f, and the duty cycle (DC), of this oscillator can be controlled in accordance with (1) and (2) I C I D f = I C + I D CL DC 1 ( V V ) I refh refl, (1) = D. (2) IC + ID Fig. 1 Simplified schematic of the reference oscillator. Since this type of oscillator outputs a rectangular wave, through Fourier series decomposition, we determine the magnitude of the wave s individual components, or harmonics, A k, in (3), where V A is the oscillator output amplitude and k is the harmonic number or order. We can immediately see that the choice of the oscillator s DC will impact the output spectrum. Typical values used are: 0.5, 0.33, 0.25, 0.2 and 0.1. The most common and easiest to implement of these is DC = 0.5. We note identical results for any DC > 0.5 as for (1 DC). The first 20 harmonics have been normalized to the first harmonic of the Fourier series for DC = 0.5 and plotted in Fig. 2 for each of the afore-mentioned DC s. For a base frequency with a value of a few MHz, this many harmonics cover most applications of interest. As expected, notice how, for DC = 0.5, all even harmonics are removed from the spectrum. A good measure to see how much noise the oscillator would inject to the load is to determine the rms power of all higher-order harmonics, i.e. above k = 2, for a reference resistance of 1 Ω and V A = 5 V. The results for the cases considered in this section are given in Table 1. We can clearly see that the lowest value is for DC = 0.5. As such, absent other constraints, a good design should target this DC as a first step to minimizing the output noise. VA 2 Ak = 1 cos(2π k DC). (3) kπ 3. DITHERING PRINCIPLES AND TYPES Simply choosing the best DC, if at all possible, isn t enough to meet the output noise requirements. One way to do this is to use a form of frequency modulation, called dithering, in order to spread out the oscillator s output spectrum over a wider band, reducing the magnitude of the frequency components within the desired target band. For the given system in Fig. 1, dithering can be achieved by: time-varying reference voltages (V refl and V refh ), time-varying currents (I C and I D ), any combination thereof. Table 1 Higher-order harmonics rms power vs. DC. DC rms Power [W] For this paper, we discuss dithering by means of timevarying currents, but the principles are the same for any case. Denoting the base parameters (without dithering) frequency and charge-discharge currents as f 0, I C0 and I D0, the following control parameters become available: dithering type = the shape of the waveform used as a dithering signal (modulator signal); particularly, the shape of I C and I D, f D = the dithering signal s frequency; it is always chosen to be smaller than f 0, f max = the maximum frequency in the base band, achieved by dithering, D % = dithering percentage = the ratio of (f max f 0 ) to f 0, in percent, DC D = the dithering signal s duty cycle; we will assume DC D = 0.5 for all cases, considering the discussion in Section 2, N step = the number of bits used for step dithering quantization. The main dithering types available are named according to the shape of the dithering signal: Linear dithering an independent triangular wave (or analog ramp), Step dithering an independent staircase waveform (or digital ramp), Step self-dithering a staircase waveform (or digital ramp) derived from the oscillator s output itself, Sinusoidal dithering an independent sine wave. The most direct method is step self-dithering, with a very simple implementation: a chain of D-type flip-flops (DFFs) follow the oscillator output, their outputs being decoded into the control signal for a current digital-analog converter (DAC), feeding back into C L. The number of DFFs required depends on the desired f D. The maximum number of bits available is equal to the number of DFFs minus one. Because of this very simple implementation, self-dithering is almost always preferred over simple step dithering. The downsides are the few choices available for f D and the fixed DC D of 0.5. The slight kink in the dithering signal s shape, inherent due to its self-generating nature, has negligible effects vs. the more regular independent waveform of step dithering, in terms of the output frequency spectrum. For ICs, unfortunately, linear dithering can only be obtained by means of a secondary oscillator, to generate a triangular voltage waveform (usually by the same mechanism as the main oscillator, but at a much lower frequency, f D, meaning a higher load capacitance, since the current cannot be reduced indefinitely), which must then be processed by a voltage-current converter. Alternatively, this type of dithering becomes more straightforward when using time-varying reference voltages, since the triangular voltage waveforms can be used as voltage references for the main oscillator, but this would require two additional oscillators, leading to a large increase in chip area.

3 3 Dithering options for integrated relaxation oscillators 63 Fig. 2 Normalized Fourier series decomposition of the oscillator s output for different DCs. Best results obtained for DC = 0.5. We anticipate that sinusoidal dithering would yield the best results, since there would be a single frequency component used as a modulator signal, but implementing it is a bit more complicated. One way to do it would be to use a chain of DFFs and a low-pass filter (LPF), but this would imply some degree of distortion if the driving signal used is the oscillator itself. Another way would be by implementing a Wien-bridge or some other frequency selective feedback oscillator to generate a pure sine wave. All discussed waveforms are exemplified in Fig. 3. Fig. 4 Magnitude characteristic of the output FFT. Zoom-ins provided for the base-band and the second harmonic. First, the three dithering techniques are compared amongst themselves, for a fixed set of control parameters common between them: f D 2 khz, DC D = 0.5, D = 12.5 %, N step = 3. These values have been chosen as typical values for adding dithering to an oscillator with the base parameters given above. The FFT results for this case is given in Fig. 5. Fig. 3 Example waveforms for linear, step and sinusoidal dithering frequency and other parameters chosen as per Section SIMULATION AND EXPERIMENTAL RESULTS The proposed oscillator s mechanisms have been implemented in MATLAB, as well as the various dithering techniques discussed, similar to their actual potential implementations. The base parameters used for this implementation are: f 0 = 2.2 MHz, DC = 0.5, I C0 = 5 µa. The output s FFT is given in Fig. 4. Fig. 5 Magnitude characteristic of the output FFT. Base-band zoom-in (TOP) and third harmonic band (BOTTOM). Parameters: f D 2 khz, DC D = 0.5, D = 12.5 %, N step = 3.

4 64 Șerban Mihalache et al. 4 Fig. 6 Magnitude characteristic of the output FFT for each dithering type vs. no dithering: linear (TOP), step (MIDDLE), sinusoidal (BOTTOM). Base-band and third harmonic zoom-ins. Parameters: f D 2 khz, DC D = 0.5, D = 12.5 %, N step = 3. Fig. 7 Magnitude characteristic of the output FFT for each case: no dithering (top), linear dithering (upper middle), step dithering (lower middle) and sinusoidal dithering (bottom).

5 5 Dithering options for integrated relaxation oscillators 65 The FFT results are shown separately, for linear dithering, step dithering and sinusoidal dithering in Fig. 6. Then, for each dithering type, f D and D are varied separately, as well as the number of bits for step dithering, in order to determine each parameter s impact on the FFT. The values used are given in Table 2. Table 2 Simulation values for f D, D and N step f D [khz] D % 5 % 12.5 % 25 % N step In order to fully verify the validity of our results and their real-world applicability, an experimental version has been implemented. Due to the lack of resources to implement the system as an integrated circuit, a discrete-device based prototype has been designed and simulated in LTSpice IV. In order to improve system performance and testing metho-dology efficiency, all digital circuits and control signals have been implemented on a Basys2 FPGA. The oscillator s output frequency spectrum has been analyzed in the following cases: the basic oscillator without dithering, with linear dithering, with step self-dithering, and with sinusoidal dithering. The measured magnitude plots of the FFT are presented, in order, in Fig. 7. Note that, due to the limitations of the discrete devices and of the measurement setup, the experimental version targets very different parameter values than the simulated version: f 0 = 35 khz, f D = 350 Hz, I C0 = 1.8 ma. 5. RESULTS INTERPRETATION AND DISCUSSION In order to get a better and clearer view of what exactly is going on, additional information is provided in Tables 3 5, giving the average in-band values for the magnitude of the output FFT for the base-band ( MHz and above) and for the third harmonic band ( MHz and above). All measured values are provided in Table 6. Table 3 FFT magnitude vs. f D f D [khz] Without dithering [db] Linear dithering [db] Step dithering [db] Sinusoidal dithering [db] Table 4 FFT magnitude vs. N step for step self-dithering N step Fig. 8 The experimental prototype PCB used for measurements. The main blocks are highlighted and tagged: the voltage and current references, the main oscillator, the secondary oscillator used for linear dithering, the 2 nd order Sallen-Key filter used for sinusoidal dithering. The Basys2 FPGA used for step self-dithering is not shown. The experimental prototype PCB is shown in Fig. 8. The main blocks are highlighted and tagged: the voltage and current reference circuitry, the main oscillator, the secondary oscillator used to generate the linear dithering signal, and the 2 nd order Sallen-Key filter used to obtain the sinusoidal dithering signal from the linear ramp. The Basys2 FPGA containing the digital circuits for step self-dithering is not shown. From these results and from those given in Sections 3 and 4, we can see how the three types of dithering offer roughly the same base-band and third harmonic band attenuation. However, somewhat expectedly, sinusoidal dithering leads to much lower inter-harmonic distortion due to its greatly reduced spectral content. At the same time, step dithering has reduced inter-harmonic distortion for higher-order harmonics. As for the dithering frequency itself, we note that there is almost no benefit to going to a very low frequency, as the results are roughly the same for all considered frequencies. As such, it is better to go for a higher frequency, to greatly reduce the area requirement for the additional circuitry.

6 66 Șerban Mihalache et al. 6 For step dithering, for a higher number of bits, the spectrum morphs into the spectrum for linear dithering, as expected. Finally, as the dithering percentage is made larger, consequently extending the base-band and the harmonic bands, the magnitude of the attenuation increases as expected, but care must be taken to avoid ending up with a higher total effective noise power. Also note that, for step self-dithering, as the dithering percentage is made larger without increasing the number of bits, the high-frequency content injected by the fast transitions between steps becomes more and more significant, decreasing the smoothness of the attenuation of the base-band and of the harmonic bands, since the amplitude of this high-frequency noise gets higher and more distortion occurs. As a last point to consider, one can observe how sinusoidal dithering, albeit being the best type of dithering using the criteria presented, still suffers from a non-constant attenuation at the edges of the base band and of the higher harmonic bands, where the magnitude of the frequency spectrum increases, a phenomenon commonly known as frequency shoulders. While this paper does not tackle ways in which this effect can be mitigated, there are registered patents on using an altered sinusoidal signal, with sharpened peaks and troughs, instead of a pure sinusoidal wave, as a dithering signal, thereby making the attenuation constant [12]. Table 5 FFT magnitude vs. D % D [%] Without dithering [db] Linear dithering [db] Step dithering [db] Sinusoidal dithering [db] Table 6 Measured FFT magnitude f 0 [khz] 35 f D [Hz] (1) 350 f D [Hz] (2) 273 D [%] 12.5 N step 4 No dithering [db] Linear dithering [db] Step dithering [db] Sinusoidal dithering [db] (35 khz) (1) For linear and sinusoidal dithering. (2) For step dithering. (105 khz) CONCLUSIONS The problem of applying a form of frequency modulation, called dithering, to the square wave digital clock signal of a mixed-signal system has been discussed. The main motivation behind this spread-spectrum technique is to reduce the noise injected into the operating band of the load of the mixed-signal system. The mixed-signal system chosen as the basis for the discussion was a relaxation oscillator using a dualcomparator and dual-reference topology. Three types of dithering have been investigated: linear ramp dithering, using a triangular wave as the dithering signal; step self-dithering, using the oscillator s own output and frequency divider and a DAC to generate a digital ramp; and sinusoidal dithering, using a sinusoidal wave as the dithering signal. Simulations have been run using MATLAB for each type of dithering using several values for the control parameters, the dithering frequency f D, the dithering percentage D and the number of steps for step self-dithering. A discrete-device based experimental prototype has been developed using LTSpice IV, and consisting of a custommade PCB and a Basys2 FPGA for the digital circuitry. Due to limitations, different values for the main frequency and, consequently, the dithering parameters, have been used. The simulation and experimental results are in accordance and confirm that the best type of dithering, in regards to obtaining relatively constant noise attenuation in the oscillator s baseband and the higher order harmonics bands, is sinusoidal dithering. However, step self-dithering is much easier to physically implement, especially in an integrated circuit where circuit area is a key factor, and its performance is only marginally less than that of sinusoidal dithering.

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