Design of an Oscillator with Low Phase Noise and. Medium Output Power in a 0.25 µm GaN-on-SiC. HEMT Technology

Transcription

1 IET-MAP 1 Design of an Oscillator with Low Phase Noise and Medium Output Power in a 0.25 µm -on-sic Technology Hang Liu (liuhang@ntu.edu.sg), Xi Zhu (forest.zhu@mq.edu.au), Chirn Chye Boon (eccboon@ntu.edu.sg), Xiang Yi (yixiang@ntu.edu.sg) Abstract To investigate the effects of both the drain and gate bias voltages on the performance of oscillator, a 0.25 µm -on-sic oscillator is presented in this paper. Utilizing the designed oscillator, the trade-off between phase noise and output power is effectively investigated at the circuit level. As a result, the designed oscillator can provide low phase noise and medium output power simultaneously. The phase noise at VGS = -2.3 V and VDS = 3.3 V is measured to be -112 dbc/hz and -143 dbc/hz at 100 khz offset and 1 MHz offset respectively from a GHz carrier, with an output power of more than 14 dbm. Moreover, the output power can be boosted to 26 dbm, if a drain bias 16 V is used, while good phase noise of MHz is still achievable. The achieved phase noise is low among all reported oscillators. This work has successfully demonstrated that the monolithic oscillator fabricated in -on-sic technology features low phase noise as well as medium output power simultaneously. Index Terms -on-sic, high electron-mobility transistor (), integrated oscillator and ultra-low noise. This research was supported by the National Research Foundation Singapore through the Singapore MIT Alliance for Research and Technology (SMART)'s Low Energy Electronic Systems (LEES) research programme. The authors are with the VIRTUS, School of Electrical Electronic Engineering, Nanyang Technological University, Singapore ( liuhang@ntu.edu.sg).

2 IET-MAP 2 I. INTRODUCTION Oscillator is a key component of many communication systems. The signal integrity of such systems is often limited by the oscillator's phase noise. In particular, the modern wireless communication systems utilize the advanced digital modulation schemes to enhance the data rates, and may require the oscillator to have phase noise lower than -110 dbc/hz at 100 khz frequency offset [1]. For such low phase noise, dielectric resonator oscillators (DRO) have been used in the past [2]. However, the DRO is usually bulky and costly compared to the monolithic oscillator. Therefore, research on design of compact and low-cost monolithic oscillators with low phase noise have attracted extensive attention in the last years [1, 3-17]. To achieve low phase noise, heterojunction bipolar transistor (HBT) based designs are inherently better than the field effect transistor (FET) based ones because HBT device has inherently lower flicker noise corner frequency than the FET device [3]. Thus, several low phase noise oscillators have been designed in gallium arsenide (GaAs), indium phosphide (InP) HBT and silicon germanium (SiGe) HBT technologies [1, 3-5]. One of the drawbacks of such oscillators is that the output power is limited by the relatively low breakdown voltage. To overcome this problem, gallium nitride () high electron-mobility transistors (s) have been recognized as high power and high frequency devices for next generation wireless, space, military and many other applications. The fundamental material properties of enable a much higher voltage handling and better heat sinking capability compared to GaAs/InP and SiGe [6-18]. These advantages can enable monolithic oscillators to be realized with significant improvement in output power, thus potentially eliminating the need for additional power amplifiers. However, the design of a monolithic oscillator with low phase noise in technology still remains a great challenge due to the simulation inaccuracy, which is caused by the lack of accurate model. To simulate phase noise, very accurate device small-signal, largesignal, and noise models must be available. In addition, simulators may also vary in their accuracy in predicting the phase noise. Although there are some excellent publications on the high power monolithic oscillators in the literature [6-17], the achieved phase noise performance is still inadequate and thus requires further improvement.

3 IET-MAP 3 In this paper, a 0.25 µm -on-sic oscillator is designed and then the effects of both the drain and gate bias voltages on the phase noise of this oscillator are investigated. Consequently, low phase noise and medium output power are achieved simultaneously. In contrast, most of previously published works are mainly focused on a fixed-drain bias. It is noticed that the phase noise of the designed oscillator can be improved, if an appropriate drain bias is used. The measured phase noise at VGS = -3 V and VDS = 16 V is dbc/hz and -132 dbc/hz at 100 khz offset and 1 MHz offset respectively from GHz carrier. Moreover, it delivers a 26 dbm output power with approximately 30 db second harmonic suppression. The phase noise is also measured at VGS = -2.3 V and VDS = 3.3 V to be -112 dbc/hz and -143 dbc/hz at 100 khz offset and 1 MHz offset respectively from GHz carrier, while the output power is more than 14 dbm. The paper is organized in the following way. In Section II, an evaluation of the state-of-the-art oscillators is performed. Then, the design consideration of an oscillator with low phase noise is presented in Section III. In Section IV, the measurement results of the designed oscillator in terms of the effects of different gate bias and drain bias on the phase noise as well as output power are investigated and compared with the previously published works. Finally, the conclusion is drawn in Section V. II. EVALUATION OF THE STATE-OF-ART OSCILLATORS The performance summary of several recently published state-of-art multi-ghz SiGe, GaAs and monolithic oscillators are given in Table I. As shown in Table 1, most oscillators are designed mainly for low frequency applications due to the device limitation, such as the ones designed for C-band [6, 8, 10, 12, 14] and X-band [7, 9, 11, 13], while there are a few designed for millimeter-wave frequency such as Q- band [15] and V-band [16, 17], which are not included in the table. TABLE I THE SUMMARY OF THE STATE-OF-ART OSCILLATORS Ref. [JSSC 05] Tech. GaAs HBT Output Power (dbm) Osc. Freq. (GHz) Phase Noise 1MHz Supply Voltage (V) DC Power (W) Tuning Range (GHz)

4 IET-MAP 4 [MTT 12] [JSSC 07] [MTT 00] [MWCL 01] [JSSC 03] [MTT 04] [MTT 05] [MWCL 05] [MTT 07] [MTT 12] [MTT 13] [Our work - 7] [Our work - 8] * Core circuit only GaAs HBT SiGe HBT SiGe HBT * N/A ** N/A N/A N/A N/A N/A **Phase noise peaking As summarized in Table I, the oscillators designed in either SiGe or GaAs HBT technology can obtain reasonable phase noise at both 100 khz and 1 MHz offset frequency, while the GaAs HBT based designs can provide higher output power than the SiGe based ones. Although the oscillators can provide much higher output power than the GaAs HBT based designs, the phase noise performance of oscillators are much inferior to their GaAs counterparts, which needs further improvement. An exceptional design is presented in [8], which used an in-house facility. The phase noise of the designed oscillator can be kept as low as the ones designed in GaAs HBT while the output power of more than 20 dbm is still achieved. Another interesting "GaAs-like" oscillator is also designed in an in-house facility and is presented in [11]. This oscillator is investigated under a 5 V drain bias instead of utilizing large device with high drain bias to achieve the high output power. Although the phase noise of this oscillator still needs to be further improved, it opens up a new examination on the design of oscillators in technology for low voltage, moderate output power as well as low phase noise. It is also clearly shown in Table I that

5 IET-MAP 5 oscillators with large tuning range can only achieve a phase noise of -123 dbc/hz [6], whereas those fixed frequency ones can achieve a phase noise as low as -135 dbc/hz [14]. In addition, varactors are not available in Cree s process design kit (PDK). Thus, the fixed-frequency oscillator is chosen for our design. III. DESIGN CONSIDERATIONS OF AN OSCILLATOR WITH LOW PHASE NOISE A. Oscillator Design with Robust Start-up The overall circuit schematic of the proposed oscillator, including components on both die and PCB, such as bond wires (BW), and transmission lines (TL) is shown in Fig. 1(a) and its small-signal equivalent circuit of the core oscillator, which is marked with red circle, is shown in Fig. 1(b). (a) (b)

6 IET-MAP 6 Fig. 1 The designed oscillator (a) overall schematic including die and PCB components (b) equivalent small-signal circuit of the core oscillator In order to achieve high output power as well as ultra-low phase noise, Hartley topology with a fixed LC tank was chosen for the core oscillator, which is shown in Fig. 1(a) [10, 14]. The core oscillator is coupled with a large transistor M2 through an inter-stage capacitor Ccouple. The M2 is configured as a common-source driver amplifier and the Ccouple is chosen to be small so that only the high frequency components can pass through and feed into the driver amplifier. Moreover, the overall capacitance between Drain (D) and Gate (G) is represented as Cgd, which is formed by the parasitic capacitance of the and other capacitance. The variation of oscillation frequency at different biasing conditions will be shown in later section, and it gives a clue on how this capacitance changes. Inductors and L2, are chosen so that the oscillation condition at the frequency of interest is satisfied. The loop gain of the core oscillator,, which can be derived from the small-signal equivalent circuit as shown in Fig. 1(b) is given by = ( + ) + ( + ) + +, (1) where is the transconductance of the transistor M1 and is the load impedance of the core oscillator, which is equivalent to the impedance looking into the driver amplifier. Shifting all the non-zero terms to one side and equating the imaginary and real part to zero separately gives the oscillation frequency and gain condition as shown below = 1 2 ( + ), = 1. (3) The final gain expression including the driver amplifier gain at the oscillation frequency is given by: =. (4)

7 IET-MAP 7 These equations derived from the small-signal equivalent circuit are verified by simulation, and the results are shown in Fig. 2. To ensure a robust start-up, the simulation of the oscillator was performed using Agilent Advanced Design System (ADS) Electro-magnetic (EM) simulations are performed using ADS 3D finite element method (FEM) engine. The -on-sic device and all on-chip passive components are provided by Cree's commercially used PDK. The minimum length of the device is 0.25µm. First of all, the start-up open loop gain of the oscillator was evaluated through the ADS oscillator probe. The result of the loop gain magnitude and phase are shown in Fig. 2(a) and Fig 2(b). The EM simulation result indicates that the oscillator will oscillate at 4.4 GHz. From past experience, the simulation tends to under-estimate the frequency, thus we design our oscillator to operate at this frequency on purpose so that the measured oscillation can be around 5 GHz S11 (a)

8 IET-MAP 8 Phase of S Phase Magnitude Magnitude of S Frequency (GHz) 0.6 (b) Fig. 2 The simulated S-parameter seen from the oscillator port at gate in (a) polar plot, (b) rectangle plot B. Oscillator Design with Low Phase Noise As discussed in [19, 20], the waveform from large-signal simulation is required for accurate phase noise calculation. To predict the exact waveforms of a nonlinear circuit, transient simulations are normally used. However, such nonlinear analysis often has convergence issues and is not time-efficient. Thus, harmonic balance (HB) simulation with fast Fourier transform (FFT) transformation back to the time-domain signal has been widely adopted as a method to see the time-domain waveform [4, 13, 14, 19, 20]. The accuracy of such method strongly depends on the order of harmonics that are included in the simulation. It is worthy to mention that the recently published work in [13] demonstrated a novel method, which uses linear time variant (LTV) theory with HB simulation to accurately calculate the phase noise of the oscillator. However, it is also verified in [13] that for high power operation, there is a large difference between extrinsic load line and intrinsic load line. Hence the current level shows significant difference due to the extrinsic current containing high resonance current passing through the transistor parasitic capacitance. As a result, it is important to use the intrinsic current passing through the transistor only in order to exclude the non-noise generating current passing through the parasitic. Unfortunately, this step requires access to the intrinsic transistor model that is usually not available in the encrypted model from a commercial PDK.

9 IET-MAP 9 In order to achieve low phase noise, instead of quantitatively calculate the device parameters, several design considerations must be taken into account qualitatively. According to Leeson's phase noise equation, a singlesideband phase noise spectrum can be qualitatively described as [21], ( )= 10log (5) where Ql is the quality factor of the resonator, Psig is the oscillation power, F is the effective noise factor of the amplifier, k is Boltzmann's constant, T is absolute temperature in Kelvin, is the output frequency, is the offset frequency from the output frequency, is the flicker noise corner frequency, which is the transition point between 20 db/decade and 30 db/decade roll-off. From (6), the effect of increasing Q for improving phase noise is evident. Any doubling of Q will theoretically result in a 6 db improvement in phase noise at a given offset frequency. Several papers have investigated how to improve Q for integrated inductors, particularly for silicon where substrate loss degrades Q significantly. For III V technologies, the substrate is essentially lossless and the Q factor is limited primarily by metal loss. For an oscillator with integrated resonant tank, the Q factor is typically less than 30 in the frequency range of 5 10 GHz [1, 3, 6, 12]. In contrast, the simulated integrated inductor offers the Q as high as more than 40 around 5 GHz. Inductance (nh) Inductance Q factor Frequency (GHz) Q Fig. 3 The simulated Q and inductance of a typical integrated inductor in CREE's 0.25µm -on-sic technology

10 IET-MAP 10 Once the Q of passive components has been optimized at the interested frequency band, then the device size should be considered. As can be seen from (6), a relatively large device size is suitable due to the following reasons. First of all, large device geometry can suppress low frequency noise (LFN). Secondly, if all other influences could be considered constant, the larger the device means the larger the signal amplitude. The larger signal amplitude increases the signal to noise ratio and reduces the phase noise. Thirdly, a larger device also means a larger transconductance. The larger transconductance helps to maximize the loop gain. If the phase shift of the loop is designed to have a large derivative at the center of the resonance frequency, the ability of the resonator to attenuate the phase noise will be maximized. Moreover, larger Cgs helps to reduce the high frequency noise. In short, larger device geometry helps to improve phase noise. On the other hand, due to the absence of mature flicker noise model for the, impulse sensitivity function (ISF) simulation is performed during the design stage so that a good indication of the noise performance can be qualitatively predicted, regardless of the flicker noise model. This simulation also helps to determine the suitable device size. The term, ISF, can be used to indicate the phase noise level. It can be seen from Fig. 4 that larger device can provide better phase noise at the selected gate bias, VGS. However, a larger transistor has a larger parasitic capacitance, Cgd. As previously derived in (2), larger Cgd will lead to lower oscillating frequency. A larger transistor also means a larger die size and thus higher cost. Therefore, there are design trade-offs between output power, phase noise and oscillation frequency. In this design, a four-finger device with finger-width of 200 µm and length of 0.25 µm was chosen to obtain a gm = 70 ms to satisfy the start-up condition with reasonable margin. Finally, different drain and gate bias also affect the phase noise, which will be further studied in the later sections.

11 IET-MAP 11 ISF ISF g m g m (ms) Size (um) 55 Fig. 4 The simulated ISF against different device size IV. THE MEASUREMENT RESULTS AND DISCUSSIONS To verify the functionality of the designed oscillator and further investigate the impact of gate and drain bias variations on phase noise, the implemented oscillator is fabricated in Cree's 0.25µm -on-sic HMET technology. The measurements were performed on a test fixture, which is shown in Fig. 5. As illustrated, offchip RF chokes are realized using TLs, and a surface-mount DC-block capacitor is used. Those unlabeled components are either AC bypass capacitors for stabilizing the DC, or zero-ohm resistors for connection only. The die was attached to the PCB using epoxy, and then the PCB is attached to the heat sink. The substrate of the PCB is Rogers Both the power spectrum and phase noise were measured using an Agilent E4407B spectrum analyzer. Fig. 5 The photograph of the designed oscillator in test fixture

12 IET-MAP 12 To investigate the effect of varying drain bias on the phase noise of the designed oscillator, the gate bias is fixed at -3 V and the drain bias is changed from 2 V to 16 V. As seen from Fig. 6, the measured phase noise of the designed oscillator varies from -132 dbc/hz to -143 dbc/hz at an offset frequency of 1 MHz and from -100 dbc/hz to -112 dbc/hz at an offset frequency of 100 khz. As illustrated in Fig. 6, by varying VDS, U- shaped phase noise plots are shown which agrees with the ratio between the output voltage swing vout and the drain current IDS shown in Fig. 7. This indicates a transition from the voltage limited region to the current limited region, the best phase noise should and indeed appear around this region. The ISF is also simulated and plotted together in Fig. 7. As mentioned in [19, 20], larger ISF indicates worse phase noise. Moreover, Leeson s equation in (5) also gives the same conclusion that lower drain bias and thus lower output power should correspond to worse phase noise. However, a conflicting result is shown in Fig. 6 and Fig. 7, which indicates that the ISF derived from the -on-sic model does not predict the trend of phase noise while VDS is varied. It is noted that the similar phenomenon in terms of phase noise variation against different VDS is also observed in [4]. The measured output power and oscillation frequency of the designed oscillator are shown in Fig. 8. The oscillation frequency is changed from 5.05 GHz to 5.12 GHz while VDS is tuned from 2 V to 16 V. Meanwhile, the output power is varied from 6 dbm to 26 dbm Phase Noise (dbc/hz) MHz V DS (V) Fig. 6 Measured phase VGS = -3 V at the offset frequency of 100 khz and 1 MHz

13 IET-MAP 13 ISF ISF v out / I DS v out / I DS (V/A) V DS (V) Fig. 7 The simulated ISF and measured VGS = -3 V Frequency (GHz) Frequency Output Power Output Power (dbm) V DS (V) Fig. 8 Measured frequency and output power of the designed VGS = -3 V On the other hand, the measured phase noise of the designed oscillator against different gate bias is also investigated. As seen from Fig. 6 that utilizing an appropriate drain bias helps to reduce the phase noise of the oscillator. The drain bias for the best phase noise to appear is between 3 and 4 V. Thus, a commonly used drain bias of 3.3 V is chosen in the following analysis. The measured phase noise against the swept gate bias, with a fixed drain bias of 3.3 V, is illustrated in Fig. 9. As shown in Fig. 9, the oscillator gives the lowest phase noise at both the 100 khz and 1 MHz offset frequency while the gate bias is at -2.3 V. To investigate the measured results qualitatively, the simulation results of ISF vs. gate bias is plotted in Fig. 10. The measured oscillation frequency and output power of the designed oscillator are plotted in Fig. 11. As can be seen from Fig. 10, the lowest ISF value is also at a gate bias of -2.3 V. Therefore, it is noted

14 IET-MAP 14 that the phase noise of the designed oscillator against different gate bias can be predicted well by ISF while the drain bias is fixed. Furthermore, as shown in Fig. 11 that the oscillation frequency varies from 5.05 GHz to 4.95 GHz and the output power varies from 9 dbm to 14 dbm while the gate bias is varied from -3 V to - 2 V. The change in terms of oscillation frequency is slightly larger compared to the case when drain bias is varied, and this gives a clue that the parasitic capacitance between the gate and drain of the transistor, Cgd, is more sensitive to the gate bias. The measured spectrum is shown in Fig. 12. As illustrated that the oscillation frequency is around GHz with 30 db second harmonic suppression. The output power is around 26 dbm (after taken into account of the 1.6 db loss of the cable). Furthermore, the measured phase noise of the designed oscillator at different bias conditions are plotted in Fig. 13. In Fig. 13(a), it shows that the phase noise is -100 dbc/hz and -132 dbc/hz at an offset frequency of 100 khz and 1 MHz respectively from at GHz. Fig. 13(b) shows that the phase noise is -112 dbc/hz and -143 dbc/hz at an offset frequency of 100 khz and 1 MHz respectively from a GHz carrier Phase Noise (dbc/hz) V GS Fig. 9 Measured phase VDS = 3.3 V at the offset frequency of 100 khz and 1 MHz

15 IET-MAP ISF V GS (V) Fig. 10 The simulated VDS = 3.3 V Frequency (GHz) Frequency Output Power V GS (V) Output Power (dbm) Fig. 11 Measured frequency and output power of the designed VDS = 3.3 V Some key factors of the designed oscillator are summarized in Table II. As can be seen from Table II that the higher is the drain bias, the higher is the output power delivered. However, the phase noise performance deteriorates as higher drain bias is chosen. Therefore, there is a design trade-off between maximum achieved output power and minimum achieved phase noise.

16 IET-MAP 16 Fig. 12 Measured power spectrum of the designed VDS = 16 V and VGS = -3 V with second harmonic suppression (a) (b) Fig. 13 Measured phase noise of the designed (a) VGS = -3 V and VDS = 16 V and (b) VGS = -2.3 V and VDS = 3.3 V TABLE II THE SUMMARY OF THE DESIGNED OSCILLATOR AT 16 V AND 3.3 V DRAIN BIAS

17 IET-MAP 17 Supply Voltage (V) DC Power (W) Output Power (dbm) Oscillation Freq. (GHz) Phase 100kHz (dbc/hz) Phase 1MHz (dbc/hz) V. CONCLUSIONS A monolithic oscillator is designed in a commercial 0.25µm -on-sic technology and then utilized as a vehicle for the investigation of trade-off between phase noise and output power with the different drain and gate bias. In contrast, most of the previously published works mainly focused on a fixed drain bias. To qualitatively understand such effects on the phase noise, both Leeson's equation and ISF are utilized to compare the simulated and measured results. With a fixed drain bias, both Leeson's equation and ISF can correctly predict the trend of the phase noise vs. gate bias. However, neither ISF simulation nor Leeson's equation can provide a good prediction on phase noise while a swept drain bias is applied. The measured phase noise at VGS = -3 V and VDS = 16 V is -100 dbc/hz and -132 dbc/hz at 100 khz offset and 1 MHz offset respectively from GHz carrier. Moreover, it delivers a 26 dbm output power with 30 db second harmonic suppression. The phase noise at VGS = -2.3 V and VDS = 3.3 V is also measured to be -112 dbc/hz and -143 dbc/hz at 100 khz offset and 1 MHz offset from GHz carrier, while the output power is more than 14 dbm. It can be concluded that this work has successfully demonstrated that the oscillator can provide low phase noise and medium output power simultaneously. In addition, if accurate models for medium or low drain bias can be developed, the phase noise of oscillator should be further improved and well predicted in simulation. REFERENCES [1] H. Zirath, R. Kozhuharov, and M. Ferndahl, "Balanced Colpitt-oscillator MMICs designed for ultra-low phase noise," IEEE J. Solid-State Circuits, vol. 40, no. 10, p , Oct [2] P. Rice, R. Sloan, M. Moore, A. R. Barnes, M. J. Uren, N. Malbert and N. Labat,"A 10 GHz dielectric resonator oscillator using technolgy," in Proc. IEEE Microw. Theory Tech. Symp., pp , Jun

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