MC14513B. BCD To Seven Segment Latch/Decoder/Driver
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1 BCDToSeven Segment Latch/Decoder/Driver CMOS MSI (LowPower Complementary MOS) The MC453B BCDtoseven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functio of a 4bit storage latch, an 842 BCDtoseven segment decoder, and has output drive capability. Lamp test (LT), blanking (BI), and latch enable (LE) inputs are used to test the display, to turnoff or pulse modulate the brightness of the display, and to store a BCD code, respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output (RBO) can be used to suppress either leading or trailing zeroes. It can be used with seveegment light emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly. Applicatio include itrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. Features Low Logic Circuit Power Dissipation HighCurrent Sourcing Outputs (Up to 25 ma) Latch Storage of Binary Input Blanking Input Lamp Test Provision Readout Blanking on all Illegal Input Combinatio Lamp Inteity Modulation Capability Time Share (Multiplexing) Capability Adds Ripple Blanking In, Ripple Blanking Out to MC45B Supply Voltage Range = 3. V to 8 V Capable of Driving Two LowPower TTL Loads, One LowPower Schottky TTL Load to Two HTL Loads Over the Rated Temperature Range PbFree Package is Available* MAXIMUM RATINGS (Voltages Referenced to V SS ) Parameter Value DC Supply Voltage Range.5 to +8. V Input Voltage Range, All Inputs V in.5 to +.5 V DC Current Drain per Input Pin I ma Power Dissipation per Package (Note ) P D 5 mw Operating Temperature Range T A 55 to +25 C Storage Temperature Range T stg 65 to + C Maximum Continuous Output Drive Current (Source) per Output I OHmax 25 ma Maximum Continuous Output Power P OHmax 5 mw (Source) per Output (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability.. Temperature Derating: Plastic P and D/DW Packages: 7. mw/ C From 65 C To 25 C 2. P OHmax = I OH ( V OH ) 8 A WL YY WW G MARKING DIAGRAM MC453BCP AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package PDIP8 P SUFFIX CASE 77 ORDERING INFORMATION Device Package Shipping MC453BCP PDIP8 2 s/rail MC453BCPG PDIP8 (PbFree) 2 s/rail This device contai protection circuitry to protect the inputs agait damage due to high static voltages or electric fields. However, it is advised that normal precautio be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. A destructive high current mode may occur if V in and V out are not cotrained to the range V SS (V in or V out ). Due to the sourcing capability of this circuit, damage can occur to the device if is applied, and the outputs are shorted to V SS and are at a logical (See Maximum Ratings). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or ). *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 26 Publication Order Number: MC453B/D
2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) Output Voltage Segment Outputs Level V in = or V in = or Level Output Voltage RBO Output Level V in = or V in = or Level Input Voltage (Note 3) Level (V O = 3.8 or.5 ) (V O = 8.8 or. ) (V O = 3.8 or.5 ) (V O =.5 or 3.8 ) Level (V O =. or 8.8 ) (V O =.5 or 3.8 ) Output Drive Voltage Segments (I OH = ma) Source (I OH = ma) (I OH = ma) (I OH = ma) (I OH = 2 ma) (I OH = ma) (I OH = ma) (I OH = ma) (I OH = ma) (I OH = 2 ma) (I OH = ma) (I OH = ma) (I OH = ma) (I OH = ma) (I OH = 2 ma) V OH V OH V IL V IH 55 C 25 C 25 C Min Max Min 7. OH Noise immunity specified for worstcase input combination. Noise Margin for both and level =. = 2. = 2.5 = Typ (Note 3) Max Min Max
3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (continued) (Voltages Referenced to V SS ) 55 C 25 C 25 C Min Max Min Typ (Note 4) Max Min Max Output Drive Current RBO Output (V OH = 2.5 V) Source (V OH = 9.5 V) (V OH = V) ( =.4 V) Sink ( =.5 V) ( =.5 V) I OH I OL Output Drive Current Segments ( =.4 V) Sink ( =.5 V) ( =.5 V) I OL Input Current I in ±. ±. ±. ±. Adc Input Capacitance C in 7.5 pf Quiescent Current (Per Package) V in = or, I out = A I DD Adc Total Supply Current (Note 5, 6) (Dynamic plus Quiescent, Per Package) (C L = 5 pf on all outputs, all buffers switching) I T I T = (.9 A/kHz) f + I DD I T = (3.8 A/kHz) f + I DD I T = (5.7 A/kHz) f + I DD 4. Noise immunity specified for worstcase input combination. Noise Margin for both and level =. = 2. = 2.5 = 5. The formulas given are for the typical characteristics only at 25 C. 6. To calculate total supply current at loads other than 5 pf: I T (C L ) = I T (5 pf) + x 3 (C L 5) f where: I T is in A (per package), C L in pf, in, and f in khz is input frequency. Adc Input LE and RBI low, and Inputs D, BI and LT high. f in respect to a system clock. All outputs connected to respective C L loads % A, B, AND C 5% % 2f 5% DUTY CYCLE ANY OUTPUT 5% V SS V OH Figure. Dynamic Power Dissipation Signal Waveforms 4
4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 7) (C L = 5 pf, T A = 25 C) TLH TLH Output Fall Time Segment Outputs (Note 7) t THL = (.5 /pf) C L + 5 t THL = (.75 /pf) C L t THL = (.55 /pf) C L Output Fall Time RBO Outputs t THL = (3.25 /pf) C L t THL = (.35 /pf) C L t THL = (.95 /pf) C L Propagation Delay Time A, B, C, D Inputs (Note 7) = (.4 /pf) C L + 62 = (.25 /pf) C L = (.2 /pf) C L + 65 t PHL = (.3 /pf) C L t PHL = (.6 /pf) C L + 26 t PHL = (.35 /pf) C L Propagation Delay Time RBI and BI Inputs (Note 7) = (.5 /pf) C L = (.45 /pf) C L = (.3 /pf) C L + 35 t PHL = (.85 /pf) C L t PHL = (.45 /pf) C L t PHL = (.35 /pf) C L Propagation Delay Time LT Input (Note 7) = (.45 /pf) C L = (.25 /pf) C L = (.2 /pf) C L + 8 t PHL = (.3 /pf) C L t PHL = (.45 /pf) C L t PHL = (.35 /pf) C L t THL t THL t PHL t PHL t PHL Setup Time t su Hold Time t h Latch Enable Pulse Width t WL(LE) 7. The formulas given are for the typical characteristics only. All Types Min Typ Max
5 PACKAGE DIMENSIONS PDIP8 CASE 772 ISSUE D 8 9 B L J NOTES:. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN.25 mm (.) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. CONTROLLING DIMENSION: INCH. H F G A D N C SEATING PLANE K M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G. BSC 2.54 BSC H J K L.3 BSC 7.62 BSC M N MC453B/D
PIN ASSIGNMENT B 1 18 C 2 17 f LT 3 16 g BI 4 a LE 5 14 b D 6 13 c A 7 12 d RBI e RBO e f d g a c b DISPLAY TRUTH TABLE Input
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QUAD D-TYPE FLIP FLOP WITH CLEAR HIGH SPEED : t PD = 16 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT
M74HC259TTR 8 BIT ADDRESSABLE LATCH
8 BIT ADDRESSABLE LATCH HIGH SPEED : t PD = 20 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
M74HC273TTR OCTAL D TYPE FLIP FLOP WITH CLEAR
OCTAL D TYPE FLIP FLOP WITH CLEAR HIGH SPEED : f MAX = 66 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT
Obsolete Product(s) - Obsolete Product(s)
OCTAL D TYPE FLIP FLOP HIGH SPEED : f MAX = 66 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
Phase-Locked Loop High-Performance Silicon-Gate CMOS
TECHNICAL DATA Phase-Locked Loop High-Performance Silicon-Gate CMOS The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC4046A
Obsolete Product(s) - Obsolete Product(s)
DUAL MONOSTABLE MULTIVIBRATOR RETRIGGERABLE/RESETTABLE CAPABILITY TRIGGER AND RESET PROPAGATION DELAYS INDEPENDENT OF R X, C X TRIGGERING FROM LEADING OR TRAILING EDGE Q AND Q BUFFERED OUTPUT AVAILABLE
HCF4538B DUAL MONOSTABLE MULTIVIBRATOR
DUAL MONOSTABLE MULTIVIBRATOR RETRIGGERABLE/RESETTABLE CAPABILITY TRIGGER AND RESET PROPAGATION DELAYS INDEPENDENT OF R X, C X TRIGGERING FROM LEADING OR TRAILING EDGE Q AND Q BUFFERED OUTPUT AVAILABLE
M74HC690TTR DECADE COUNTER/REGISTER (3-STATE)
DECADE COUNTER/REGISTER (3-STATE) HIGH SPEED: f MAX = 53 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT
M74HC160TTR SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER HIGH SPEED : f MAX = 62 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
Obsolete Product(s) - Obsolete Product(s)
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER HIGH SPEED : f MAX = 62 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
TC74HC273AP,TC74HC273AF,TC74HC273AFW
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC273AP/AF/AFW TC74HC273AP,TC74HC273AF,TC74HC273AFW Octal D-Type Flip Flop with Clear The TC74HC273A is a high speed CMOS OCTAL D-TYPE FLIP
HCF4017B DECADE COUNTER WITH 10 DECODED OUTPUTS
DECADE COUNTER WITH 10 DECODED OUTPUTS MEDIUM SPEED OPERATION : 10 MHz (Typ.) at V DD = 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V
Quad 2-Input Data Selectors/Multiplexer
TECNICAL DATA IN74C157A Quad 2-Input Data Selectors/Multiplexer The IN74C157A is identical in pin out to the LS/ALS157. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
Obsolete Product(s) - Obsolete Product(s)
DUAL BINARY UP COUNTER MEDIUM SPEED OPERATION : 6MHz (Typ.) at 10V POSITIVE -OR NEGATIVE- EDGE TRIGGERING SYNCHRONOUS INTERNAL CARRY PROPAGATION QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC
DS DS Series Dual Peripheral Drivers
DS55451 2 3 4 DS75451 2 3 4 Series Dual Peripheral Drivers General Description Features Y The DS7545X series of dual peripheral drivers is a family of versatile devices designed for use in systems that
Quad 2-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C257A Quad 2-Input Data Selector/Multiplexer with 3-State Outputs igh-performance Silicon-ate CMOS The IN74C257A is identical in pinout to the LS/ALS257. The device inputs are compatible
Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS
TECNICA DATA IW029B Presettable Up/Down Counter igh-voltage Silicon-Gate CMOS The IW029B coists of a four-stage binary or BCD-decade up/down counter with provisio for look-ahead carry in both counting
Obsolete Product(s) - Obsolete Product(s)
HEX BUFFER/CONVERTER (INVERTING) PROPAGATION DELAY TIME t PD = 40ns (TYP.) at V DD = 10V C L = 50pF HIGH TO LOW LEVEL LOGIC CONVERSION MULTIPLEXER: 1 TO 6 OR 6 TO 1 HIGH "SINK" AND "SOURCE" CURRENT CAPABILITY
HCF4585B 4-BIT MAGNITUDE COMPARATOR
4-BIT MAGNITUDE COMPARATOR EXPANSION TO 8, 12, 16...4 N BITS BY CASCADING UNIT MEDIUM SPEED OPERATION : COMPARES TWO 4-BIT WORDS IN 180ns (Typ.) at 10V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT
Obsolete Product(s) - Obsolete Product(s)
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING HIGH SPEED: t PD = 13 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.)
M74HC595TTR 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE) HIGH SPEED: f MAX = 59MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.)
CD74HC73, CD74HCT73. Dual J-K Flip-Flop with Reset Negative-Edge Trigger. Features. Description. Ordering Information. Pinout
Data sheet acquired from Harris Semiconductor SCHS134 February 1998 CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject Dual -K liplop Features
MM Liquid Crystal Display Driver
Liquid Crystal Display Driver General Description The MM145453 is a monolithic integrated circuit utilizing CMOS metal gate, low threshold enhancement mode devices. The chip can drive up to 33 LCD segments
Obsolete Product(s) - Obsolete Product(s)
HEX BUS BUFFER WITH 3 STATE OUTPUT INVERTING HIGH SPEED: t PD = 9 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
HCF4020B RIPPLE-CARRY BINARY COUNTER/DIVIDERS 14 STAGE
RIPPLE-CARRY BINARY COUNTER/DIVIDERS 14 STAGE MEDIUM SPEED OPERATION: 16MHz (Typ.) at V DD = 10V FULLY STATIC OPERATION COMMON RESET BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS
TECHNICAL DATA Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS IN74AC193 The IN74AC193 is identical in pinout to the LS/ALS193, HC/HCT193. The device inputs are compatible with standard
TC74HC175AP,TC74HC175AF,TC74HC175AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC175AP/AF/AFN TC74HC175AP,TC74HC175AF,TC74HC175AFN Quad D-Type Flip Flop with Clear The TC74HC175A is a high speed CMOS D-TYPE FLIP FLOP
Obsolete Product(s) - Obsolete Product(s)
QUAD 2 INPUT NAND GATE PROPAGATION DELAY TIME t PD = 60ns (Typ.) at V DD = 10V BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V
M74HC563TTR OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING HIGH SPEED: t PD = 13 (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL