DIGITAL COMMUNICATIONS

Transcription

1 DIGITAL COMMUNICATIONS LAB MANUAL (STUDENT COPY) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING GUDLAVALLERU ENGINEERING COLLEGE SESHADRI RAO KNOWLEDGE VILLAGE::GUDLAVALLERU

2 INDEX S.NO. NAME OF THE EXPERIMENT PAGE NO. 1 Time Division Multiplexing Pulse Code Modulation & Demodulation Differential Pulse Code Modulation & Demodulation Delta Modulation Frequency Shift Keying Phase Shift Keying Differential phase shift keying Companding Linear Block Code- Encoder and Decoder Binary Cyclic Code- Encoder and Decoder ADDITIONAL EXPERIMENTS 1 Amplitude Shift Keying Time Division Multiplexing & De multiplexing (Digital) MATLAB Program for ASK Modulation & Demodulation MATLAB Program for PSK Modulation & Demodulation MATLAB Program for FSK Modulation & Demodulation MATLAB Program for QPSK Modulation & Demodulation APPENDIX REFERENCES 73

3 Digital Communication Lab

4 Additional Experiments

5 APPENDIX

6 1. TIME DIVISION MULTIPLEXING AND DEMULTIPLEXING Aim: 1. To study the 4 channel analog multiplexing and demultiplexing 2. To study the effect of sampling frequency on output signal characteristics. 3. To study the effect of input signal amplitude on the output signal characteristics. Apparatus required: 1. Time Division Multiplexing and de multiplexing trainer Kit. 2. Dual Trace oscilloscope Theory: In PAM, PPM the pulse is present for a short duration and for most of the time between the two pulses no signal is present. This free space between the pulses can be occupied by pulses from other channels. This is known as Time Division Multiplexing. Thus, time division multiplexing makes maximum utilization of the transmission channel. Each channel to be transmitted is passed through the low pass filter. The outputs of the low pass filters are connected to the rotating sampling switch (or) commutator. It takes the sample from each channel per revolution and rotates at the rate of f s. Thus the sampling frequency becomes f s the single signal composed due to multiplexing of input channels. These channels signals are then passed through low pass reconstruction filters. If the highest signal frequency present in all the channels is f m, then by sampling theorem, the sampling frequency f s must be such that f s 2f m. Therefore, the time space between successive samples from any one input will be T s =1/f s, and T s 1/2f m. 1

7 Circuit Diagram: Procedure: Fig: 1 Time Division Multiplexing And Demultiplexing Circuit There are 4 signal sources; a) AF Signal generator b) Triangular wave generator c) Square wave generator and d) Sine wave generator 1. Connect these four signals to four inputs of the Multiplexer. Adjust each signal amplitude to be with in +/-2V (p-p) and frequency non-over lapping within a frequency band of 300Hz. 2. Connect A, B output of 7476 to A 1, B l inputs of Multiplexer. 3. Adjust the frequency of IC 8038 (Square wave, triangular wave generator) to be around 32 KHz, so that each of the Four channels are sampled at 8 KHz. 4. Adjust the pulse width of 555 timers to be around 10µsecs. 5. Observe the 4 output pin 11 of 7476 on one channel 1and TDM output pin 13 of CD4052 on second channel of oscilloscope. Synchronize scope Internal-CH 1 mode. All the multiplexed channels are observed during the full period of the clock (1/32 KHz). 6. Connect TDM output to comparator ve input and saw tooth wave to +ve Input. Observe the Comparator output. The PAM pulses are now converted in to PWM pulses. 2

8 7. Connect the PWM pulses to TDM input of De multiplexer at pin 3 of second CD4052. Observe the individual outputs Y0, Y1, Y2, and Y3 at pin 1, 5, 2 & 4 of CD4052 respectively. The PWM pulses corresponding to each channels are now separated as 4 streams. 8. Take one output and connect it to Low Pass Filter and the Low Pass Filter output to Amplifier. Observe the output of the amplifier in conjunction with the corresponding input. Repeat this for all 4 inputs. This is the Demodulated TDM output. Any slight variation in frequency, amplitude is reflected in the corresponding output. Observations: S.No Type of Signal 1 AF signal 2 Sine wave 3 Square wave 4 Triangular wave Input Signal Amplitude Time period (V p-p ) (ms) Multiplexed output Time No. of Slot(ms) cycles Model Waveform: Multiplexed Output Waveform Inference: 3

9 Questions: 1. What is TDM? 2. Applications of TDM? 3. What is the effect of amplitude and frequency of input signals on output? 4

10 2. PULSE CODE MODULATION AND DE MODULATION Aim: To obtain the pulse code modulation and de modulation signals. Apparatus required: Theory: 1. PCM trainer kit 2. Dual Trace Oscilloscope. Pulse Code Modulation is known as digital pulse modulation technique. In fact, the pulse code modulation technique that the message signal is subjected to a great number of operations. It consists of 3 main parts i.e., transmitter, transmission path and receiver. The essential operations in the transmitter of a PCM system are sampling, quantizing and encoding. Sampling is the operation in which an analog signal is sampled according to the sampling theorem resulting in a discrete time signal. The quantizing and encoding operations are usually performed in the same circuit which is known as an ADC. Also, the essential operations in the receiver are regeneration of impaired signals, decoding and demodulation of the train of quantized samples. These operations are usually performed in the same circuit which is known as digital to analog converter. Further at intermediate points along the transmission route from the transmitter to the receiver, regenerative repeaters are used to reconstruct the transmitted sequence of coded pulses in order to combat the accumulated effects of signal distortion and noise. The quantization refers to the use of a finite set of amplitude levels and the selection of a level nearest to a particular sample value of the message signal as the representation the system at transmission in which sampled and quantized values of an analog signal are transmitted via a sequence of code words is called Pulse Code Modulation. Two most commonly used versions are the differential pulse code modulation and delta modulation. The PCM communication system is shown in Fig1. In the circuit is often called an analog to digital converter. The functional block that performs the task of accepting binary digits and generating appropriate sequences of levels is called a digital to analog converter. The bandwidth of PCM will be much greater than that of the message. PCM is used to convert analog signals to binary form. Low pass 5

11 filter may be used to reduce the quantization noise and it yields the original message signal. Circuit Diagram: Fig: 1 Pulse Code Modulation and Demodulation Circuit Procedure: 1. Make the connections as per the diagram as shown in the Fig.1.and switch on the power supply of the trainer kit. 2. Clock generator generates a 20 KHz clock.this can be given as input to the timing and control circuit and observe the sampling frequency f s = 2 KHz approximately at the output of timing and control circuit. 3. Apply the signal generator output of 6V (p-p) approximately to the A to D converter input and note down the binary word from LED s i.e. LED ON represents 1 & OFF represents 0 4. Feed the PCM waveform to the demodulator circuit and observe the waveform at the output of D/A which is quantized level. 6

12 Model Waveforms: (a) (b) (c) Fig: 2 Waveforms of (a) Modulating Signal (b) Sampling Signal (c) PCM output 7

13 Apply the DC control voltage DC voltage(v) -4-3 MSB Bit sequence LSB Questions: 1. What is the need of parallel to serial converter? 2. What is the use of Companding? 3. What are the applications of PCM? 8

14 3. DIFFERENTIAL PULSE CODE MODULATION AND DEMODULATION Aim: To study the differential PCM & demodulation by sending variable frequency sine wave & variable DC signal input. Apparatus required: Theory: 1. AF oscillator 2. DPCM modulator 3. DPCM demodulator 4. Connecting wires 5. CRO - 30MHz 6. Variable DC Source 1 In this DPCM instead of transmitting a base band signal m(t) we send the difference signal of K th sample and (k-1) th sample value. The advantage here is fewer levels are required to quantize the difference than the required to quantize m(t) and correspondingly, fewer bits will be needed to encode the levels. If we know the post behaviour of a signal up to a certain time, it is possible to make some interference about its future values this is called prediction. The filter designed to perform the prediction is called a predictor. The difference between the interest and the predictor o/p is called the prediction error. Circuit Diagram: Fig:1 Differential Pulse Code Modulation Circuit 9

15 Fig: 2 Differential Pulse Code Demodulation Circuit Procedure: 1. Switch on the experimental kit. 2. Apply the variable DC signal of amplitude 6v(p-p) with frequency of 80Hz to the input terminals of DPCM modulator. 3. Observe the sampling signal of amplitude 5v (p-p) with frequency 20KHz on channel 1 of a CRO. 4. Observe the output of DPCM on the second channel. 5. By adjusting the DC voltage potentiometer, observe the DPCM output. 6. During the demodulation connect DPCM output to the input of demodulator and observe the output of DPCM demodulator. Model waveforms: (a) 10

16 (b) Fig: 3 Waveforms of (a) Sampling Signal (b) Modulating Signal (c) DPCM Output (c) (a) 11

17 - (b) Fig. 4 Output of (a) D/A Converter (b) Demodulated Inference: Questions: 1. What is the effect sampling signal? 2. Write the advantage of DPCM compared with PCM? 3. What is the one bit version of DPCM? 12

18 Aim: 4. DELTA MODULATION To obtain the delta modulation and demodulation signals. Apparatus required: Theory: 1. Delta Modulation & Demodulation Kit 2. Cathode Ray Oscilloscope 0-30MHz Delta modulation uses a single bit PCM code to achieve digital transmission of analog signals with conventional PCM each code is binary representation of both the sign and magnitude of a particular sample. With delta modulation, rather than transmit a coded representation of the sample, only a single bit is transmitted, which indicates whether that sample is larger or smaller than the previous sample. The algorithm for a delta modulation system is quite simple. If the current sample is smaller than the previous sample, a logic 0 is transmitted. If the current sample is larger than the previous sample, a logic 1 is transmitted. The input analog is sampled and converted to a PAM signal, which is compared to the output of the DAC. The output of the DAC is a voltage equal to the regenerated magnitude of the previous sample, which was stored in the up/down counter as a binary number, The up/down counter is incremented or decremented depending on whether the previous sample is larger or smaller than the current sample. The up/down counter is clocked at a rate equal to the sample rate. Therefore, the up/down counter is updated after each comparison. Block Diagram: Fig: 1 Delta Modulation Circuit 13

19 Procedure: Fig: 2 Delta Demodulation Circuit 1. Switch on the experimental board. 2. Connect the clock signal of frequency of 10KHz,with amplitude of 5v(p-p) to the delta modulator circuit. 3. Connect the modulating signal of amplitude 5v(p-p) and frequency of of 0.2KHz modulating input of the delta modulator And observe the same on channel 1 of a Dual Trace oscilloscope. 4. Observe the Delta Modulator output on channel Connect this Delta modulator output to the Demodulator 6. Also connect the clock signal to the demodulator. 7. Observe the Demodulator output with and without RC filter on CRO. Model Waveforms: (a) 14

20 (b) (c) Fig: 3 Waveforms (a) Clock input (b) Delta modulation output & message signal (c) D/A converter output Inference: 15

21 Questions: 1. What is the slope overload effect? 2. What is granular noise? 3. Write the advantage of DM over PCM? 4. What is the effect of the Low Pass Filter cut off frequency on output of demodulator? 16

22 Aim: 5. FREQUENCY SHIFT KEYING To generate the waveforms of frequency shift keying Apparatus required: Name of the apparatus Specifications/Range Quantity Resistors 33kΩ 2 Capacitors 0.01µF, 100pF Each one Function Generator 0-1MHz 1 RPS 0-30V, 1A 1 CRO 0-30MHz 1 IC 8038 Supply voltage - ±18V or 36V Power dissipation 750mW 1 CRO Probes Theory: FSK signaling schemes find a wide range of applications in low-speed digital data transmission system. FSK schemes are not as efficient as PSK interms of power and bandwidth utilization. In binary FSK signaling the waveforms are used to convey binary digits 0 and 1 respectively. The binary FSK waveform is a continuous, phase constant envelope FM waveform. The FSK signal bandwidth in this case is of order of 2MHz, which is same as the order of the bandwidth of PSK signal. Circuit Diagram: Fig: 1 Frequency Shift Keying 17

23 Procedure: 1. Connect the circuit as shown in fig.1 2. Apply the (binary) Data input of amplitude 20V (p-p) with frequency of 6 KHz from function generator to pin no Give the power supply of 10v to the appropriate pins. 4. Observe the FSK output at pin no Now note down the mark and space frequencies for different carrier frequencies. 6. Calculate the maximum frequency deviation and modulation index. 7. Repeat the steps (5) and (6) for different pulse durations of binary input. Model Waveforms: (a) (b) 18

24 (c) Fig: 2 Waveforms of (a) Carrier wave (b) Data input (c) FSK Wave Inference: Questions: 1. Write the advantage of FSK compared to ASK? 2. What is the disadvantage of FSK compared with ASK & PSK? 3. What is the effect of R1, C2 values on the output? 19

25 Aim: 6. PHASE SHIFT KEYING To generate the waveforms of phase shift keying. Apparatus required: Name of the apparatus Specifications/Range Quantity Diodes(IN4007) Max Voltage:45V 4 Transformers 7V-0-7V 2 Function Generator 0-1MHz 2 CRO 0-30MHz 1 CRO Probes Theory: Circuit diagram of PSK as shown in Fig.1. The phase of carrier is shifted between two values is called Phase Shift Keying. The amplitude of carrier remains constant. Phase Shift Keying is also called Phase Reversal Keying. The performance of PSK is more than ASK. PSK is a non linear modulation. PSK needs a complicated. Synchronous circuit at the receiver. The bandwidth of PSK is 2f m. Circuit Diagram: Fig: 1 Phase Shift Keying Circuit 20

26 Procedure: 1. Switch on the experimental board. 2. Apply the carrier signal of amplitude7v (p-p) with frequency of 4 KHz to the modulator input and observe the signal on the channel of the CRO. 3. Apply the modulating signal of amplitude 6V (p-p) and frequency of 0.5 KHz to pin Observe the output of PSK modulator on the channel 2 of the CRO. Model Waveforms: (a) (b) 21

27 (c) Fig: 2 Waveforms of (a) Carrier signal (b) Modulating signal (c) PSK output Inference: Questions: 1. Drawback of DPSK compared to BPSK? 2. Write the advantage of BPSK over the BPSK? 3. What is the effect of carrier amplitude on the output? 4. What is the effect of modulating signal frequency on the output? 22

28 7. DIFFERENTIAL PHASE SHIFT KEYING MODULATION AND DEMODULATION Aim: To study the various steps involved in generating the differential phase shift keyed signal and the binary signal from the received DPSK signal Apparatus required: 1. DPSK trainer board 2. Cathode Ray Oscilloscope (0-30MHz) Theory: The differentially coherent PSK signaling scheme make use of a technique designed to get around the need for a coherent reference signal at the receiver. In the DPSK scheme, the phase reference for demodulation is derived from the phase of the carrier during the preceding signaling interval, and the receiver decodes the digital information based on the differential phase. Circuit Diagram: Fig: 1 Differential Phase Shift Keying Circuit 23

29 Procedure: 1. Switch on the experimental board. 2. Check the carrier signal and the data generator signals initially. 3. Apply the carrier signal of amplitude 6v (p-p) with frequency of1khz to the carrier input, the data input of amplitude 5v (p-p) with frequency of 600Hz to the data input and bit clock of amplitude 5v (p-p) with and frequency of 1 KHz to the DPSK modulator. 4. Observe the DPSK wave of amplitude 5.6v (p-p) and frequency of 1 KHz with respect to the input data generated signal of dual trace oscilloscope. 5. Give the output of the DPSK modulator signal to the input of demodulator, give the bit clock output to the bit clock input to the demodulator and also give the carrier output to the carrier input of demodulator. 6. Observe the demodulator output with respect to data generator signal. Model Waveforms: (a) (b) 24

30 (c) (d) (e) 25

31 Fig: 2 Waveforms of (a) Carrier signal (b) Bit clock (c) Data input (d) Differential data (e) DPSK wave Inference: Questions: 1. Write the advantage of DPSK? 2. What is the drawback of DPSK compared to PSK system? 3. What is the effect of carrier amplitude on the output of DPSK? 26

32 Aim: 8. COMPANDING 1. Study and analysis of µ-law Compressor and Decompressor. 2. Study and analysis of A-Law Compressor and Decompressor. Apparatus: 1. Companding Trainer Kit (Techbook ST2805) 2. Regulated Power Supply 3. Oscilloscope/DSO 4. Test probe Theory: Companding: In digital Companding, the analog signal is first sampled and converted to a linear PCM code and then the linear code is digitally compressed. In receiver, the compressed PCM code is expanded and then decoded (i.e., converted back to analog). The encoded representation of µ255 PCM code words use a signmagnitude format wherein 1 bit identifies the sample polarity and the remaining bits specify the magnitude of the sample. The 7 magnitude bits are conveniently partitioned into a 3-bit segment identifier (S) and 4-bit quantizating step identifier (Q). Thus, the basic structure of an 8-bit µ255 PCM codeword is shown in figure. Polarity bit (P) = 0 for positive sample values 1 for negative sample values Compressor: The compression process is as follows. The analog signal is sampled and converted to a linear 14-bit sign-magnitude code(1-bit(msb) as sign bit and other 13-bits as magnitude bits). The sign bit is transferred directly to an eight-bit compressed code. The segment number in the eight-bit code is determined by counting the number of leading 0s in the 13-bit magnitude portion of the linear 27

33 code beginning with the most significant bit. Subtract the number of leading 0s (not to exceed 7) from 7. The results the segment number, which is converted to a three-bit binary number and inserted into the eight-bit compressed code as the segment identifier. The four magnitude bits (a, b, c and d) represent the quantization interval (i.e., subsegments) and are substituted into the least significant four bits of the 8-bit compressed code. In the given table using only magnitude bits. µ-law Binary Encoding Table: Essentially, the expander guesses what the truncated bits were prior to compression. µ-law Binary Decoding Table: 28

34 A-Law Companding: A-law is the CCITT recommended companding standard used across Europe. Limiting sample values to 12 magnitude bits. In digital companding, the analog signal is first sampled and converted to a linear PCM code and then the linear code is digitally compressed. In receiver, the compressed PCM code is expanded and then decoded (i.e., converted back to analog). The eight-bit compressed code consists of a sign bit, a three-bit segment identifier, and a fourbit quantization interval. The compression process is as follows. The analog signal is sampled and converted to a linear 13-bit sign-magnitude code (1-bit (MSB) as sign bit and other 12-bits as magnitude bits). The sign bit is transferred directly to an eight-bit compressed code. The segment number in the eight-bit code is determined by counting the number of leading 0s in the 12-bit magnitude portion of the linear code beginning with the most significant bit. Subtract the number of leading 0s (not to exceed 7) from 7. The results the segment number, which is converted to a three-bit binary number and inserted into the eight-bit compressed code as the segment identifier. The four magnitude bits (a, b, c and d) represent the quantization interval (i.e., subsegments) and are substituted into the least significant four bits of the 8-bit compressed code. A-Law Binary Encoding Table: Essentially, the expander guesses what the truncated bits were prior to compression. 29

35 A-Law Binary Decoding Table: Block Diagrams: µ-law Companding 30

36 A-Law Companding Procedure (µ-law): Step 1: Connect and switch on the power supply of ST2805. Step 2: Select µ-law Companding using switch. Move switch towards right. Step3: Connect CN3 to CN1 or CN2 for input Selection. If CN3 connected to CN1 then internally generated Signal (Sine Wave) will be selected as input. If CN3 connected to CN2 then Dip input will be selected. So user can select input using DIP Switches. Step 4: User can match compressed output and decompressed output for respective input using given table. Observations: Observe the internally generated input signal at TP1. Observe the binary bits of selected input signal on led at 12 bit register linear code. Observe the sign bit of compressed output at TP2. Observe the binary bits of segment identifier of compressed output at TP3, TP4, and TP5. Observe the binary bits of Quantization interval of compressed output at TP6, TP7, TP8, and TP9. Observe the analog compressed output at TP10 and binary bits on led at compressed data. Observe the sign bit of decompressed output at TP11. 31

37 Observe the binary bits of segment identifier of decompressed output at TP12, TP13, and TP14. Observe the binary bits of Quantization interval of decompressed output at TP15, TP16, TP17, and TP18. Observe the analog decompressed output at TP19 and binary bits on led at Decompressed data. Table for verification of compressor and decompressor output wrt. Input selection using DIP switch. Model Waveforms: Real time output of µ-law Compressor and decompressor on DSO when sine wave is selected as input signal 32

38 CH1: Sine Wave as Input (TP1) CH2: Compressed Signal (TP10) CH1: Sine Wave as Input (TP1) CH2: Decompressed Signal (TP19) CH1: Compressed Signal (TP10) CH2: Decompressed Signal (TP19) Procedure (A-Law): Step 1: Connect and switch on the power supply of ST2805. Step 2: Select A-Law Companding using switch. Move switch towards left. Step 3: Connect CN3 to CN1 or CN2 for input Selection. If CN3 connected to CN1 then internally generated Signal (Sine Wave) will be selected as input. If CN3 connected to CN2 then Dip input will be selected. So user can select input using DIP Switches. Step 4: User can match compressed output and decompressed output for respective input using given table. 33

39 Observations: Observe the internally generated input signal at TP1. Observe the binary bits of selected input signal on led at 12 bit register linear code. Observe the sign bit of compressed output at TP20. Observe the binary bits of segment identifier of compressed output at TP21, TP22, and TP23. Observe the binary bits of Quantization interval of compressed output at TP24, TP25, TP26, and TP27. Observe the analog compressed output at TP28 and binary bits on led at compressed data. Observe the sign bit of decompressed output at TP29. Observe the binary bits of segment identifier of decompressed output at TP30, TP31, and TP32. Observe the binary bits of Quantization interval of decompressed output at TP33, TP34, TP35, and TP36. Observe the analog decompressed output at TP37 and binary bits on led at Decompressed data. Table for verification of compressor and decompressor output wrt input selection using DIP switch. 34

40 Model Waveforms: Real time output of A-Law Compressor and decompressor on DSO when sine wave is selected as input signal CH1: Sine Wave as Input (TP1) CH2: Compressed Signal (TP28) CH1: Sine Wave as Input (TP28) CH2: Decompressed Signal (TP37) CH1: Compressed Signal (TP1) CH2: Decompressed Signal (TP37) 35

41 9. LINEAR BLOCK CODE - ENCODER & DECODER Aim: To Study the Hamming Code 7-bit Generation. Apparatus: 1. Linear Block Code- Encoder & Decoder Trainer Kit (Scientech 2121A & 2121B) 2. 2 mm Banana Cable 3. Regulated Power Supply Theory: Error Detection and Correction: Error detection is the ability to detect the presence of errors caused by noise or other impairments during transmission from the transmitter to the receiver. Error correction is the additional ability to reconstruct the original, error-free data. There are two basic ways to design the channel code and protocol for an error correcting system. Linear block codes: Linear block codes are conceptually simple codes that are basically an extension of single-bit parity check codes for error detection. A single-bit parity check code is one of the most common forms of detecting transmission errors. This code uses one extra bit in a block of n data bits to indicate whether the number of 1s in a block is odd or even. Thus, if a single error occurs, either the parity bit is corrupted or the number of detected 1s in the information bit sequence will be different from the number used to compute the parity bit: in either case the parity bit will not correspond to the number of detected 1s in the information bit sequence, so the single error is detected. Linear block codes extend this notion by using a larger number of parity bits to either detect more than one error or correct for one or more errors. Unfortunately linear block codes, along with convolutional codes, trade their error detection or correction capability for either andwidth expansion or a lower data rate, as will be discussed in more detail below. We will estrict our attention to binary codes, where both the original information and the corresponding code consist of bits taking a value of either 0 or 1. 36

42 Block Diagram: Procedure: 1. Connect the power supply mains cord to the Scientech 2121A and Scientech 2121B but do not turn ON the power supply until connections are made for this experiment. 2. Keep default/manual switch in Manual mode. 3. There are some conditions regarding H-Matrix selection manually which are: a. Any row should not be identically selected like there should not all 1 s or all 0 s. b. Each row selection should be different from other row. c. The matrix should be so chosen that all the rows are distinct and consist of at least three 1 s in them. 4. Switch On the power supply and press reset button. 5. Check the clock pulse of 2 KHz on Oscilloscope at given test point. 6. At Scientech 2121A Block Code Encoder unit now select the data at seven Segment display with the help of BCD (binary coded decimal) switch. 7. Check the data at seven segment display and its binary equivalent (d3, d2, d1, d0), in the Code Word Generator block T where bit pattern is selected in the form of 8, 4, 2, 1 format. 8. Now set the H matrix are per the condition given in step 3. In Observation Table 3.1, some example sets are given (Set 1, Set2, Set3 and Set4). You can set your own matrix or you can choose any set from example sets and select the H Matrix as per the table. 37

43 9. After that check the H matrix in the form of H= [Ik] [P]; Identity matrix and Parity matrix corresponding to the selected set as given in the Observation Table Check the massage signal in the form of (d3, d2, d1, d0, p3, p2, p1) and verify the status of Parity Bits (p3, p2, p1) as per the equations given for parity generation (see bservation Table 3.1). 11. Connect 2mm patch cords between horizontal bit stream and p/s block as per the connections diagram. 12. Observe the bit pattern output of codeword Generator at vertical 7-bit stream. 13. Now connect the Data output to the Data In of 2121B which is block code decoder. 14. Now connect the clock and ground of 2121A to 2121B via a 2mm patch cord. 15. Now set the H-Matrix section of 2121B Block code Decoder unit as per the same set what you have chose for 2121A Encoder unit. Refer the Observation Table Now first set Data 0 at Encoder unit and press reset switch until you get same decoded data on LED display and as well as at the seven segment display in numeric form. Once you get the same data 0 at decoder unit you can vary BCD switch to get the sequential data from For any selected data from 0-9, check the H matrix in the form of H= [P] [Ik]; Parity matrix and Identity matrix as given in the Observation Table Also check the massage signal in vertical matrix R in the form of (d3, d2, d1, d0, p3, p2, p1) and check the status of Syndrome Em. As there is no error in the bits it will show (0 0 0). 19. Check the corrected code word and match it with the code word of Encoder unit. 20. Also check the Decode Bits (d3, d2, d1, d0) and match with the data at Encoder unit. 38

44 Equations for Parity Generation: Code Word Generator: Observation Table: 39

45 Aim: 10. BINARY CYCLIC CODE- ENCODER AND DECODER To study the Binary Cyclic Encoding and Decoding and to verify the input and output. Apparatus Required: 1. ST2120 Error Detection & Correction Cyclic Codes Kit mm Banana cable 3. Cathode Ray Oscilloscope Theory: The linear code C of length n is a cyclic code if it is invariant under a cyclic Cyclic code shift: if and only if As C is invariant under this single right cyclic shift, by iteration it is invariant under any number of right cyclic shifts. As a single left cyclic shift is the same as n-1 right cyclic shifts, C is also invariant under a single left cyclic shift and hence all left cyclic shifts. Therefore the linear code C is cyclic precisely when it is invariant under all cyclic shifts. Encoder Diagram: Fig.: Encoder for (7, 4) Cyclic Code Generator by g(x) =1+x 2 +x 3 40

46 Table: Register Contents of Encoder Block Diagram: Procedure: 1. Connect the power supply mains cord to the ST2120, but do not turn ON the power supply until connections are made for this experiment. 2. From Clock Section, connect 16 KHz Clock output to Clock Generator (Clock input). 3. Connect the Data Clock of clock generation section to Data Clock of Data Source. 4. Connect the Data Out of Data Source to Data In of Cyclic Encoder. 5. Connect the Code Clock of Clock Generation section to Code Clock of Cyclic Encoder. 41

47 6. Switch On the power supply and oscilloscope. 7. Observe the bit pattern of Code Word output of Cyclic Encoder. The bit stream is a repeating 8 bit serial sequence of the input data selected through BCD switches. 8. Change input data through BCD switches and observe the output of Cyclic Encoder. 9. Now connect the Code Word output of Cyclic Encoder to Decoder and output of Decoder to Input of display. 10. Change the clock input to 8 KHz to 1 KHz and then observe the data output. Observations: 1. The data output of Data Source is a repeating sequence of input data selected through BCD switches. 2. The 8 bits of output data are binary coded decimal values on BCD switches. 3. The output data rate of Data Sources is selected through the input data clock. 4. Encoded and decoded data stream is same as observed on segmental display. Result: 42

48 Aim: 1. AMPLITUDE SHIFT KEYING To generate the waveforms of Amplitude Shift Keying. Apparatus required: Name of the Apparatus Specifications/Range Quantity Resistors 1.2KΩ, 3 Transistor BC CRO 30MHz 1 Function generator 0-1MHz 1 Regulated Power Supply 0-30V, 1A 1 CRO Probes Theory: The binary ASK system was one of the earliest form of digital modulation used in wireless telegraphy. In an binary ASK system binary symbol 1 is represented by transmitting a sinusoidal carrier wave of fixed amplitude A c and fixed frequency f c for the bit duration T b where as binary symbol 0 is represented by switching of the carrier for T b seconds. This signal can be generated simply by turning the carrier of a sinusoidal oscillator ON and OFF for the prescribed periods indicated by the modulating pulse train. For this reason the scheme is also known as on-off shift testing. Let the sinusoidal carrier can be represented by Ec (t) =A c cos (2Πf c t) then the binary ASK signal can be represented by a wave s(t) given by S(t) = A c cos(2πf c t), symbol 1 ASK signal can be generated by applying the incoming binary data and the sinusoidal carrier to the two inputs of a product modulator. The resulting output is the ASK wave. The ASK signal which is basically product of the binary sequence and carrier signal has a same as that of base band signal but shifted in the frequency domain by ±f c. The band width of ASK signal is infinite but practically it is 3/T b. 43

49 Circuit Diagram: Fig: 1 Amplitude Shift Keying Circuit Procedure: 1. Connect the circuit as per the circuit diagram. 2. Switch on the supply. 3. Apply the sinusoidal carrier signal from the function generator to the collector terminal of the transistor with 10v (p-p) amplitude and10khz frequency. 4. Apply the Binary signal from the pulse generator to the Base terminal of the transistor with 5v (p-p) amplitude and 2 KHz frequency. 5. Observe the output of ON/OFF keying from ASK modulator circuit using CRO. 6. Now vary the Amplitude and frequency of the binary signal and observe the output changes of ASK modulated Wave & compare it with the modulating data signal applied to the modulator input. Model Waveforms: (a) 44

50 (b) Fig: 2 Waveforms of (a) Carrier signal (b) Data signal & ASK wave Questions: 1. Why we are not preferred ASK over PSK and FSK? 2. What is another name of ASK modulation scheme? 3. What is the Effect of carrier amplitude, frequency, V cc on the output? 45

51 Aim: 2. TIME DIVISION MULTIPLEXING AND DEMULTIPLEXING 1. To study the 4 channel analog multiplexing and de multiplexing 2. To study the effect of sampling frequency on output signal characteristics. Apparatus Required: 1. Time Division Multiplexing & De multiplexing (Digital) Trainer Kit (Or) a. Data Generator IC 7490 b. 8-1 Multiplexer IC c. 3-bit Address Generator IC d. 1-8 De multiplexer IC e. Clock Generator IC 555 f. DC Regulated Power Supply +5V. 2. Set of Patch chords 3. Dual Trace Cathode Ray Oscilloscope. Theory: 8 TO 1 MULTIPLIXER For this Multiplexing process, 8 bit Digital Multiplexer IC is used. L1 to L8 are the 8 input channels, data Multiplexed is given to them. A0, A1 and A2 are the address data finder. Depending upon the address data at any instant, input channel corresponding to the address location is multiplexed. For example, if the address bit is 101, channel L6 is multiplexed at that instant. 1 TO 8 DE MULTIPLEXER For this De multiplexing process, digital De multiplexer IC is used. L1 to L8 are the corresponding. 8-channel outputs, which are in synchronization to the multiplexed channels ar multiplexing process. The address data generator for both Multiplexer and De multiplexer is same. So both Multiplexer and Demultiplexer are in synchronization. 46

52 Block Diagram: Procedure: 1. Switch ON the experimental kit. 2. Observe the MSB bit of the address generator to one channel of a dual trace CRO and trigger the CRO w.r.t. the same channel. 3. Observe the output of the 8-1 line multiplexer on the second channel of the CRO. 4. Apply a low (GND) signal to the 8 multiplexing input one by one and observe how the total time is divided by each channel w.r.t. the address generator. Fig.2 shows the working principle. 5. Now connect the 8-1 line multiplexer to the 1-8 line demultiplexer. 6. Give any data available from the data generator to any multiplexing input and observe the output at corresponding demultiplexer output. Ex. Suppose if we are giving input at L1 input, observe the output of the Demultiplexing output at L1 only. 7. Now connect different data to the different inputs and observe the outputs at corresponding demultiplexed outputs and compare the multiplexing inputs and corresponding demultiplexed outputs. 8. Data provided at D1 is not multiplexed because its frequency is greater than the Address generators frequency (sampling theorem). 47

53 Model Output Waveforms: 48

54 Aim: 3. BINARY AMPLITUDE SHIFT KEYING MODULATION AND DEMODULATION To Generate the Amplitude Shift Keying Modulation and Demodulation signals using MATLAB Apparatus required: Software MATLAB7.0.4 Algorithm: Step1: The binary sequence is taken as input into a variable. Step2: The carrier signal with required frequency is selected. Step3: The required carrier wave is generated. Step4: The input binary data is given to serial to parallel converter. Step5: The parallel sequence is converted to analog signal using D/A converter. Step6: The analog signal is combined with the generated carrier signal. Step7: The required ASK signal is generated. Step8: (Detection) The ASK wave is combined with the carrier wave. Step9: The output is given to the comparator circuit. Step10: The output is converted into digital by using A/D converter. Step11: This gives us the binary sequence as the output of the demodulator. Block diagrams: BASK MODULATOR BASK DEMODULATOR Program: %Matlab program for ASK wave clc; clf; clear all; 49

55 close all; b=input('enter binary data:'); fc=4000; t=linspace(0,1/1000,50); ec=cos(2*pi*fc*t); ook=[ ]; bin=[ ];car=[ ]; for i=1:length(b); ook=[ook,b(i)*ec]; bin=[bin,b(i)*ones(1,50)]; car=[car,ec]; end %ASK detection balout=[ ];%sync det output demod=[ ];%demodulation output for i=1:length(ook); balout=[balout,car(i)*ook(i)]; end; for i=1:50:length(ook); if sum(balout(i):balout(i+49))>0.5 demod=[demod,ones(1,50)]; else demod=[demod,zeros(1,50)]; end; end; %ploting the graph subplot(5,1,1); plot(ec,'linewidth',2); title('carrier'); xlabel('time'); ylabel('amplitude'); subplot(5,1,2); plot(0:length(bin)-1,bin,'k','linewidth',2); title('input data'); xlabel('time'); 50

56 ylabel('amplitude'); subplot(5,1,3); plot(ook,'r-','linewidth',2); title('modulated data'); xlabel('time'); ylabel('amplitude'); subplot(5,1,4); plot(balout,'r-','linewidth',2); title('balanced modulator data'); xlabel('time'); ylabel('amplitude'); subplot(5,1,5); plot(demod,'r-','linewidth',2); title('demodulated output data'); xlabel('time'); ylabel('amplitude'); Model Output Waveforms: 51

57 Aim: 4. BINARY PHASE SHIFT KEYING MODULATION AND DEMODULATION To Generate the Binary Phase Shift Keying Modulation and Demodulation signals using MATLAB Software required: MATLAB7.0.4 Algorithm: Step1: The binary sequence is taken as input into a variable. Step2: This binary data is converted into the polar form either in RZ or NRZ form. Step3: The carrier signal with required frequency is selected. Step4: The required carrier wave is generated. Step5: Both carrier and the binary data is given to the balanced modulator circuit. Step6: The balanced modulator output gives us the BPSK waveform. Step7: (Demodulator) The BPSK wave is given to the multiplier along with the carrier signal. Step8: The multiplier output is passed through the low pass filter. Step9: This gives us the binary sequence as the output of the demodulator. Block diagram: 52

58 Program: %Matlab program for BPSK wave clc; clf; clear all; close all; b=input('enter binary data:'); fc=4000; t=linspace(0,1/1000,50); ec=cos(2*pi*fc*t); pskout=[ ]; bin=[ ];car=[ ]; for i=1:length(b); if b(i)==1 pskout=[pskout,b(i)*ec]; else pskout=[pskout,(b(i)-1)*ec]; end; bin=[bin,b(i)*ones(1,50)]; car=[car,ec]; end %BPSK detection balout=[ ];%sync det output demod=[ ];%demodulation output for i=1:length(pskout); balout=[balout,car(i)*pskout(i)]; end; for i=1:50:length(pskout); 53

59 if sum(balout(i):balout(i+49))>0 demod=[demod,ones(1,50)]; else demod=[demod,zeros(1,50)]; end; end; %ploting the graph subplot(5,1,1); plot(ec,'linewidth',3); title('carrier'); xlabel('time'); ylabel('amplitude'); subplot(5,1,2); plot(0:length(bin)-1,bin,'k','linewidth',3); title('input data'); xlabel('time'); ylabel('amplitude'); subplot(5,1,3); plot(pskout,'r-','linewidth',3); title('bpsk output'); xlabel('time'); ylabel('amplitude'); subplot(5,1,4); plot(balout,'r-','linewidth',3); title('balanced modulater data'); xlabel('time'); ylabel('amplitude'); subplot(5,1,5); plot(demod,'r-','linewidth',3); title('demodulated output'); xlabel('time'); ylabel('amplitude'); 54

60 Model Output Waveforms: 55

61 Aim: 5. FREQUENCY SHIFT KEYING MODULATION AND DEMODULATION To Generate the Frequency Shift Keying Modulation and Demodulation signals using MATLAB Software required: MATLAB7.0.4 Algorithm: Step1: The binary input bit sequence is taken and stored into a variable. Step2: The carrier frequencies for both low frequency and high frequency bits are selected and the respective carriers are generated. Step3: The input bits are given separately to two level shifters as one as the direct bits and for another through the inverter. Step4: Both the level shifter outputs are multiplied with the respective carrier (High frequency carrier for bit 1 and low frequency carrier for bit 0 ). Step5: Both the multiplier outputs are added up to get the output FSK wave form. Step6: In the FSK detector process at first the input FSK wave is given to the band pass filter and then passed through the limiting circuit. Step7: The limiting circuit output is given to the FM detector circuit. Step8: The FM detector output is then passed through low pass filter which acts as an integrator that adds up all the values of the signal. Step9: The low pass filter output is then given to the decision device which gives us the output as the input bit stream. Block diagrams: Binary FSK Transmitter: 56

62 Binary FSK Receiver Program: %Matlab program for FSK wave clc; clf; clear all; close all; b=input('enter binary data:'); f1=4000;f2=12000; t=linspace(0,1/4000,50); ec1=cos(2*pi*f1*t); ec2=cos(2*pi*f2*t); fskout=[ ]; bin=[ ];car1=[ ];car2=[ ]; for i=1:length(b); if b(i)==1 fskout=[fskout,b(i)*ec2]; else fskout=[fskout,(1-b(i))*ec1]; end; bin=[bin,b(i)*ones(1,50)]; car1=[car1,ec1]; car2=[car2,ec2]; end %FSK detection bal1=[ ];bal2=[ ];demod=[ ]; 57

63 for i=1:length(fskout); bal1=[bal1,car1(i)*fskout(i)]; bal2=[bal2,car2(i)*fskout(i)]; end; for i=1:50:length(fskout); sum1=0,sum2=0;sum=0; for i=i:i+49 sum1=sum1+bal1(i); sum2=sum2+bal2(i); end; sum=-sum1+sum2; if sum>0 demod=[demod,ones(1,50)]; else demod=[demod,zeros(1,50)]; end; end; %ploting the graph subplot(5,1,1); plot(car1,'linewidth',3); title('carrier 1'); xlabel('time'); ylabel('amplitude'); subplot(5,1,2); plot(car2,'linewidth',3); title('carrier 2'); xlabel('time'); ylabel('amplitude'); subplot(5,1,3); plot(0:length(bin)-1,bin,'k','linewidth',3); title('input data'); xlabel('time'); ylabel('amplitude'); subplot(5,1,4); plot(fskout,'r-','linewidth',3); title('fsk output'); xlabel('time'); 58

64 ylabel('amplitude'); subplot(5,1,5); plot(demod,'r-','linewidth',3); title('demodulated output'); xlabel ('time'); ylabel ('amplitude'); Model Output Waveforms: 59

65 Aim: 6. QUADRATURE PHASE SHIFT KEYING MODULATION AND DEMODULATION To Generate the Quadrature phase Shift Keying Modulation and Demodulation signals using MATLAB Software required: MATLAB7.0.4 Algorithm: Step1: The binary bit sequence is first taken into a variable. Step2: The suitable carrier frequency is selected and two carriers one with zero phase and other with 90o phase are generated. Step3: The input bit stream is given to the de-multiplexer and is decoded. Step4: The de-multiplexer output is divided into two and one is multiplied with in phase component and the other with the out of phase component. Step5: Both the multiplexer outputs are taken and are added together which gives us the QPSK output wave. Step6: In the de-modulation process the input QPSK wave is multiplied with both the in phase and out phase components by an multiplier. Step7: Both the outputs are passed through an low pass filter which acts as an integrator that adds up all the values of the signal. Step8: The low pass filter outputs are given to the decision device which assigns the values to the wave. Step9: The decision device output is given to the multiplexer circuit which gives the output as the input bit stream. Block Diagrams: 60

66 Program: %Matlab program for QPSK wave clc; clf; clear all; close all; b=input('enter binary data:'); fc=4000; t=linspace(0,1/4000,50); ec2=cos(2*pi*fc*t); ec1=sin(2*pi*fc*t); qpskout=[ ];bin=[ ];car1=[ ];car2=[ ];be=[ ];bo=[ ];bal1=[ ];bal2=[ ]; for i=1:length(b); bin=[bin,b(i)*ones(1,50)]; car1=[car1,ec1]; car2=[car2,ec2]; if mod(i,2)==0 if b(i)==0 be=[be,-ones(1,100)]; else be=[be,ones(1,100)]; end; bal1=[bal1,be(i*50-1)*ec1,be(i*50-1)*ec1]; else if b(i)==1 bo=[bo,ones(1,100)]; else bo=[bo,-ones(1,100)]; 61

67 end; bal2=[bal2,bo(i*50-1)*ec2,bo(i*50-1)*ec2]; end; end; for i=1:2:length(b) if b(i)==0 && b(i+1)==0 qpskout=[qpskout,-ec1-ec2,-ec1-ec2]; elseif b(i)==0 && b(i+1)==1 qpskout=[qpskout,-ec1+ec2,-ec1+ec2]; elseif b(i)==1 && b(i+1)==0 qpskout=[qpskout,ec1-ec2,ec1-ec2]; else end; qpskout=[qpskout,ec1+ec2,ec1+ec2]; end; %ploting the graph subplot(4,1,1); plot(bin,'linewidth',3); title('binary data'); xlabel('time'); ylabel('amplitude'); subplot(4,1,2); plot(be,'r','linewidth',3); title('even data'); xlabel('time'); ylabel('amplitude'); subplot(4,1,3); plot(bo,'g','linewidth',3); title('odd data'); 62

68 xlabel('time'); ylabel('amplitude'); subplot(4,1,4); plot(car1,'linewidth',3); title('carrier 1'); xlabel('time'); ylabel('amplitude'); figure; subplot(4,1,1); plot(car2,'linewidth',3); title('carrier2'); xlabel('time'); ylabel('amplitude'); subplot(4,1,2); plot(bal1,'r','linewidth',3); title('bal mod 1 data'); xlabel('time'); ylabel('amplitude'); subplot(4,1,3); plot(bal2,'g','linewidth',3); title('bal mod 2 data'); xlabel('time'); ylabel('amplitude'); subplot(4,1,4); plot(qpskout,'linewidth',3); title('modulated'); xlabel('time'); ylabel('amplitude'); %demodulation of qpsk demod1=[ ];demod2=[ ];demod=[ ];synd1=[ ];synd2=[ ]; for i=1:length(qpskout); 63

69 synd1=[synd1,car1(i)*qpskout(i)]; synd2=[synd2,car2(i)*qpskout(i)]; end; for i=1:100:length(qpskout); sum1=0;sum2=0; for i=i:i+99 sum1=sum1+synd1(i); sum2=sum2+synd2(i); end; if sum1 > 0 demod1=[demod1,ones(1,50)]; else demod1=[demod1,zeros(1,50)]; end; if sum2 > 0 demod2=[demod2,ones(1,50)]; else demod2=[demod2,zeros(1,50)]; end; end; demod1 demod2 for i=1:50:length(demod1); demod=[demod,demod1(i:i+49),demod2(i:i+49)]; end; %ploting the graph figure; subplot(3,1,1) plot(synd1,'linewidth',3); title('sync detector 2'); xlabel('time'); ylabel('amplitude'); subplot(3,1,2) plot(synd2,'r','linewidth',3); title('sync detector 2'); xlabel('time'); ylabel('amplitude'); 64

70 subplot(3,1,3) plot(demod,'g','linewidth',3); title('demodulated'); xlabel('time'); ylabel('amplitude'); Model Output Waveforms: 65

71 66

72 APPENDIX Name of the component 74LS00 74LS08 74LS74 Important Specifications Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low Max- 80mA Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High Max mA Output Current Low Max- 80mA Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Power supply current - 8.0mA Pin Diagram Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High Max mA Output Current Low Max- 80mA Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low max - 80mA 67

73 74LS374 Supply Voltage Min 4.75V Supply Voltage Max 5.25V High level input voltage min 2V Low level input voltage max 0.8V High level output current max -2.4mA Low level output current max- 24mA Operating temperature Range 0 o C to +70 o C LS163 Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low max - 80mA Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low max - 80mA 68

74 74LS164 Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low max - 80mA Supply Voltage Min 4.75V Supply Voltage Max 5.25V Free air operating temperature- 0 o C to +70 o C Supply Current max 36mA Clock frequency 25MHz Pulse width (Clock) 25ns Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Power supply current 34mA

75 74193 Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Clock frequency 25MHz Supply Current max 34mA 74LS86 Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low max - 80mA 74LS90 Supply Voltage Min 4.75V Supply Voltage Max 5.25V Operating temperature Range 0 o C to +70 o C Output Current High max mA Output Current Low max - 80mA LM311 Input voltage Range V to 13V Voltage gain 40V/mV Saturation voltage 1.5V Positive Supply Current 7.5mA Negative Supply Current 5mA LM324 Wide power supply rating 3V to 32V Operating temperature Range 0 o C to +70 o C Storage temperature - (-65 o C to +150 o C) 70

76 DAC0800 ADC0800 Supply Voltage 5V Operating temperature Range (-55 o C to +125 o C) Power Dissipation -500mW Input current 5mA Storage temperature - (-65 o C to +150 o C) Supply voltage ±5V Clock range 50 to 800KHz Operating temperature Range (-55 o C to +125 o C) Power supply current 20mA CD4051 Supply voltage - +5V to 18V Operating temperature Range (-40 o C to +80 o C) Storage temperature - (-65 o C to +150 o C) Power dissipation 700mW CD4052 Supply voltage - +5V to 18V Operating temperature Range (-40 o C to +80 o C) Storage temperature - (-65 o C to +150 o C) Power dissipation 700mW 8038 Simultaneous outputs sine wave Square wave and Triangle Low distortion 1% High linearity 01% Easy to use 50% reduction in external components Wide frequency range of operation Hz to 1.0Mhz Variable duty cycle 2% to 98% 71

77 TL084 µa741 Supply voltage - ±18V or 36V total Power dissipation 750mW Input voltage (any pin) Not to exceed supply voltages Input current (pins 4 and 5 ) 25mA Operating temperature range: 55 o C to +125 o C Supply Voltage ±22V Power Dissipation 500mW Differential input voltage ±30V Input voltage ±15V Operating Temperature -55 o to +125 o C Storage Temperature range -55 o to +150 o C Supply Voltage ±18V Power Dissipation 680mW Input voltage ±15V Operating Temperature -0 o to +70 o C Storage Temperature range -65 o to +150 o C IC 555 Operating tem :SE o C to 125 o C NE o to 70 o C Supply voltage :+5V to +18V Timing :µsec to Hours Sink current :200mA Temperature stability :50 PPM/ o C change in temp or 0-005% / o C. 72