ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

Transcription

1 EEN474/704: (Analo) SI ircuit esin Sprin 018 ecture 3: MOS ransistor Modelin Sam Palermo Analo & Mixed-Sinal enter exas A&M Uniersity

2 Aenda MOS ransistor Modelin are-sinal Model Small-Sinal A Model MOS apacitors urrent Readin Razai hapters & 17

3 rawn & Effectie hannel enths [Razai] drawn he transistor ate oerlaps both the source and drain reion by a lenth of due to side diffusion in the fabrication process his results in the ectie transistor ate lenth,, bein shorter than the drawn lenth, drawn hrouhout the remainder of the course, will enerally refer to 3

4 Finite Output Resistance in Saturation [Sedra/Smith] In saturation, as S is increased the channel pinch-off point moes slihtly towards the source his phenomenon is called channel-lenth modulation and is characterized by a parameter 4

5 Finite Output Resistance in Saturation [Sedra/Smith] he current will increase slihtly with S in saturation, resultin in a finite incremental output resistance Note, the channel-lenth modulation parameter is inersely proportional to I I I n n n n ox ox n ox ox ox n S n n 1 1 n n S S 5

6 MOS are-sinal Output haracteristic with Finite Output Resistance [Sedra/Smith] has units of 1 riode : I Saturation : I n ox n ox 1 n 0.5 n S S S 6

7 MOS are-sinal ransfer haracteristic [Sedra/Smith] I n ox n 1 S 7

8 Impact of Bulk oltae X SB I n ox n 1 S [Razai] F SB F SB he current decreases as SB increases due to an increased threshold oltae 8

9 are-sinal Response 9

10 are-sinal + Small-Sinal A Response For small-sinal analysis, we linearize the response about the operatin point If the sinal is small enouh, linearity holds and the complete response is the summation of the lare-sinal response and the small-sinal A response 10

11 ow-frequency Small-Sinal Model he linearized small-sinal model is formed by computin an ectie oltae-to-current transformation factor conductance by differentiatin the lare-sinal response at the operatin point [Razai] 11

12 ransconductance, m ransistor transfer characteristic is used to extract transconductance, m In Saturation (Nelectin Effects) I OX m i s OX [Sedra/Smith] 1

13 Output onductance, o ransistor output characteristic is used to extract output conductance, o I In Saturation (Includin Effects) OX 1 S o i ds OX I [Sedra/Smith] 13

14 Body ransconductance, mb he small-sinal drain current chanes with BS modulation due to chanes in [Razai] mb i bs In Saturation (Nelectin Effects) OX * bs F m SB 14

15 ow-frequency Small-Sinal Model 15 SB F m bs OX bs mb OX ds OX s m i i i * 0 [Razai]

16 MOS ransistor apacitances [Razai] Gate - hannel ap G ox hannel - Bulk ap B q SiN 4 F sub Gate - Source Oerlap (Frinin) ap o o Note, o ox Gate - rain Oerlap (Frinin) ap Go o Source - Bulk Junction ap SBJ A S j P S jsw rain - Bulk Junction ap BJ A j P jsw j j0 1 BX B m jsw 1 jsw0 BX B msw 16

17 MOS ransistor apacitances (Off) [Razai] Gate - rain ap G Go o Gate -Source ap Go o Gate - Bulk ap GB G G B B rain - Bulk ap B Source - Bulk ap SB BJ SBJ 17

18 MOS ransistor apacitances (riode) [Razai] Gate - rain ap Gate - Bulk ap G Gate -Source ap GB rain - Bulk ap B Source - Bulk ap SB 0 Go o BJ SBJ G B G B 18

19 MOS ransistor apacitances (Saturation) [Razai] Gate - rain ap G Go Gate -Source ap Gate - Bulk ap GB 0 o 3 G rain - Bulk ap B Source - Bulk ap SB BJ SBJ 3 B 19

20 MOS Gate apacitors Response [Razai] Note, o ox 0

21 MOS Source & rain Junction apacitors [Razai] P S A S P A E E Junction SB B A j P jsw E j E jsw 1

22 Source/rain Junction Perimeter aps isclaimer Note, there is some ambiuity on how to model the source/drain junction perimeter (sidewall) capacitance on the side of the ate his is due to the channel occupyin a portion of the sidewall area ifferent textbooks present different approaches he Razai text conseratiely assumes that the sidewall perimeter capacitance is the same on all sides he Johns/Martin text (sometimes preiously used) optimistically sets the sidewall perimeter cap to zero under the ate he correct answer is somewhere in the middle e will follow the Razai method and assume that the sidewall perimeter capacitance is the same on all sides (een under the ate) I will try to make it clear on any problem description

23 MOS Source & rain Junction apacitors [Razai] P S A S P A E E Junction SB B A j P jsw E j E jsw Foldin into finers & sharin drain Foldin into finers Junction SB S A S P S A P j E E A E E E P S jsw E j E Foldin the transistor allows for approximately half the drain junction capacitance with a small increase in source junction capacitance jsw Junction B A j P jsw E j E jsw 3

24 AMU J. Sila-Martinez rain/source Resistance Other resistors: Source/rain i P+ /S rain/source Resistance In addition to the contact resistance, the diffusion resistance has to be considered. op iew R R series R R [] i In SPIE, R [] is defined as RSH -4-

25 AMU J. Sila-Martinez -5- Small Sinal Model (Saturation reion) Small sinal model (saturation reion) B o mb bs m s B db d s bs S S G bs bs ds ds s s S OX F SB F S OX i i i i I SB F m bs OX bs mb OX ds OX s m i i i * 0 bs mb ds 0 s m I i

26 Next ime MOS ransistor Modelin Hih-Field Short-hannel Effects Spice Models 6