A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Transcription

1 RADIOENGINEERING, VOL., NO., JUNE A Survey of Non-conventional Techniques for Low-voltae Low-power Analo ircuit Des Fabian KHATEB 1, Sala BAY ABO DABBOUS 1, Spyridon VLASSIS 1 Dept. of Microelectronics, Brno University of Technoloy, Technická 10, Brno, zech Republic Electronics Laboratory, Physics Departent, University of Patras, Greece khateb@feec.vutbr.cz, xbayab00@stud.feec.vutbr.cz, svlassis@physics.upatras.r Atract. Des terated circuits able to work under low-voltae (LV) low-power (LP) condition is currently undero a very considerable boo. Reduc voltae supply and power consuption of terated circuits is crucial factor sce eneral it ensures the device reliability, prevents overheat of the circuits and particular prolons the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulkdriven (BD), float-ate (FG) and quasi-float-ate (QFG) techniques have been proposed as powerful ways to reduce the des coplexity and push the voltae supply towards threshold voltae of the MOS transistors (MOST). Therefore, this paper presents the operation prciple, the advantaes and disadvantaes of each of these techniques, enabl circuit desers to choose the proper des technique based on application requireents. As an exaple of application three operational transconductance aplifiers (OTA) based on these non-conventional techniques are presented, the voltae supply is only ±0.4 V and the power consuption is 3.5 μw. PSpice siulation results us the 0.18 μ MOS technoloy fro TSM are cluded to verify the des functionality and correspondence with theory. Keywords Low-voltae low-power analo circuit des, bulkdriven, float-ate, quasi-float-ate, OTA. 1. Introduction Over the last decade reduc the voltae supply and iiz the power consuption becoe the ost iportant priority particularly for portable electronics and battery-powered iplantable and wearable edical devices. The LV LP capability of portable electronics and battery-powered edical devices is essential deand sce it enables creas the battery lifetie and/or decreas the size and weiht of the devices by us battery with saller size and weiht which is deanded and iportant odern devices [51]. Interated circuit (I) technoloies trend toward reduction of the iu feature size of MOS transistors, thus ore electronic functions per unit area are achieved. However, creas the device density of sle I eans its turn hiher power dissipation and overheat. Hence it is very iportant to decrease the power dissipation of the terated circuits to ensure device function and reliability [1]. Achieveent of LV LP operation could be obtaed either by technoloies or by des techniques. The a advantaes and disadvantaes of the LV LP technoloies and soe of the ost popular techniques are discussed this paper; three a technoloies are used for low-voltae low-power I des: BiMOS technoloy is advanced seiconductor technoloy, which terates bipolar junction transistor and MOS transistor a sle terated circuit, and cobes the advantaes of both transistor types. This technoloy iproves speed over purely bipolar technoloy, offers lower power dissipation over purely MOS, hih analo perforance, saller I size and ore reliable I. However, this technoloy requires extra fabrication steps which crease the process cost [9]. SOI (Silicon on sulator) technoloy: In this technoloy a layer of silicon dioxide is iplanted below the surface by oxidation of Si or by oxyen iplantation to Si. This iplanted silicon dioxide is called buried oxide (BOX) which helps to reduce parasitic capacitances, and as a result iproves the perforances of the device. This technoloy offers ideal device isolation and saller layout area, hih switch speed and lower-power consuption. However, fabrication of this technoloy is ore expensive featur also hiher self-heat because of poor theral conductivity of the sulator []. MOS Technoloy: In MOS (copleentary etal oxide seiconductor) technoloy both kds of transistors are used p-channel MOSFET and n-channel MOSFET a copleentary way on the sae sutrate. Besides, MOS technoloy is used the fabrication of conventional icrochip, sce it is less expensive than BiMOS and SOI technoloies and offers hih perforance, hih density and low-power dissipation.

2 416 F. KHATEB, S. BAY ABO DABBOUS, S. VLASSIS, A SURVEY OF NON-ONVENTIONAL TEHNIQUES FOR LOW-VOLTAGE While the MOS transistor diensions are shrunk, the power supply voltae is reduced to ensure the device reliability. However, the threshold voltae is not scaled down by the sae ratio sce devices with hiher threshold voltae value have hiher noise ar and saller leakaes [7]. This rather hih value of the threshold voltae is the a liitation LV LP analo circuit des. In order to overcoe this restriction any techniques have been troduced based on MOS technoloy. By utiliz these techniques, the threshold voltae is decreased or even reoved. The ost widely used techniques for LV LP analo circuits des are: ircuits with rail-to-rail operat rane [49, 50]. MOSTs operat weak version [6]. Level shifter techniques [7]. Float-ate approach [4, 7, 1, 13, 14, 15, 9, 33, 34, 35, 37, 39, 44]. Quasi-float-ate approach [16, 17, 18, 19, 0, 38, 41, 4, 43]. Bulk-driven MOST [3, 5, 7, 8, 10, 11, 1, 1, 3, 4, 5, 7, 8, 31, 3, 36, 40]. However, the last three techniques are considered as non-conventional; they offer aly des siplicity and capability to work under ultra LV LP condition with sufficient circuit s perforances. ircuits based on these techniques are suitable for ultra LV LP application as batterypowered iplantable and wearable edical devices. Based on our survey a variety of recent publications describe various attractive ipleentations of the non-conventional techniques LV LP applications such as operational aplifier [16, 8, 9], operational transconductance aplifier OTA [30-35], second eneration current conveyor II [19, 36, 37, 38], class AB output stae for MOS op-aps [39], transconductors [41-44], current differenc external transconductance aplifier (DeTA) [40], differential-put buffered, external transconductance aplifier (DBeTA) [11], differential voltae current conveyor DV [7], and any others. This paper is oranized as follows. In Section, the non-conventional techniques based on bulk MOS technoloy are presented, clud prciple of operation, sall sal odels and a advantaes and disadvantaes of each technique. Section 3 presents OTA des as an application exaple based on these techniques, siulation results and their evaluations are also cluded. Fally, Section 4 concludes the paper.. Non-conventional Techniques Based on Bulk MOS Technoloy.1 Bulk-driven MOST (BD-MOST) MOS transistor is a four terals device naely: dra D, ate G, source S and bulk B as shown Fi. 1(a) and its cross section (b) which is presented with sutrate teral Sub. Depend on the type of used technoloy (i.e. N-, P-well or tw-tub) the bulk teral is norally connected either to positive/neative supply voltae for PMOS/NMOS transistor, respectively, or to the transistor source teral. In other words, the bulk teral is ored and not used as a sal teral and hence any applications are overlooked. The prciple of the bulk-driven technique was firstly presented [10]. Fi. 1. Bulk-driven N-MOST: a) sybolic and b) crosssection. To deonstrate the prciple of operation of the bulkdriven technique coparison with the conventional atedriven MOST (-MOST) the coon source aplifier as an exaple of application is shown Fi.. In the bulk-driven technique the ate-source voltae ust be set to a proper bias voltae V bias to for an version layer under the ate oxide, peritt the operation the conductance reion. V V out V Fi.. oon source aplifier based on a) ate-driven NMOST and b) bulk-driven NMOST. Unlike the conventional ate-driven technique the put sal the bulk-driven technique is applied to the bulk teral V = V rather than the ate teral. The operation of the BD-MOST is uch like a JFET where the channel width is constant as lon as the put and bias voltaes don t chane. Fi. 3 shows the dra current versus bulk-source voltae of BD-NMOST Fi. (b) with three different diensions, it is clear that by scal up the transistor diensions W/L the transconductance steadily creases, as it is discussed later. As well the relationship between dra current and ate-source voltae of the ate-driven NMOST Fi. (a) is shown Fi. 3. The siulation has been done with the follow characteristics: V DD = 0.8 V, V ss = 0 V, V bias = 0.5 V, R D = 15 k, W/L = (5μ/0.5μ, 10μ/0.5μ and 0μ/0.5μ) for BD-NMOST and W/L = 5μ/0.5μ for -NMOST, 0.18 μ MOS process. It is evident fro Fi. 3 that the dra current of the - NMOST appears when the put voltae exceeds the V out

3 RADIOENGINEERING, VOL., NO., JUNE threshold voltae value (V T 400 V); while BD- NMOST the threshold voltae has been reoved. Furtherore, the BD-NMOST operates under neative put voltae and has a wide operat rane stretches to slihtly positive put voltae. onversely, the BD-PMOST operates under positive, zero and slihtly neative put voltae. Hence BD-MOST is a very attractive technique railto-rail applications [1], [11]. bulk-source voltae for various teperatures of -10, 7 and 70. The cross section of BD-NMOST is shown Fi. 1(b) the ai to ease understand the sall sal odel of the coon source BD aplifier and the fluence of the parasitic capacitances on BD-MOST's paraeters, as it is discussed below. Fi. 5(a) and (b) show the sall sal equivalent circuit at hih frequencies of the coon source aplifier based on -NMOST and BD-NMOST, respectively. The capacitances bd,, ub are bulk-dra, bulk-source and bulk-sutrate parasitic capacitance, respectively. These parasitic capacitances are a result of well and sutrate structure of the transistor. Fi. 3. Dra currents versus ate-source voltae of - MOST and bulk-source voltae of BD-MOST with various W/L ratios. Fi. 4. Bulk current versus bulk-source voltae of the BD- NMOST for teperatures of -10, 7 and 70. However, the operat rane of the BD-MOST ust be liited to avoid latch up proble, sce the bulk-source voltae ust be saller than the turn-on voltae of the bulk-source PN junction diode [11], which causes a rearkable current throuh the bulk teral and the transistor is latch up. It is relatively safe to use BD-MOST at low-voltae applications ore than other applications. Fi. 4 shows the current throuh bulk teral versus the Fi. 5. Sall sal equivalent circuit of the coon source aplifier based on: a) Gate-driven NMOST, b) Bulkdriven NMOST. The transconductance of -MOST which operates stron version is iven by: W K ( vs VT ) (1) L where W, L are channel width and channel lenth, respectively. V s is ate-source voltae, V T is the threshold voltae, K is the current a factor of the used process. Nevertheless the transconductance of BD- MOST is [11]: B b (0. 0.4) V G F BS where B is the total bulk-channel capacitance, G is the total ate channel capacitance, is the body ect coicient, and F the Feri potential, V BS is the quiescent bulksource voltae. Fro previous equation it is clear that b is saller than, the sae result understandable fro Fi. 3. The relatively sall transconductance of the BD- MOST is considered as one of its drawbacks coparison with -MOST, sce hih value of transconductance is widely desired analo circuit des. However, saller transconductance is attractive several applications such as bioedical applications. A practical exaple is the G - filter [, 33, 34, 48], where the positions of poles are detered by the ratio /, because bioloical sals ()

4 418 F. KHATEB, S. BAY ABO DABBOUS, S. VLASSIS, A SURVEY OF NON-ONVENTIONAL TEHNIQUES FOR LOW-VOLTAGE frequencies are sutantially sall, the poles ust be at very low values and this can be achieved either by creas the capacitance value or decreas the transconductance. Factually decreas transconductance is ore practical; saller transconductance was troduced a lot of works such as [45, 46]. Nevertheless the BD-MOST's transconductance can be creased by creas the W\L ratio as it was discussed previously. To detere the frequency perforance of a BD- MOST, transition frequency f T ust be calculated. This frequency is defed as the frequency where the anitude of the short circuit, coon-source current a falls to unity [47]. To calculate the transition frequency, consider the ac circuit of Fi. 6(a) and the sall sal equivalent of Fi. 6(b), whereas the parasitic capacitances have been described Fi. 5. i i out i iout Fi. 6. ircuits for calculat transition frequency of BD- MOST: a) ac scheatic, b) sall sal equivalent circuit. The sall sal put current i : i s( ) v. (3) ub If the current throuh bd is nelected then i out : out bv bd i. (4) Fro (3) and (4) we can fd the current a: i out i b s( bd ). (5) ub Put s = j to fd the frequency response, then: i out i b j ( bd ). (6) ub The anitude of the sall sal current a is unity when: b T. (7) ub Then the transition frequency of the BD-MOST is: f T b 1 1 T bd b ub bd. (8) Assue that ( + ub ) is uch reater than bd, that ives: b f T ( ) f b T ( ) (9) ub whereas f T is transition frequency of -MOST which can be calculated by the sae steps: f T. (10) Fro (9) it is obvious that the transition frequency of BD-MOST is saller than the transition frequency of - MOST, sce the transition frequency is proportional to the transconductance, as well as the ect of the parasitic capacitances. The put referred noise power spectral density of -MOST is expressed by: s ni i (11) where i ni is the total dra current enerated by noise sources and its unit is A. The put referred noise power spectral density of BD-MOST can be expressed by [11]: v noise, BD b. (1) BD-MOST suffer fro hiher referred noise as it is clear fro (1), sce b herently saller than. BD-MOST and -MOST have identical output resistance r o Fi. 5: 1 1 ro. (13) I o DSsat Many advantaes can be obtaed by us the BD- MOST analo circuit des: The threshold voltae requireents are reoved. A wider put coon ode rane under neative, zero and slihtly positive put voltae (BD- NMOST). Suitable for rail-to-rail applications. an be odeled us the conventional MOS transistor. an process D and A over the FG-MOST and QFG-MOST which process A only, as it is discussed below. In the other hand soe drawbacks coe with the BD- MOST technique: Saller transconductance and transition frequency coparison with -MOST. Hiher put referred noise than conventional - MOST. In the applications where both PMOS and NMOS are needed to use as bulk-driven transistors, tw well process is needed, that can be achieved at the expense of hiher cost process and larer chip area. Analo circuits with tiht atch between BD- MOSTs are difficult to be fabricated, sce BD-

5 RADIOENGINEERING, VOL., NO., JUNE MOSTs are fabricated differential wells to have isolated bulk. Latch-up aybe occurs.. Float-ate MOST (FG-MOST) The first well-known application of the FG-MOST was to store data diital EEPROMs, EPROMs and flash eories [37]. Recently, any new and iportant LV LP applications were desed us the float ate technique [13, 14, 15, 9, 33, 34, 35, 37, 39, 44], sce the threshold voltae is tunable as it is discussed below. The sybol of the FG-MOST with two control ates is shown Fi. 7(a), its equivalent circuit (b), its layout (c) and the cross-sectional views (d). The ate FG-MOST is fabricated us the poly1 layer and is left float, sce it is surrounded by sulator layers (SiO ). Two or ore control ates (G, G bias ) are fored us the second poly layer and capacitively coupled to the float ate. Section A G G bias Source SiO Metal (a) D S FG-poly1 B poly1 poly Dra V V bias n+ bias Source fb V fd D FG fs VS (b) FG P-sutrate Section A VB Dra n+ and Q FG is the itial chare trapped at the float ate dur fabrication; Sce float ate is surrounded by hih-quality isolation any electrical chare jected onto this ate is retaed for several years, caus D offsets. However, this chare can be eliated by several ways such as clean with ultraviolet (UV) liht, hot electron jection [4, 7, 1], Fowler-Nordhei (FN) tunnel [4, 1], forc an itial condition with a switch [4] or by fabrication process solution which is based on a novel layout technique that takes advantae of the fabrication process itself [56]. To deonstrate the operation prciple of the FG- MOST, a coon source aplifier based on the FG- NMOST with two control ates is shown Fi. 8(a), its sall sal equivalent circuit is depicted Fi. 8(b). As it is clarified Fi. 8, a proper bias voltae V bias is applied at one of the control ates G bias throuh lare value capacitance, which is able to shift the threshold voltae. The put sal is applied at the second control ate G and odulates the version layer, thus controls the dra current. The threshold voltae of the FG-MOST is expressed by: V T FG V V T bias (16) K1 where V T is the threshold voltae of a conventional - MOST, K 1 and K are iven by: K 1, K bias K. (17) It is obvious fro (16) that the threshold voltae of FG-MOST is saller than the threshold voltae of conventional -MOST; it can be even reoved with proper values of the bias voltae, K 1 and K. Input 1 Input SiO Section B Poly put1 G (c) Poly put G bias FG P-sutrate Section B (d) Fi. 7. Two-put float ate NMOST: a) sybolic, b) equivalent circuit, c) layout and d) cross-sectional views. The float ate voltae is iven by: VFG V biasvbias fdvd fsvs fbvb QFG (14) where the capacitances and bias are the control ates capacitances at which the put sal V and the bias voltae V bias is applied, respectively. fb, fd and fs denote the float ate-bulk, -dra and -source capacitances. is the su of these capacitances: (15) bias fd fs fb Fi. 8. Float-ate MOST: a) coon source aplifier and b) sall sal odel equivalent circuit. For exaple, assue the coon source aplifier Fi. 8(a) with a a FG-NMOST has has W/L W/L = 10/0.5μ/μ, = 10/0.5μ, R D = 15 k, = bias = 0.1 pf, fs = fd = 0.8 ff, thus K 1 = K 0.5 and the threshold voltae is reoved for V bias = 0.7 V. The sae result is illustrated Fi. 9 where

6 40 F. KHATEB, S. BAY ABO DABBOUS, S. VLASSIS, A SURVEY OF NON-ONVENTIONAL TEHNIQUES FOR LOW-VOLTAGE the dra current of the previous FG-NMOST is copared with the dra current of the -NMOST Fi. (a). Whereas the -NMOST has has W/L W/L = 10/0.5μ/μ = and R D = 15 k. Fro Fi. 9 it is obvious that the threshold voltae requireent is reoved fro the sal path us FG-MOST. The sall sal put current is: ( bias fs fd ) i s vs. (19) If the current throuh fd is nelected then: i out, v. (0) s Fro (19) and (0), the current a can be written: Fi. 9. Dra currents versus ate-source voltaes of FG- MOST and -MOST. Actually, the desers face a proble with siulation of the FG-MOST, because the siulators don't accept a float node. Many solutions have been proposed to overcoe the siulation proble and are presented [4], [5-55]. The ost popular solution is to connect extreely hih resistor parallel with the float ate put capacitors [53]; this ethod was used to siulate FG-MOST this paper. The ective transconductance of cobed structure of the FG-MOST is iven by:, K 1. (18) It's clear fro this equation that the ective transconductance, is saller than the ate transconductance. The ective transconductance can be creased proportionally with and / ratio. That can be done at the expense of creas the power consuption and the occupied chip area. To calculate transition frequency, let s consider the ac circuit and its sall sal equivalent circuit Fi. 10: i i out i Fi. 10. ircuit for calculat transition frequency of FG- MOST: a) ac scheatic, b) sall sal equivalent circuit. i out i out,. (1) i ( bias fs fd ) s By follow the sae steps that were done to fd transition frequency of BD-MOST at the previous suection, the transition frequency equation of FG-MOST will be iven by:. ft. () FG ( bias fs fd ) Assu fs is uch reater than fd and sutitut the ective transconductance value fro (18), then: ft. (3) FG ( bias fs ) It is clear that the transition frequency of FG-MOST is saller than the transition frequency of -MOST; hence FG-MOST has saller bandwidth than -MOST. The relationship between the put referred noise power spectral density of FG-MOST and -MOST is iven by [4]: FG. (4) It is evident that the put referred noise creases at the ective put of the FG-MOST. The ective output conductance of the FG-MOST is larer than the output conductance of the -MOST, because of D and A feedback fro dra to float ate throuh fd [7]. The output conductance of FG-MOST is iven by [4]: 1 fd ds. ds (5) ro, where ds is output conductance of -MOST transistor operates at the sae bias conditions. Many advantaes can be obtaed us FG-MOST technique, such as: Possibility of ulti-put terals. Threshold voltae can be shifted accord to the application s requireents. an be used ultra-low power ultra-low voltae applications.

7 RADIOENGINEERING, VOL., NO., JUNE an be fabricated any MOS technoloy, althouh for better perforance double poly technoloy is recoended. There are soe disadvantaes co with this technique: Larer area is occupied on the chip over the conventional -MOST, sce the bias and put capacitances have relatively hih values [4, 19]. Uncerta aount of cuulative itial chare the float ate. Reduction of the ective transconductance and output ipedance coparison with the conventional -MOST. Saller transition frequency, hence saller bandwidth than the -MOST. Shortae of siulation odels, as well the siulators don t accept the float node. the ate-dra capacitor of the diode connected transistor M R. Fi. 1 shows the coon source aplifier based on QFG-MOST (a) and its sall sal equivalent circuit (b), where the previous capacitors are shown, however the float ate-bulk capacitance is ored, because it has no fluence on sal path. The operation prciple of the QFG-MOST is siilar to the FG-MOST..3 Quasi-Float-ate MOST (QFG-MOST) Many recent publications describe terest and iportant ipleentations of the QFG-MOST LV LP applications [16, 17, 18, 19, 0, 38, 41, 4, 43]. The QFG- MOST appears as a developed version of the FG-MOST to overcoe soe of its drawbacks. It has been discussed previously that the relatively hih bias capacitance value of the FG-MOST leads to an crease the silicon area and a reduction of the ective transconductance and GBW. Besides, FG-MOST has uncerta residual chare trapped at the float ate. Us the QFG-MOST, the occupied chip area is iized and the itial chare is no loner an issue [4]. Sce the float ate is tied throuh a lare value resistor to a proper bias voltae, depend on the transistor type. Practically, a leakae resistance R lk of a reverse biased P-N junction of a diode connected MOS transistor M R is ipleented rather than a typical resistor, as it is obvious Fi. 11 which shows the sybolic of the QFG-MOST (a), its equivalent circuit (b) and layout (c) with sle put teral. QFG-MOST ay have a ultiple put terals like the FG-MOST. Besides, it can be fabricated any MOS technoloy, nevertheless, the double poly technoloy is recoended to obta better results. As it is shown Fi. 11 the put teral is capacitively connected to the float ate as FG-MOST case. The quasi-float ate D voltae value is set to V bias dependently of the D coponent of the put voltae while the quasi-float ate A voltae can be expressed by [19]: srlk VQFG ( V fdvd fsvs fbvb ) (6) 1 srlk where is:. (7) fs The capacitors, fs, fb and fd are put, float ate-source, -bulk and -dra capacitor, respectively. d is fd fb d Fi. 11. One-put Quasi-Float ate NMOST: a) sybolic, b) its equivalent circuit and c) layout. Fi. 1. Quasi-Float ate MOST: a) coon source aplifier with sle put teral, b) sall sal odel equivalent of (a). The dra current of the coon source aplifier Fi. 1 versus its ate-source voltae, coparison with the dra current of the coon source aplifier Fi. (a) is shown Fi. 13. It is notable that the threshold voltae requireents have been reoved fro the sal way us the QFG-MOST. Attention ust be attracted to the float ate voltae V QFG level; this voltae should be at the rane where the p-n junction of the diode connected transistor M R is still reverse biased [4].

8 4 F. KHATEB, S. BAY ABO DABBOUS, S. VLASSIS, A SURVEY OF NON-ONVENTIONAL TEHNIQUES FOR LOW-VOLTAGE Assu that R lk is extreely lare, then the sall sal put current is: If the current throuh ( d fs fd ) i s vs fd is nelected then: i out, s. (30) v. (31) Fro (30) and (31) the current a can be found: Fi. 13. Dra currents versus ate-source voltaes of QFG- MOST and -MOST. The ective transconductance of the QFG-MOST is iven by:, (8) where is the transconductance seen fro the float ate. The ective transconductance of QFG-MOST is larer than the ective transconductance of FG-MOST, however still saller than the transconductance of conventional -MOST as it is obvious fro Fi. 13. It is notable fro Fi. 1(b) that the put is hih pass filter; its cut-off frequency is iven by: fcut off 1 Rlk,. (9) The cut-off frequency should be extreely sall for properly operation at the applications where the low frequencies are needed. Hence the value of R lk ust be lare enouh the order of Gia ohs. To calculate transition frequency of QFG-MOST, let s consider the ac circuit and its sall sal equivalent circuit Fi. 14: i d FG R lk i (a) (b) V fd V =V s d R lk fs, V s + M QFG Fi. 14. ircuit to calculate transition frequency of QFG- MOST: a) ac scheatic, b) sall sal equivalent circuit. i out i out i out,. (3) i ( d fs fd ) s By follow the sae steps that were done previously, then the transition frequency equation of QFG-MOST is:. ft. (33) QFG ( d fs fd ) Assue that fs is uch reater than fd and copensate the ective transconductance fro (8), then the transition frequency can be expressed by: ft. (34) QFG ( ) fs d The put referred noise of the QFG-MOST is siilar for to that of FG-MOST, sce the put sal path both MOSTs is the sae, then: v noise, QFG. (35) As it is clear QFG-MOST suffer fro hiher put referred noise than -MOST, however, the put referred noise of QFG-MOST is saller than it of FG-MOST, sce,qfg <,FG. The ective output conductance of QFG-MOST is reater than the ective output conductance of FG- MOST, and it is iven by the sae for of the FG-MOST conductance: fd ds. ds. (36) The QFG-MOST has alost the sae advantaes as the FG-MOST, besides: There is no itial chare trapped at the float ate. Saller occupied chip area than FG-MOST. The ective transconductance and transition frequency are relatively hiher than the ective transconductance and transition frequency of FG-MOST, but they are still saller than the transconductance and transition frequency of the conventional - MOST.

9 RADIOENGINEERING, VOL., NO., JUNE Soe drawbacks coe with QFG-MOST techniques, such as: Greater ective output conductance than the ective output conductance of FG-MOST and the output conductance of -MOST. Float ate voltae ust not exceed the cut- voltae of the p-n junction of the diode connected transistor M R. 3. Exaple of Application (Operational Transconductance Aplifier OTA) To illustrate the ipleentation prciple of non-conventional techniques analo circuit des, these techniques are used this section to build three LV LP Miller OTAs with the sae voltae supply, power consuption and transistors aspect ratios. However, the differential pair transistors are different i.e. BD-PMOST, FG-PMOST and QFG-PMOST to clarify the perforances of each technique. A coparison study between the ost iportant characteristics of the three OTAs is presented as well. Sce operational transconductance aplifier is an iportant block used any applications and structures, it has been chosen as an exaple of non-conventional techniques application. Actually, Miller OTA coposite of cascade of two staes, first stae is a differential aplifier with PMOS put transistors (M 1, M ), see Fi. 15, and the current irror (M 3, M 4 ) act as an active load. The second stae is a siple coon source aplifier with transistor M 6 act as driver and M 7 as an active load, its output connected to its put throuh the copensation capacitor c and resistor R c, this capacitor act as Miller capacitance, without it the circuit is not stable [6]. The bias current I b and transistors M 8, M 5, M 7 provide the bias currents needed for the first and second stae of OTAs. Utiliz the non-conventional techniques as put devices of the differential aplifier at the first stae, LV LP OTAs can be achieved. Three Miller OTAs based on non-conventional techniques are depicted Fi. 15, bulk-driven OTA (a), float-ate OTA (b) and quasi-float-ate OTA (c). In the bulk-driven OTA, the ate terals of BD- PMOSTs (M 1, M ) are tied to V ss to provide sufficient bias voltae, the put sals are applied at bulk terals Fi. 15(a). Float-ate OTA is desed by ipleentation of two FG-PMOSTs (M 1, M ) with two control ates. The bias voltae V ss is applied at one of control ates of each transistor. The put sals are applied at the second control ate as it is shown Fi. 15(b). The third OTA has two QFG-PMOSTs with sle put teral as put devices; the float ates of the QFG-PMOSTs are tied throuh reversed-biased diode connected transistors (M 9 and M 10 ) to V ss, while put sals applied to the put terals as shown Fi. 15(c). Fi. 15. LV LP Miller OTA based on: a) BD-MOST, b) FG- MOST and c) QFG-MOST. The siulation results of the described OTAs are suarized Tab. 1, and the transistors aspect ratios are listed Tab.. It is notable that the proposed OTAs offer hih perforance LP LV operation, where the power consuption is reduced to about 3.5 μw and the power supply is ± 0.4 V. Besides relatively hih output ipedance, wide put voltae rane and phase ar hiher than 60º are obtaed, hence the proposed OTAs ensure stability. In Fi. 16 the frequency responses for each OTA are depicted; as well the GBW, the a and the phase values at the unity a frequency are shown. The output sals of a voltae follower connected OTA are shown Fi. 17, the put se wave has 100 V aplitude and 10 khz frequency. By copar the basic paraeters fro Tab. 1, it is evident that the best perforances are offered by QFG-OTA then FG-OTA. However, due to the put and bias capacitances the chip area of the FG and QFG-OTAs is larer than the BD-OTA.

10 44 F. KHATEB, S. BAY ABO DABBOUS, S. VLASSIS, A SURVEY OF NON-ONVENTIONAL TEHNIQUES FOR LOW-VOLTAGE haracteristics Bulk-driven OTA Float-ate OTA Quasi-float-ate OTA Power consuption [μw] Phase ar [º] Output ipedance [k] Offset voltae [V] Dynaic rane [V] -100 to to to 400 MRR [db] GBW [MHz] Ga [db] Slew rate [V/s] Measureent conditions: V DD = 0.4V, V SS = -0.4V, c = L =1 pf, = bias =1 pf, R c =7k, I b =6 A Tab. 1. The siulation results of three LV LP Miller OTAs. Vout, V [V] Vout, V [V] Vout, V [V] Fi. 17. Output voltae and put voltae of the OTA based on: a) Bulk-driven transistor, b) float-ate transistor, and c) quasi-float ate transistor. Fi. 16. Frequency response of the OTA based on: a) Bulk-driven transistor, b) float-ate transistor, c) quasi-float ate transistor. Transistor W/L [μ/μ] M 1, M 1/0.6 M 3, M 4 1/0.6 M 5, M 7 8/0.6 M 6 4.9/0.6 M 8 4/0.6 M 9, M 10 4/1 Tab.. The transistors aspect ratios of the OTAs Fi. 15.

11 RADIOENGINEERING, VOL., NO., JUNE Threshold voltae Transconductance - W VT VT 0 F v F ( v V ) MOST K L s T BD- MOST FG- MOST reoved VT Vbiask VT, FG k1 reduced or reoved b b,, ox ( ) ( ) Transition frequency ft s Output conductance ds I ds b ftb ds Ids ub ft FG ( bias fs ) d ds, ds Input referred noise i BD b BD ( 6 5) FG FG (.7 4) QFG- MOST VT Vbiask VT, FG k1 reduced or reoved,, ( ) f T QFG d ( fs d ) ds, ds QFG QFG ( 1. ) Tab. 3. Ma paraeters suary of non-conventional techniques. 4. onclusions This paper presents the prciple of non-conventional techniques for LV LP analo circuit des; the a paraeters of non-conventional techniques were clarified and also suarized Tab. 3 to ake the reachable. Furtherore, their advantaes and disadvantaes were listed, thus one can use appropriate technique for tended analo circuit des. In spite of that the non-conventional techniques offer des siplicity with hih perforance, low voltae and low power operation, soe drawbacks coe with these techniques, aly, the reduction of the a bandwidth, transconductance and the output ipedance ( FG-MOST and QFG-MOST case). Fally, to deonstrate the ipleentation way, OTAs based on non-conventional techniques are presented. The siulation results of LV LP OTAs Fi. 15 show attractive results such as: low supply voltae ± 0.4 V; low power consuption close to 3.5 μw, ood stability, and hih dynaic voltae rane. Thus the non-conventional techniques are utilized successfully LV LP applications. Acknowledeents The described research was perfored laboratories supported by the SIX project; the reistration nuber Z.1.05/.1.00/03.007, the operational prora Research and Developent for Innovation and has been supported by the zech Science Foundation as project No. GA10/11/1379, and by the Mistry of Industry and oerce under the contract FR-TI3/485. References [1] ISMAIL, M., SAKURAI, S. Low-voltae MOS Operational Aplifiers Theory, Des and Ipleentation. Kluwer Acadeic Publishers, 001. [] SAKURAI, T., MATSUZAWA, A., DOUSEKI, T. Fully-depleted SOI MOS ircuits and Technoloy for Ultralow-power Applications. Japan: Sprer, 006. [3] URBAN,. S., MOON, J. E., MUKUND, P. R. Des bulkdriven MOSFETs for ultra-low-voltae analoue applications. Seiconductor Science and Technoloy 010, vol. 5, p [4] RODRIGUEZ-VILLEGAS, E. Low Power and Low Voltae ircuit Des with the FGMOS Transistor. London: Institution of Eneer and Technoloy, 006. [5] KHATEB, F., BIOLEK, D., KHATIB, N., VAVRA, J. Utiliz the bulk-driven technique analo circuit des. In IEEE 13th International Syposiu on Des and Dianostics of Electronic ircuits and Systes. Vienna (Austria), 010, p [6] MALOBERTI, F. Analo Des for MOS VLSI Systes. Dordrecht: Kluwer Acadeic Publishers, 001. [7] RAJPUT, S. S., JAMUAR, S. S. Low voltae analo circuit des techniques. IEEE ircuits and Systes Maaze, 00, vol., no. 1, p [8] URBAN,. S., MOON, J. E., MUKUND, P. R. Scal the bulkdriven MOSFET to deca-nanoeter bulk MOS processes. Microelectronics Reliability, 011, vol. 51, no. 4, p [9] DALY, J.., GALIPEAU, D. P. Analo BIMOS Des Practices and Pitfalls. USA: R press LL, 000. [10] GUZINSKI, A., BIALKO, M., MATHEAU, J.. Body-driven differential aplifier for application contuous-tie active - filter. In Proc. ED. Paris (France), 1987, p [11] KHATEB, F., KAAR, F., KHATIB, N., KUBÁNEK, D. Hihprecision differential-put buffered and external transconductance aplifier for low-voltae low-power applications. ircuits, Systes, and Sal Process, 01, vol. 31, p

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