Boris Krnic Nov 15, ECE 1352F. Phase Noise of VCOs

Transcription

1 Boris Krnic Nov 15, ECE 135F Phase Noise of VCOs. ABSTRACT The ain purpose of this paper is to present siplified first order noise analysis techniques as applied to ring VCOs. The scarcity of literature on the topic as well as industry trends ade e decide to focus solely on the ring oscillator topology. Most of the published work in this area has been done by B.Razavi. A.Hajiiri has done quite a lot in the theoretically ore advanced and general VCO noise analysis. The paper begins by a brief otivation for low phase noise VCOs, and a few short coents on three VCO classes. Presented next are siplified linear, first-order phase noise and jitter analyses that nevertheless provide significant insight into the governing noise echaniss with very reasonable accuracy. Certain low noise VCO design and siulation issues are looked at next. The following section provides a brief look at the underlying tie-variant oscillator theory and cyclostationary statistics needed for a ore rigorous phase noise treatent of a general VCO. Further insight is offered into VCO design, including the ring oscillator topology. Lastly, conclusions are provided. 1

2 1. Need for Low Phase Noise VCOs Phase noise results in spectral ipurity of the VCO output frequency. This is anifested as unwanted jitter ipacting the tiing accuracy in applications where precise phase alignent is required. In cases where frequency translation is perfored, the SNR is affected by the introduction of energy at unwanted phase noise frequencies close to the carrier. High-speed digital circuits like icroprocessors and eories utilize phase locking at the board-chip interface to align the on-chip clock to the syste clock. Usually fabricated on the sae substrate and typically operating fro global supply and ground busses, a PLL will suffer fro substrate and supply noise. This noise is seen in for of jitter as already entioned, priarily through various echaniss in the VCO. The fact that a yriad of high-speed digital, analog and RF circuits utilize PLLs for frequency synthesis, clock recovery, skew suppression and counication channel jitter reduction deonstrates the need for low phase noise VCOs.. Coparison of Oscillator Types A. Haronic Oscillator A haronic oscillator is equivalent to two energy storage eleents, operating in resonance, producing a periodic output signal. The resonant eleent can be an LC-tank or a quartz crystal. Resonant circuit-based VCOs are known to have excellent jitter perforance. Analysis of noise in resonant-based VCOs is well developed in literature, and design techniques for realizing low jitter perforance are well understood. An exaple LC-oscillator is shown in Fig.. There are a few

3 disadvantages for onolithic ipleentation of this circuit; 1) both the control and the output signals are single-ended aking the circuit sensitive to supply/substrate noise; ) the required inductor and varactor Q is usually greater than off-chip coponents are needed. Another possibility is the use of integrated inductors that are generally large and exhibit low Q factors due to resistive losses. Advances in processing certainly allow the use of integrated inductors for certain, but not all applications. Fig. B. Relaxation Oscillator A relaxation oscillator is equivalent to one energy storage eleent, with additional circuitry that senses the eleent state and controls its excitation to produce a periodic output signal. The jitter perforance of this type of oscillator is worse than that of the haronic oscillator, but the circuit is suitable for onolithic integration. C. Ring Oscillator The trend toward large-scale integration and low cost akes onolithic oscillators very desirable. Due to their speed and ease of integration, ring oscillators are 3

4 increasingly being used as voltage controlled oscillators. Soe exaples where they find use are in clock recovery phase-locked loops for serial data counication, disk drive clock recovery, clock frequency ultiplication, oversapling analog-to-digital converters However, it was only in the id-nineties that ore rigorous phase noise analyses appeared along with experiental verifications of their predictions. 3. Noise Shaping in a Linear Oscillatory Syste When a circuit begins to oscillate, the aplitude grows until it is liited by soe nonlinear echanis. In typical configurations, the open-loop gain of the circuit drops as signal swings becoe large thus preventing further growth of aplitude. Presented next is the derivation of the noise shaping function assuing the oscillator is a linear feedback syste as shown in Fig 1. Fig. 1 The transfer function for the syste in fig. 1 is presented as: Y X ( jω) = H ( jω) H ( jω) + 1 (1) The denoinator of (1) goes to infinity for a circuit oscillating at ω if H ( jω ) = 1. For frequencies close to the carrier frequency, i.e., ω = ω + ω, the open loop transfer function can be approxiated as H = H + H assuing ω is sall. 4

5 dh H ( jω) = H ( jω ) + ω dω Y X 1 dh, assuing ω << 1 dh d ω ω dω [ j( ω + ω )] () which is true for ost practical cases. Fro (), we conclude that the noise power spectral density is shaped by Y X This is shown in Fig. [ j( ω ω )] 1 + = (3) dh ( ω) dω Fig. As already entioned above, the noise shaping function was derived using a linear-tie-invariant odel of the oscillator that is an inherently tie-variant, linear syste, if aplitude liiting is ignored, [1]. The validity of this approach is discussed in [1]. The key point to bear in ind is that (3) is a siple odel that yields reasonable accuracy. One odel will not be appropriate for any oscillator type, therefore the designer needs to understand when this odel is applicable and when it is not. Its accuracy ust ultiately be checked through siulations. 5

6 4. CMOS Ring Oscillator Phase Noise Approach A fully differential three-stage ring oscillator is shown in Fig 3a. Both the control and the output signals are fully differential to achieve high coon-ode rejection. (b) possible ipleentation of one ring oscillator stage Fig 3. Fig 4. depicts a linearized VCO odel that can be used for first-order phase noise analysis. Fig 4. 6

7 The odel consists of the stage output resistance R, load capacitance C, equivalent stage transconductance G and input-referred current noise sources injected into all nodes. The noise sources incorporate both theral and shot noise. Since each stage is represented as a first-order linear syste, its transfer function can be expressed as H 1,,3 G R ( jω) = where G R is the dc stage gain and ω the ω 1+ j ω oscillation frequency. Recalling that to sustain steady oscillations, total loop-gain equal to unity and total phase shift around the loop of 36 at ω are necessary. This iplies that each stage contributes 1 of phase shift resulting in ω = 3 RC. The stage transfer function now becoes, H 1,,3 G R ( jω) =. Since H ( jω ) = 1 is the second ω 1+ j 3 ω oscillation condition, it iplies that G R =. Finally, the total open-loop transfer 8 function of the three-stage ring oscillator can be written as H ( jω) =. 3 ω 1 + j 3 ω It follows fro (3), that if a noise current I n1 is injected into node 1, its power spectru V I 1 is shaped by: [ j( ω + ω) ] n1 = R ω 7 ω (4) This equation is key to predicting various phase noise coponents in the ring oscillator. 7

8 4.1 Linearized Model Issues The odel presented in Fig 4. was an oversiplification of the oscillator. Oscillator stages turn on and off during the oscillation period suggesting that G, R and C paraeters are not constant as assued in the derivation of (4). Secondly, the linear odel doesn t predict ixing effects resulting fro nonlinearities, and thirdly it doesn t account for cyclostationary device noise behavior. The cyclostationary behavior, i.e., periodically tie varying statistics (ean, autocorrelation ) result fro the fact that the circuit bias conditions are a function of tie. 4. Additive Noise The additive noise is the noise due to sources I n1 3 that can directly be added at the output. Assuing equivalent noise sources and a noise frequency close to ω such that the stage gain unity, the total contribution of I n1 3 at the output is V R ω ω (5), where 9 ω [ j( + ω )] = ntot I n I n represents both theral and shot noise. The profile of (5) suggests that additive noise is significant only at frequencies close to ω. 4.3 High-Frequency Multiplicative Noise Circuit nonlinearity when successive stages turn off during oscillations causes noise coponents to be ultiplied by the oscillator signal. The output signal can always be odeled by higher order polynoial ters such as 3 Vout = a Vin + a Vin + a Vin a n Vin 1 3 n 8

9 The input signal in presence of noise can be written as Vin t) = A cosω t A cosω t. ( + Substituting Vin(t) into the expression for Vout, we see that frequency ixing occurs. In case of a fully differential configuration, a =, so that only the 3 Vin ter is significant yielding Vout a A A cos ( ω ω )t. The high-frequency ultiplicative noise effect α 3 is ost significant for 3 n n ω n close to ω. This is illustrated in Fig 5. n n Fig Low-Frequency Multiplicative Noise In stage ipleentation of Fig 3b. the ring oscillator frequency of oscillation is a function of the tail current. Any noise in the current source will anifest itself at the output as frequency odulation. In this case, low frequency concern. 1 f noise is of ost Assuing that the output voltage takes the shape of an FM odulated signal, steing fro a sinusoidally odulated oscillator free running frequency and classically expressed by Vout Kvco t) = A t + I t cos ω sin ω, where ω is the frequency of the ω ( odulating noise signal, then using a sall angle approxiation,i.e., Kvco ω << 1, I 9

10 Vout A I Kvco A cos ω t + [ cos( ω + ω ) t cos( ω ω ) t], (6) ω (6) represents frequency convolution and is depicted in Fig 6. Fro Fig. 6 it becoes obvious that Fig 6. 1 f noise contribution at low frequencies becoes extreely significant for two reasons. First, the aplitude of the two delta functions at ± ω will be higher (due to the 1 f noise profile). Second, the saller the spacing ω ± ω, the higher the aplitude of the noise shaping function will be. These two effects are ultiplicative thus accentuating the low-frequency noise at the output. 5. CMOS Ring Oscillator Tiing Jitter Approach In this section two additional oscillator noise sources will be presented, naely the supply and substrate noise whose effects are traditionally expressed and analyzed in the tie doain in ters of signal edge uncertainty tiing jitter. One of the coonly used figures of erit for oscillators is the cycle-to-cycle jitter illustrated in Fig 7. Fig 7. 1

11 The rs value of this tiing error is given as T = li ( T T ) cc N 1 N N n= 1 n+ 1 n and represents the rs difference between two consecutive periods. 5.1 Phase Noise/Jitter Relation Phase noise and jitter are frequency doain and tie doain quantities representing the oscillator frequency uncertainty. As deonstrated in [], the two 4π 3 ω quantities can be related by S ( ω )( ω ω ) T cc where φ T cc represents the cycle-to-cycle jitter variance and Sφ is the noise shaping power spectral density function. 5. Jitter due to Supply/Substrate Noise There are two ajor effects that convert the supply and substrate noise to jitter. Depicted in Fig 8. are the nonlinear MOS drain capacitances Cdb, whose capacitance is a function of Vdd and Vsub. The second effect is the finite coon-ode rejection of the stage inverter. Fig 8. 11

12 As the drain junction capacitances vary with noise on supply/substrate, they odulate the frequency of the ring oscillator. An oscillator under the influence of such environental noise can be thought of as a VCO having different control voltages. The variation of oscillation frequency with a control voltage can be described by a sensitivity function Kvco as follows: assuing the odulating control voltage is a sall sinusoidal disturbance of the for V ( t) = V cosω t and recalling that the VCO frequency is ideally given by f out = f + K V, it follows that the frequency change generated is vco cont f o ( t) = V K cosω t vco. The change in frequency as a function of tie can be converted into an equivalent change in period as a function of tie that can be further used to deterine the autocorrelation function. In [], using the cycle-to-cycle jitter variance defined in ters of its autocorrelation function, it is shown that the cycle-to-cycle jitter is V K cc for f << f we have f vco given by T = 1 cos( ω f ) V K vcoω Tcc (7) 3 f Fro (7) it is evident that the jitter equation is a function of noise aplitude, noise frequency, oscillator frequency and the sensitivity function K vco. The sensitivity can be extracted fro siulations by sweeping the supply and substrate voltages and observing the influence on output frequency. It is further reported in [], that the single-ended ring oscillator has a uch higher sensitivity to supply/substrate noise than the differential design which is an expected result. Coupled with the fact that differential designs have uch better coon-ode rejection, a fully differential ring oscillator, such as that of 1

13 Fig 3. is preferred. It is also interesting to note that jitter is directly proportional to supply/substrate noise aplitude (within a few hundred V) and frequency. 5.3 Low Jitter Oscillator Design Input Transistor Gate Width A slightly different approach was taken in [3], where the cycle-to-cycle jitter was shown to be inversely proportional to the tail current and the overdrive voltage. It follows that for low jitter designs, the overdrive voltage should be as large as possible within the allowable liits of course. This can be achieved by a large tail current and low aspect ratio. In [], the gate width effect on jitter was forulated differently. There, the input transistors widths were varied while an independent load capacitance was adjusted so that the oscillation frequency was kept constant at all ties. This resulted in an optial input transistor width, For values greater than w opt, at which the corresponding jitter was iniu. w opt the jitter increases. The ethod used in [] is interesting because it copares various transistor width effects at the sae oscillation frequency, thus setting a coon reference point for the coparison. It can further be analyzed as follows: for the sake of arguent we can represent the internal node capacitance as C + i = Cout( i) + Cin( i+ 1) Cload where C C + C out( i) db gd, and in i+ 1) gs gd C ( C + C, and C load is the adjustable capacitor to keep the oscillation frequency constant. Now, assuing that the transistor width is scaled by k, then both the C in( i+1) and C out(i) will roughly scale by k since Cgs WLCox (not exactly equal due to fringing effects) and C db WLdiffusionCj + WCjsw (assuing 13

14 W >> Ldiffusion ). This eans that the input and output capacitance su at the internal node will increase by ( k )( C in + C ) +. In order to keep the oscillation frequency 1 ( i 1) out( i) the sae, C needs to be decreased by ( k )( C in + C ) load +. Therefore the su 1 ( i 1) out( i) C + out( i) + Cin( i+ 1) Cload is always constant. If we now define the node capacitance sensitivity ratio l = nonlinear _ cap linear _ cap C C db tot we see that as the width is increased by k, the ratio l is increased by k as well. Since the nonlinear capacitor contribution grows as the width is increased, the output frequency is odulated ore strongly due to supply/substrate noise and we expect to see larger resulting jitter which is exactly what is reported in []. This result also atches what has been reported in [3], except that it points to an optial width rather than as low as possible width Power Consuption Using the result fro [3], the jitter can be iniized by increasing the tail current Iss, thus increasing the power consuption. This result was to be expected. It can further be illustrated as follows: if we assue that N identical oscillator outputs are added in phase and that they exhibit only the device electronic noise, then the signal power will be increased by N and the noise power will be increased by N since all the noise sources are uncorrelated (resulting noise voltage α N ). This thoughtexperient shows that if power is increased by N, the power-to-noise ratio is increased by N. On the other hand if we consider the sae scenario with supply/substrate noise we note that signal power will increase by N, but so will the noise power since the sae supply/substrate noise affects each oscillator noise is correlated. The iportant 14

15 conclusion is that that supply/substrate noise effect on jitter is relatively independent of the power consuption. Therefore, the supply/substrate induced jitter ust be eliinated by circuits with iproved positive/negative power-supply rejection. This can be accoplished by using fully differential stages and by using cascode current sources if there is enough voltage swing available. Also, the supply/substrate jitter can be decreased by careful layout techniques such as guard rings, low resistance/inductance supply lines Effect of the Nuber of Stages In applications where the required oscillation frequency is considerably lower than the technology axiu speed, a ring oscillator with ore than three stages can be used. If the oscillation frequency is deterined by both the parasitic and load capacitances, as described in section 5.3.1, the three-stage design is better. If an n-stage N design is designed to oscillate at f, the 3-stage design would want to oscillate at 3 f if all other conditions are the sae. In order to reduce the 3-stage design frequency to that of the n-stage design, we can accoplish that by increasing the load capacitance. In doing so, we decrease the effect of the parasitic nonlinear capacitor at the internal nodes, thus aking these nodes less susceptible to supply/substrate voltage variations which results in lower jitter. 15

16 6. Siulation The tie-varying nature of oscillators prohibits the use of standard sall-signal ac analyses used in SPICE. For this reason, siulations ust be perfored in the tie doain. It is further recoended in [1] to use sinusoidal noise sources as for exaple square wave noise source ay result in an incorrect spectru exhibiting coherent sidebands due to errors in interpolation. To siulate the phase noise effects, noise sources at a frequency offset ω n are injected at various circuit nodes and the spectru is constructed for each case. The linear superposition of all resulting spectra yields the final total output spectru. Finally in [1], a first order ethod is presented that roughly accounts for the cyclostationary noise behavior, by replacing the sinusoidal noise current source by a nonlinear voltage-controlled noise current source. The reported difference between the two scenarios was.5db. 7. Tie-Variant Oscillator Approach In [1], a ore advanced oscillator odel is introduced. It starts by noting that in an oscillator, each noise perturbation affects both the aplitude and the phase of the output signal. Being tie-variant, this effect depends on the tie at which the ipulse is applied. Therefore a odel is used where the input is a current or voltage ipulse and the corresponding output is the excess phase generated. For exaple, in a parallel LC tank, a current ipulse at the input only affects the voltage across the capacitor with no effect on the current through the inductor. This results in an instantaneous change in the tank voltage and hence a shift in the aplitude and phase depending on the tie of 16

17 injection. For a linear capacitor, the instantaneous voltage change V is equal to q C, where q is the total charge injected by the current ipulse. As already entioned the change in aplitude and phase due to the input ipulse is tie-variant. If the ipulse is applied at the peak voltage across the capacitor, it will result in an instantaneous aplitude change, but there will be no phase shift. On the other hand, if the ipulse is applied at a zero crossing, it has a axiu effect on the excess phase, φ ( t), but a iniu effect on the aplitude, ( t) A. The current ipulse at t = τ generates a step change in phase. For a sall injected charge, the phase shift is proportional to the V injected charge = Γ( ω τ ) = Γ( ω τ ) q φ where Vax q V,q ax ax ax are the axiu voltage swing and its corresponding charge. The function Γ ( x), is the tie-varying, frequency and aplitude independent proportionality factor, called the ipulse sensitivity function, ISF. It deterines the sensitivity of the oscillator to an ipulse input by describing the aount of excess phase shift generated at any point in tie. Various oscillators therefore exhibit different ISFs. The iportant point to note is that the current-phase transfer function is linear for sall injected charge, even though the active eleents ay be strongly nonlinear. Device nonlinearity does however directly affect the shape of the ISF which results in different influences on phase noise. Therefore, for a sall charge injected, the equivalent syste phase responses can fully be characterized using their linear tie-variant phase unit ipulse responses: h φ ( t τ ) ( ω τ ) u ( τ ) Γ, = t. q ax 17

18 The phase response, φ ( t), can be found by convolving the ipulse-phase response with the current/voltage input disturbance, i.e., ( ω oτ ) i ( τ ) τ t Γ φ( t) = hφ ( t, τ ) i( τ ) dτ = d, (8) q ax It is shown in [1], that since the ISF is periodic, it can be expanded into Fourier series by Γ ( ω τ ) = c ( nω τ + Θ ) n= n cos By exchanging the order of integration and suation, it can be shown that individual contributions to the total excess phase, for an arbitrary current input, can be identified in ters of various Fourier coefficients of the ISF. The result is that perturbations in the vicinity of integer ultiples of the carrier frequency ost significantly affect the total excess phase, φ ( t). The above theory predicts that flicker noise, weighted by the 3 coefficient c produces a 1 f phase noise region and the weighted white noise ters give rise to a 1 f phase noise region. The result of this ore involved analysis is that extra phase noise regions exist and that their contribution at low frequencies is uch higher than that of flicker noise alone, which is iportant in oscillator low-frequency ultiplicative noise resulting fro the current source odulation. The ISF is ost conveniently found through siulations. An added coplication in analyzing general VCOs is the fact that soe of the rando noise sources change periodically in tie, i.e., they are cyclostationary. For exaple the channel noise of a MOS device operating in an oscillator is cyclostationary because n periodically tie-varying gate-source voltages odulate the drain noise power. A 18

19 cyclostationary current i n ( t) can be expressed as i ( t) = i ( t) α( t), where ( t) n n ω i n is a white stationary process and α ( ω t) is a deterinistic periodic function describing the noise aplitude odulation and is referred to as the noise odulating function, NMF. 7.1 Ring Oscillator fro a Tie-Variant Perspective The ring oscillator Q is very poor since the energy stored in the node capacitances is reset every cycle. The energy restoration to the resonator occurs during the edges which are the worst possible ties. These factors account for, as stated in [1], terriblenoise perforance. As a consequence, ring oscillators are found only in the ost noncritical applications, such as wide-band phase-locked loops whose dynaics clean up the spectru. Fro the ISF analysis of the excess phase, assuing correlated noise sources, it follows that the ISF is zero except at dc and ultiples of the oscillation frequency. Every effort should therefore be ade to axiize the correlations of supply/substrate noise. This can be achieved by proper layout techniques, by aking the delay stages as siilar as possible. Another interesting result of the ISF analysis regards the choice of the singleended versus differential oscillator design. It is found that the phase noise of the singleended design is independent of the nuber of stages, whereas that of the differential design is not. For a given power consuption, the single-ended design outperfors the differential design since its power dissipation occurs on a per transition basis, whereas that of its differential counterpart is independent of the nuber of transitions. In reality, 19

20 the differential topology is still preferred due to its lower sensitivity to the supply/substrate noise and lower noise injection into other circuits on the sae chip. Since jitter is independent of the nuber of delay stages in a single-ended design, a larger nuber of stages will reduce jitter for a given oscillation frequency and power consuption, especially if good syetry is not achieved and the process has a large flicker noise. For differential designs, where jitter increases with the nuber of stages, optial jitter perforance will be achieved with a three or four stage design. This is in agreeent with conclusions drawn in []. 8. Conclusions There are a few contradictions between references used in this paper. For instance, in [] it is claied that supply/substrate noise is a uch greater contributor of jitter in ring oscillators, whereas [3] has focused on device electronic noise, providing the arguent that supply/substrate noise can be iniized by careful design and layout. I would tend to agree ore with results presented in [], due to the fact that designs are becoing ore integrated, ore coplex with voltages scaled down and frequencies scaled up, I would expect supply/substrate to be quite noisy, if not noisier. Also, device transconductances are decreasing with new technologies, thus decreasing theral noise, further accentuating the effect of supply/substrate noise. Another contradiction found was between [1] which clais that ring oscillators have very poor phase noise characteristics and are thus used in non-critical applications, whereas in [6], their potential is rated as excellent. Given that the work presented in [1] is uch ore rigorous and ore recent it is probably ore valid.

21 Lastly, a refutation of high-frequency ultiplicative noise described in [1] was presented in [1]. Despite the apparent shortcoings, the linearized approaches [1]-[6] have all shown good agreeent between predicted, siulated and experiental results. In [1], for instance, less than.db discrepancy was obtained between the linearized odel and siulations for two three-stage VCO topologies (ring-oscillator and relaxation oscillator). Excellent predicted versus siulated jitter characteristics have been reported in []-[3] using linear odels. The key point to reeber is that the linearized odel is not a panacea. It provides good agreeent for ring oscillators of the topology as shown in Fig 3. and perhaps certain relaxation oscillators. Even within the real of ring oscillators, if the delay stage circuit is significantly changed one ust ake sure that the odel is still applicable. Also, as the nuber of stages increases, the odel of section 4. loses accuracy. It was reported in [1], that the discrepancy between the predicted and siulated results grew fro.db to 1dB for a four stage design and to 6dB for an eight stage design. Therefore, it is up to the designer to understand the design and carry out the necessary verifications. Nevertheless, the linearized ethod is still very attractive due to its siplicity. It can be used as an excellent analysis starting point, alost for back-ofthe-envelope calculations. Siulations ultiately show whether it is adequate or ore advanced techniques, naely ISF and cyclostationary statistics need to be evoked. For an LC-tank VCO, tie-variant ethods ust be used, as one siply cannot get away with the linearized odels. 1

22 9. References [1] B.Razavi, A Study of Phase Noise in CMOS Oscillators, JSSC, Vol.31, No.3, March 1996, pp [] B.Razavi, F.Herzel, A Study of Oscillator Jitter Due to Supply and Substrate Noise, IEEE, Vol. 46, No.1, Jan 1999, pp [3] Todd C. Weigandt, B.Ki, Paul R. Gray Analysis of Tiing Jitter in CMOS Ring Oscillators, pp. 7-3 [4] B.Razavi, Analysis, Modeling, and Siulation of Phase Noise in Monolithic Voltage-Controlled Oscillators, IEEE, 1995 pp [5] B.Razavi, F.Herzel, Oscillator Jitter Due to Supply and Substrate Noise, IEEE, 1998, pp [6] John A. McNeill, Jitter in Ring Oscillators, JSSC, Vol. 3, No.6, June 1997 pp [7] W.Bereza, Iproved Power-Supply Rejection in Voltage-Controlled Oscillators, Journal Paper, Nortel Networks, pp. 1-4 [8] T. Brown, VCO Notes [9] B. Razavi, Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits A Tutorial, [1] A.Hajiiri, Thoas H. Lee, Oscillator Phase Noise: A Tutorial JSSC, Vol. 35, No.3, March, pp