ICL7106, ICL7107, ICL7107S

Transcription

1 ICL06, ICL0, ICL0S Data Sheet July 5, 2005 FN / 2 Digit, LCD/LED Display, A/D Converters The Intersil ICL06 and ICL0 are high performance, low power, 3 / 2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL06 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed ackplane drive; the ICL0 will directly drive an instrument size light emitting diode (LED) display. The ICL06 and ICL0 ring together a comination of high accuracy, versatility, and true economy. It features autozero to less than 0µV, zero drift of less than µv/ o C, input ias current of 0pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, ut give the designer an uncommon advantage when measuring load cells, strain gauges and other ridge type transducers. Finally, the true economy of single power supply operation (ICL06), enales a high performance panel meter to e uilt with the addition of only 0 passive components and a display. Features Guaranteed Zero Reading for 0V Input on All Scales True Polarity at Zero for Precise Null Detection pa Typical Input Current True Differential Input and Reference, Direct Display Drive LCD ICL06, LED lcl0 Low Noise Less Than 5µV PP On Chip Clock and Reference Low Power Dissipation Typically Less Than 0mW No Additional Active Circuits Required Enhanced Display Staility PFree Plus Anneal Availale (RoHS Compliant) Ordering Information TEMP. PKG. PART NO. RANGE ( C) PACKAGE DWG. # ICL06CPL 0 to 0 Ld PDIP E.6 ICL06CPLZ (Note 2) 0 to 0 Ld PDIP (Pfree) (Note 3) E.6 ICL06CM44 0 to 0 44 Ld MQFP Q44.0x0 ICL0CPL 0 to 0 Ld PDIP E.6 ICL0CPLZ (Note 2) 0 to 0 Ld PDIP (Pfree) (Note 3) E.6 ICL0RCPL 0 to 0 Ld PDIP (Note ) E.6 ICL0RCPLZ (Note 2) 0 to 0 Ld PDIP (Pfree)(Notes, 3) ICL0SCPL 0 to 0 Ld PDIP (Notes, 3) E.6 E.6 Ordering Information (Continued) PART NO. ICL0SCPLZ (Note 2) 0 to 0 Ld PDIP E.6 (Pfree) (Notes, 3) ICL0CM44 0 to 0 44 Ld MQFP Q44.0x0 ICL0CM44T 0 to 0 44 Ld MQFP (Tape Q44.0x0 and Reel) ICL0CM44Z (Note 2) ICL0CM44ZT (Note 2) TEMP. RANGE ( C) PACKAGE 0 to 0 44 Ld MQFP (Pfree) 0 to 0 44 Ld MQFP (Tape and Reel) (Pfree) PKG. DWG. # Q44.0x0 Q44.0x0 NOTES:. R indicates device with reversed leads for mounting to PC oard underside. S indicates enhanced staility. 2. Intersil Pfree plus anneal products employ special Pfree material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatile with oth SnP and Pfree soldering operations. Intersil Pfree products are MSL classified at Pfree peak reflow temperatures that meet or exceed the Pfree requirements of IPC/JEDEC J STD Pfree PDIPs can e used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888ERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2004, All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Pinouts ICL06, ICL0 (PDIP) TOP VIEW ICL0R (PDIP) TOP VIEW C B ( s) A F G E D2 C2 B2 (0 s) A2 F2 E2 D3 B3 (00 s) F3 E3 (000) AB4 POL (MINUS) V (0 s) (00 s) BP/GND V (0 s) (00 s) BP/GND C B A ( s) F G E D2 C2 B2 (0 s) A2 F2 E2 D3 B3 (00 s) F3 E3 (000) AB4 POL (MINUS) ICL06, ICL0 (MQFP) TOP VIEW V NC NC NC C B NC BP/GND POL AB4 E3 F3 B3 A F G E D2 C2 B2 A2 F2 E2 D3 2 FN82.6

3 Asolute Maximum Ratings Supply Voltage ICL06, to V V ICL0, to GND V ICL0, V to GND V Analog Input Voltage (Either Input) (Note ) to V Reference Input Voltage (Either Input) to V Clock Input ICL to ICL GND to Operating Conditions Temperature Range o C to 0 o C Thermal Information Thermal Resistance (Typical, Note 2) θ JA ( o C/W) PDIP Package MQFP Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 50 o C Maximum Lead Temperature (Soldering 0s) o C (MQFP Lead Tips Only) NOTE: Pfree PDIPs can e used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses aove those listed in Asolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions aove those indicated in the operational sections of this specification is not implied. NOTES:. Input voltages may exceed the supply voltages provided the input current is limited to ±00µA. 2. θ JA is measured with the component mounted on a low effective thermal conductivity test oard in free air. See Tech Brief TB9 for details. Electrical Specifications (Note 3) SYSTEM PERFORMANCE PARAMETER CONDITIONS MIN TYP MAX UNIT Zero Input Reading V IN = 0.0V, Full Scale = 200mV ± Digital Reading Staility (Last Digit) (ICL06S, ICL0S Only) Fixed Input Voltage (Note 6) ± Digital Reading Ratiometric Reading V ln = V REF, V REF = 00mV / Digital Reading Rollover Error Linearity V IN = V ln 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) ±0.2 ± Counts ±0.2 ± Counts Common Mode Rejection Ratio V CM = V, V IN = 0V, Full Scale = 200mV (Note 5) 50 µv/v Noise V IN = 0V, Full Scale = 200mV (PeakToPeak Value Not Exceeded 95% of Time) 5 µv Leakage Current Input V ln = 0 (Note 5) 0 pa Zero Reading Drift V ln = 0, 0 o C To 0 o C (Note 5) 0.2 µv/ o C Scale Factor Temperature Coefficient V IN = 99mV, 0 o C To 0 o C, (Ext. Ref. 0ppm/ o C) (Note 5) 5 ppm/ o C End Power Supply Character Supply Current V IN = 0 (Does Not Include LED Current for ICL0).0.8 ma End Power Supply Character V Supply Current ICL0 Only ma Pin Analog Common Voltage Temperature Coefficient of Analog Common DISPLAY DRIVER ICL06 ONLY kω Between Common and Positive Supply (With Respect to Supply) kω Between Common and Positive Supply (With Respect to Supply) V 80 ppm/ o C PeakToPeak Segment Drive Voltage PeakToPeak Backplane Drive Voltage = to V = 9V (Note 4) V 3 FN82.6

4 Electrical Specifications (Note 3) (Continued) PARAMETER CONDITIONS MIN TYP MAX UNIT DISPLAY DRIVER ICL0 ONLY Segment Sinking Current = 5V, Segment Voltage = 3V Except Pins 9 and ma Pin 9 Only 0 6 ma Pin 20 Only 4 ma NOTES: 3. Unless otherwise noted, specifications apply to oth the ICL06 and ICL0 at T A = o C, f CLOCK = 48kHz. ICL06 is tested in the circuit of Figure. ICL0 is tested in the circuit of Figure Back plane drive is in phase with segment drive for off segment, 80 degrees out of phase for on segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed y design. 6. Sample Tested. Typical Applications and Test Circuits R R 5 IN 9V R 3 2 C 4 C B 3 4 C R C 5 C R2 4 2 C COM V ICL06 A F G E D2 C2 B2 A2 F2 E2 D3 B DISPLAY F3 E3 AB POL BP C = 0.µF C 2 = 0.4µF C 3 = 0.µF C 4 = C 5 = 0.02µF R = kω R 2 = 4kΩ R 3 = R 4 = kω R 5 = MΩ DISPLAY FIGURE. ICL06 CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 5V 5V IN R R 5 R 3 2 C R C 5 C R2 4 2 C 3 C 4 DISPLAY COM V ICL0 C B A F G E D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB POL GND C = 0.µF C 2 = 0.4µF C 3 = 0.µF C 4 = C 5 = 0.02µF R = kω R 2 = 4kΩ R 3 = R 4 = kω R 5 = MΩ DISPLAY FIGURE 2. ICL0 CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 4 FN82.6

5 Design Information Summary Sheet OSCILLATOR FREQUENCY f OSC = 0.45/RC C OSC > 50pF; R OSC > 50kΩ f OSC (Typ) = 48kHz OSCILLATOR PERIOD t OSC = RC/0.45 EGRATION CLOCK FREQUENCY f CLOCK = f OSC /4 EGRATION PERIOD t = 000 x (4/f OSC ) 60/50Hz REJECTION CRITERION t /t 60Hz or t lnt /t 60Hz = Integer OPTIMUM EGRATION CURRENT I = 4µA FULL SCALE ANALOG INPUT VOLTAGE V lnfs (Typ) = 200mV or 2V EGRATE RESISTOR V R INFS = I EGRATE CAPACITOR ( t )( I ) = C EGRATOR OUTPUT VOLTAGE SWING ( t )( I ) = V V C V MAXIMUM SWING: (V 0.5V) < V < ( 0.5V), V (Typ) = 2V DISPLAY COUNT V IN COUNT = 000 V REF CONVERSION CYCLE t CYC = t CL0CK x 00 t CYC = t OSC x 6,000 when f OSC = 48kHz; t CYC = 3ms MODE INPUT VOLTAGE (V V) < V ln < ( 0.5V) AUTOZERO CAPACITOR 0.0µF < C AZ < µf REFERENCE CAPACITOR 0.µF < < µf V COM Biased etween Vi and V. V COM 2.8V Regulation lost when to V < 6.8V If V COM is externally pulled down to ( to V)/2, the V COM circuit will turn off. ICL06 POWER SUPPLY: SINGLE 9V V = 9V Digital supply is generated internally V GND 4.5V ICL06 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. ICL0 POWER SUPPLY: DUAL ±5.0V = 5V to GND V = 5V to GND Digital Logic and LED driver supply to GND ICL0 DISPLAY: LED Type: NonMultiplexed Common Anode Typical Integrator Amplifier Output Waveform ( Pin) AUTO ZERO PHASE (COUNTS) SIGNAL EGRATE PHASE FIXED 000 COUNTS DEEGRATE PHASE COUNTS TOTAL CONVERSION TIME = 00 x t CLOCK = 6,000 x t OSC 5 FN82.6

6 Detailed Description Analog Section Figure 3 shows the Analog Section for the ICL06 and ICL0. Each measurement cycle is divided into three phases. They are () autozero (), (2) signal integrate () and (3) deintegrate (DE). AutoZero Phase During autozero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog. Second, the reference capacitor is charged to the reference voltage. Third, a feedack loop is closed around the system to charge the autozero capacitor C AZ to compensate for offset voltages in the uffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A Z accuracy is limited only y the noise of the system. In any case, the offset referred to the input is less than 0µV. Signal Integrate Phase During signal integrate, the autozero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage etween and for a fixed time. This differential voltage can e within a wide common mode range: up to V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, can e tied to analog to estalish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. DeIntegrate Phase The final phase is deintegrate, or reference integrate. Input low is internally connected to analog and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will e connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: V IN DISPLAY COUNT = 000. V REF Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V elow the positive supply to V aove the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must e exercised to assure the integrator output does not saturate. A worst case condition would e a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has een used up y the positive common mode voltage. For these critical applications the integrator output swing can e reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Differential Reference The reference voltage can e generated anywhere within the power supply voltage of the converter. The main source of common mode error is a rollover voltage caused y the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to deintegrate a positive signal ut lose charge (decrease voltage) when called up to deintegrate a negative input signal. This difference in reference for positive or negative input voltage will give a rollover error. However, y selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can e held to less than 0.5 count worst case. (See Component Value Selection.) STRAY STRAY R C AZ C ER 0µA EGRATOR 2.8V TO DIGITAL SECTION DE DE INPUT HIGH 6.2V DE DE AND DE(±) N INPUT LOW COMPARATOR V FIGURE 3. ANALOG SECTION OF ICL06 AND ICL0 6 FN82.6

7 Analog This pin is included primarily to set the common mode voltage for attery operation (ICL06) or for any system where the input signals are floating with respect to the power supply. The pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum endoflife attery voltage of aout 6V. However, analog has some of the attriutes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>V), the voltage will have a low voltage coefficient (0.00%/V), low output impedance ( 5Ω), and a temperature coefficient typically less than 80ppm/ o C. V ICL06 ICL0 V FIGURE 4A. 6.8V ZENER I Z The limitations of the on chip reference should also e recognized, however. With the ICL0, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The comination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from µv to 80µV PP. Also the linearity in going from a high dissipation count such as 000 (20 segments on) to a low dissipation count such as (8 segments on) can suffer y a count or more. Devices with a positive TC reference may require several counts to pull out of an overrange condition. This is ecause overrange is a low dissipation mode, with the three least significant digits lanked. Similarly, units with a negative TC may cycle etween overrange and a nonoverrange count as the die alternately heats and cools. All these prolems are of course eliminated if an external reference is used. The ICL06, with its negligile dissipation, suffers from none of these prolems. In either case, an external reference can easily e added, as shown in Figure 4. Analog is also used as the input low return during autozero and deintegrate. If is different from analog, a common mode voltage exists in the system and is taken care of y the excellent CMRR of the converter. However, in some applications will e set at a fixed known voltage (power supply common for instance). In this application, analog should e tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can e conveniently tied to analog, it should e since this removes the common mode voltage from the reference system. Within the lc, analog is tied to an NChannel FET that can sink approximately ma of current to hold the voltage 2.8V elow the positive supply (when a load is trying to pull the common line positive). However, there is only 0µA of source current, so may easily e tied to a more negative voltage thus overriding the internal reference. V ICL06 ICL0 FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE The pin serves two functions. On the ICL06 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can e used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a ma load should e applied. ICL06 BP 20kΩ The second function is a lamp test. When is pulled high (to ) all segments will e turned on and the display should read 888. The pin will sink aout 5mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no squarewave). This may urn the LCD display if maintained for extended periods. MΩ 6.8kΩ ICL8069.2V REFERENCE TO LCD DECIMAL PO TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL PO FN82.6

8 ICL06 BP DECIMAL PO SELECT TO LCD DECIMAL POS asor the relative large capacitive currents when the ack plane (BP) voltage is switched. The BP frequency is the clock frequency divided y 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, ut out of phase when ON. In all cases negligile DC voltage exists across the segments. Digital Section CD GND FIGURE 6. EXCLUSIVE OR GATE FOR DECIMAL PO DRIVE Figures and 8 show the digital section for the ICL06 and ICL0, respectively. In the ICL06, an internal digital ground is generated from a 6V Zener diode and a large PChannel source follower. This supply is made stiff to Figure 8 is the Digital Section of the ICL0. It is identical to the ICL06 except that the regulated supply and ack plane drive have een eliminated and the segment drive has een increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 000 output (pin 9) must sink current from two LED segments, it has twice the drive capaility or 6mA. In oth devices, the polarity indication is on for negative analog inputs. If and are reversed, this indication can e reversed also, if desired. a e f a g c d c e f a g c d e f a g c d BACKPLANE LCD PHASE DRIVER TYPICAL SEGMENT OUTPUT 0.5mA 2mA SEGMENT OUTPUT ERNAL DIGITAL GROUND SEGMENT DECODE LATCH SEGMENT DECODE SEGMENT DECODE 000 s 00 s 0 s s COUNTER COUNTER COUNTER COUNTER 200 THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 4 ERNAL DIGITAL GROUND LOGIC CONTROL V TH = V 6.2V 500Ω V FIGURE. ICL06 DIGITAL SECTION 8 FN82.6

9 a e f a g c d c e f a g c d e f a g c d SEGMENT DECODE SEGMENT DECODE SEGMENT DECODE TYPICAL SEGMENT OUTPUT LATCH 0.5mA 8mA DIGITAL GROUND TO SEGMENT THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK 000 s 00 s 0 s s COUNTER COUNTER COUNTER COUNTER 4 LOGIC CONTROL 500Ω DIGITAL GROUND FIGURE 8. ICL0 DIGITAL SECTION System Timing Figure 9 shows the clocking arrangement used in the ICL06 and ICL0. Two asic clocking arrangements can e used: ERNAL TO PART 4 CLOCK. Figure 9A. An external oscillator connected to pin. 2. Figure 9B. An RC oscillator using all three pins. The oscillator frequency is divided y four efore it clocks the decade counters. It is then further divided to form the three convertcycle phases. These are signal integrate (000 counts), reference deintegrate (0 to 2000 counts) and autozero (000 to 00 counts). For signals less than full scale, autozero gets the unused portion of reference deintegrate. This makes a complete measure cycle of 4,000 counts (6,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would e used. GND ICL0 ICL06 FIGURE 9A. ERNAL TO PART 4 CLOCK To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should e a multiple of 60Hz. Oscillator frequencies of 2kHz, 20kHz, 80kHz, 60kHz, 48kHz, khz, / 3 khz, etc. should e selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 00kHz, 66 2 / 3 khz, 50kHz, khz, etc. would e suitale. Note that khz (2.5 readings/second) will reject oth 50Hz and 60Hz (also 0Hz and 4Hz). R C RC OSCILLATOR FIGURE 9B. FIGURE 9. CLOCK CIRCUITS 9 FN82.6

10 Component Value Selection Integrating Resistor Both the uffer amplifier and the integrator have a class A output stage with 00µA of quiescent current. They can supply 4µA of drive current with negligile nonlinearity. The integrating resistor should e large enough to remain in this very linear region over the input voltage range, ut small enough that undue leakage requirements are not placed on the PC oard. For 2V full scale, 40kΩ is near optimum and similarly a 4kΩ for a 200mV scale. Integrating Capacitor The integrating capacitor should e selected to give the maximum voltage swing that ensures tolerance uildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL06 or the ICL0, when the analog is used as a reference, a nominal 2V fullscale integrator swing is fine. For the ICL0 with 5V supplies and analog tied to supply ground, a ±3.5V to 4V swing is nominal. For three readings/second (48kHz clock) nominal values for C lnt are 0.µF and 0.0µF, respectively. Of course, if different oscillator frequencies are used, these values should e changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric asorption to prevent rollover errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectale errors at reasonale cost. AutoZero Capacitor The size of the autozero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.4µF capacitor is recommended. On the 2V scale, a 0.04µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Voltage The analog input required to generate full scale output (2000 counts) is: V ln = 2V REF. Thus, for the 200mV and 2V scale, V REF should equal 00mV and V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity etween the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select V REF = 0.V. Suitale values for integrating resistor and capacitor would e 20kΩ and 0.µF. This makes the system slightly quieter and also avoids a divider network on the input. The ICL0 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for V IN 0. Temperature and weighing systems with a variale fare are examples. This offset reading can e conveniently generated y connecting the voltage transducer etween IN HI and and the variale (or fixed) offset voltage etween and. ICL0 Power Supplies The ICL0 is designed to work from ±5V supplies. However, if a negative supply is not availale, it can e generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lc. Figure 0 shows this application. See ICL660 data sheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single 5V supply are:. The input signal can e referenced to the center of the common mode range of the converter. 2. The signal is less than ±.5V. 3. An external reference is used. Reference Capacitor A 0.µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the pin is not at analog ) and a 200mV scale is used, a larger value is required to prevent rollover error. Generally µf will hold the rollover error to 0.5 count in this instance. Oscillator Components For all ranges of frequency a resistor is recommended and the capacitor is selected from the equation: ICL0 GND V CD09 N µf N94 0 µf f = 0.45 For 48kHz Clock (3 Readings/sec), RC C =. V = 3.3V FIGURE 0. GENERATING NEGATIVE SUPPLY FROM 5V 0 FN82.6

11 Typical Applications The ICL06 and ICL0 may e used in a wide variety of configurations. The circuits which follow show some of the possiilities, and serve to illustrate the exceptional versatility of these A/D converters. Application Notes NOTE # DESCRIPTION AN06 Selecting A/D Converters AN0 The Integrating A/D Converter The following application notes contain very useful information on understanding and applying this part and are availale from Intersil Corporation. AN08 AN0 AN0 AN046 AN052 AN9609 Do s and Don ts of Applying A/D Converters Low Cost Digital Panel Meter Designs Understanding the AutoZero and Common Mode Performance of the ICL//9 Family Building a BatteryOperated Auto Ranging DVM with the ICL06 Tips for Using Single Chip 3 / 2 Digit A/D Converters Overcoming Common Mode Range Issues When Using Intersil Integrating Converters Typical Applications SET V REF = 00mV SET V REF = 00mV 0.µF kω kω 0.µF kω kω 5V V 0.4µF 0.µF 4kΩ MΩ 0.0µF IN 9V V 0.4µF 0.µF 4kΩ MΩ 0.0µF IN 5V BP TO BACKPLANE GND Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V attery). FIGURE. ICL06 USING THE ERNAL REFERENCE Values shown are for 200mV full scale, 3 readings/sec. may e tied to either for inputs floating with respect to supplies, or GND for single ended inputs. (See discussion under Analog ). FIGURE 2. ICL0 USING THE ERNAL REFERENCE FN82.6

12 Typical Applications (Continued) SET V REF = 00mV SET V REF = 00mV 0.µF kω 0kΩ 0kΩ.2V (ICL8069) V 0.µF kω 5V 6.8V 0.4µF 4kΩ MΩ 0.0µF IN 0.4µF 4kΩ MΩ 0.0µF IN V 0.µF V V 0.µF 5V GND GND is tied to supply estalishing the correct common mode voltage. If is not shorted to GND, the input voltage may float with respect to the power supply and acts as a preregulator for the reference. If is shorted to GND, the input is single ended (referred to supply GND) and the preregulator is overridden. FIGURE 3. ICL0 WITH AN EXTERNAL BANDGAP REFERENCE (.2V TYPE) Since low TC zeners have reakdown voltages ~ 6.8V, diode must e placed across the total supply (0V). As in the case of Figure 2, may e tied to either or GND. FIGURE 4. ICL0 WITH ZENER DIODE REFERENCE SET V REF = V SET V REF = 00mV V 0.µF 0.04µF 0.µF 40kΩ kω kω MΩ 0.0µF IN V V GND 0.µF 0.4µF 0.µF 4kΩ kω 0kΩ MΩ 0.0µF 5kΩ.2V (ICL8069) IN 5V BP/GND An external reference must e used in this application, since the voltage etween and V is insufficient for correct operation of the internal reference. FIGURE 5. ICL06 AND ICL0: RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE FIGURE 6. ICL0 OPERATED FROM SINGLE 5V 2 FN82.6

13 Typical Applications (Continued) V GND 0.µF 0.µF 0.4µF 4kΩ The resistor values within the ridge are determined y the desired sensitivity. FIGURE. ICL0 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL O/RANGE U/RANGE CD OR 4C0 TO LOGIC V CC CD C B A F G E D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL FIGURE 9. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL06 OUTPUTS TO LOGIC GND V BP V SCALE FACTOR ADJUST kω C MΩ REF 0.µF 0kΩ ZERO SILICON NPN 0.0µF ADJUST MPS 04 OR 0.4µF SIMILAR 4kΩ 9V V 0.µF BP TO BACKPLANE A silicon diodeconnected transistor has a temperature coefficient of aout 2mV/ o C. Caliration is achieved y placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a reading. The sensor should then e placed in oiling water and the scalefactor potentiometer adjusted for a 00.0 reading. FIGURE 8. ICL06 USED AS A DIGITAL CENTIGRADE THERMOMETER O/RANGE U/RANGE CD OR 4C0 TO LOGIC V CC The LM3 is required to ensure logic compatiility with heavy display loading. 5V 2 3 C 4 B 5 A 6 F G 8 E 2kΩ 9 D2 0 C2 B2 2 A2 LM3 3 F2 4 E2 5 D3 6 B3 F3 8 E3 9 AB4 20 POL kω V BP FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL0 OUTPUT V 3 FN82.6

14 Typical Applications (Continued) 0.µF kω 0µF kω SCALE FACTOR ADJUST (V REF = 00mV FOR AC TO RMS) 40kΩ N94 5µF CA 2.2MΩ AC IN V 0.4µF 4kΩ 0.µF 0µF 9V µf 4.3kΩ 0kΩ µf (FOR OPTIMUM BANDWIDTH) 0kΩ µf 0.µF BP TO BACKPLANE Test is used as a commonmode reference level to ensure compatiility with most op amps. FIGURE. AC TO DC CONVERTER WITH ICL06 5V ICL0 DM Ω LED SEGMENTS Ω Ω FIGURE. DISPLAY ERING FOR INCREASED DRIVE CURRENT 4 FN82.6

15 DualInLine Plastic Packages (PDIP) ICL06, ICL0, ICL0S INDEX AREA BASE PLANE SEATING PLANE B C A N 2 3 N/2 B D e E NOTES:. Controlling Dimensions: INCH. In case of conflict etween English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.5M Symols are defined in the MO Series Symol List in Section 2.2 of Pulication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS3. 5. D,, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm). 6. E and e A are measured with the leads constrained to e perpendicular to datum C.. e B and e C are measured at the lead tips with the leads unconstrained. e C must e zero or greater. 8. B maximum dimensions do not include damar protrusions. Damar protrusions shall not exceed 0.00 inch (0.mm). 9. N is the maximum numer of terminal positions. 0. Corner leads (, N, N/2 and N/2 ) for E8.3, E6.3, E8.3, E.3, E42.6 will have a B dimension of inch (0.6.4mm). B A 0.00 (0.) M C A A2 L B S A e C E C L e A C e B E.6 (JEDEC MS0AC ISSUE B) LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D E E e 0.00 BSC 2.54 BSC e A BSC 5. BSC 6 e B L N 9 Rev. 0 2/93 5 FN82.6

16 Metric Plastic Quad Flatpack Packages (MQFP) D D Q44.0x0 (JEDEC MS0AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B A E E D , 5 e E E , 5 PIN L N MIN 0 o MIN 0 o o L 2 o 6 o A2 A 2 o 6 o M C 0.3/ /0.00 A AB S D S SEATING PLANE C BASE METAL WITH PLATING 0.3/ /0.009 H e 0.0 BSC 0.80 BSC Rev. 2 4/99 NOTES:. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y4.5M Dimensions D and E to e determined at seating plane C. 4. Dimensions and E to e determined at datum plane H. 5. Dimensions and E do not include mold protrusion. Allowale protrusion is 0.mm (0.00 inch) per side. 6. Dimension does not include damar protrusion. Allowale damar protrusion shall e 0.08mm (0.003 inch) total.. N is the numer of terminal positions. All Intersil U.S. products are manufactured, assemled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can e viewed at Intersil products are sold y description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current efore placing orders. Information furnished y Intersil is elieved to e accurate and reliale. However, no responsiility is assumed y Intersil or its susidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted y implication or otherwise under any patent or patent rights of Intersil or its susidiaries. For information regarding Intersil Corporation and its products, see 6 FN82.6