Fabrication Process For A Novel High Speed CoPlanar-to-Coaxial Off-Chip Interconnect
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1 Advanced Packaging : Advanced Packaging I Session We-A-2 September 3, 2008 Fabrication Process For A Novel High Speed oplanar-to-oaxial Off-hip Interconnect hris McIntosh & Brock J. ameres Montana State University Bozeman, MT, USA 1
2 Introduction Drawback of wire bonds Use of coax cable to overcome drawbacks Use of cable of chip Fabrication process Early Results Future work 2
3 3 Wire Bonding Electrical Drawbacks Unshielded nature Generates considerable signal cross-talk M M f vel K 2 1 M M b K 4 1 Forward cross-talk (FEXT) Reverse cross-talk (NEXT) Where, f a f k RT V V FEXT b a b k V V NEXT
4 Wire Bonding Electrical Drawbacks (cont) Self Inductance of the return path V bnc N ret 0.8V rise Z sig 0 Voltage Bounce due to inductive return path N number of signals sharing common return path ret self inductance of wire bond providing return path 4
5 Electrical Drawbacks (cont) Reflected energy due to impedance discontinuities Wire Bonding wb Zwb Impedance of wire bond wb Z Z Z Z 0 0 Reflection coefficient Z oad impedance Z0 Source side impedance 5
6 oaxial cable Reasons for cable use Signal cross-talk is reduced by shielded cable Self Inductance is significantly less due to number of signals sharing return path Reflected energy is reduced by controlled impedance of the cable 6 M M f vel K 2 1 M M b K Z V N V rise sig ret bnc 0 0 Z Z Z Z c c c Z
7 What s the Target Goal? Provide a chip-to-chip interconnect system Replace critical wire bond interconnect System will provide Shielding (reducing cross talk) Matched impedance transmissions Increased signal transmission lengths Increased speed 7
8 Major steps able selection Wafer selection Design waveguide dimensions Trench fabrication Waveguide fabrication Assembly and Testing 8
9 able selection Impedance equal to 50 Size less than 600m Bigger than 300um Type - Semi-rigid Outer shield is the ground path 9
10 MIRO OAX Selected cable UT-020 & UT-013 semi-rigid cable UT 013 UT 020 Outer Dia (um) 330 (+/- 25.4) 584 (+/- 25.4) Dielectric Dia (um) enter onductor Dia (um) 78.7 (+/- 12.7) 127 (+/- 12.7) Impedance (ohms) 50 +/ /- 2.0 Material - Outer conductor opper opper Material - Dielectric PTFE PTFE Material - enter onductor SPW SPW 10
11 Test hip ayout Test chip layout 3D model of hip-to-hip interconnect 11
12 Process Steps 12
13 Anisotropic etch TMAH SiO 2 as mask Depth of trench: Outer able Dia 2 Trench Etching Inner able Dia 2 Trench run from Gnd trace to Gnd trace 13
14 o-planar WaveGuides Why was o-planar chosen? Overall structure size 2W gnd +W sig +2S copl W sig, S copl, & determine Z 0 W gnd set to 100um able striped in stages Helps reduce edge affects 14
15 Etched Trenches & WaveGuides Figures show etched trenches with Aluminum traces deposited 15
16 PB Test Fixture Two dies with oaxial cable embedded within the etched trenches Test PB boarded used to mount the dies, includes wire bonding pads 16
17 Early Results 17
18 Possible Future Work Using UT-008 cable Outer dia 203 m Gives the following oplanar dimensions W sig = 120um S copl = 40um W gnd = 50um Total structure footprint 300um Footprints 43% less compared to UT-013 Use of thick dielectric for trench 18
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