DESIGN AND SIMULATION ANALYSIS OF SEVEN LEVEL CASCADED GRID CONNECTED INVERTER FOR PV SYSTEM

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1 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 EIGN AN IMULATION ANALYI OF EVEN LEVEL CACAE GRI CONNECTE INVERTER FOR PV YTEM Akshay B. Zade, tudent M.E epartent of Electrical, University of Pune, GHRIET, Pune, India r. Asha Gaikwad, Professor epartent of Electrical, University of Pune, GHRIET, Pune, India ABTRACT This paper presents the siulation analysis of seven level cascaded rid connected inverter and also copared with five level inverter for %TH for voltae and current by usin level shifted PWM techniques. The proposed syste are odeled and siulated throuh coputer software tool usin MATLAB /IMULINK. This paper also presents the desin and developent of the seven level cascaded rid connected inverter.the LC filter is also use in the output side to further reduce the TH values.even level inverter is utilise as a power converter to inject power enerated fro pv source to the rid.multilevel inverters have been ainly used in ediu or hihpower syste applications, such as static reactive power copensation and adjustablespeed drives. In these applications, due to the liitations of the currently available power seiconductor technoloy.the ter ultilevel bean with the threelevel converter. ubsequently, several ultilevel converter topoloies have been developed. However, the eleentary concept of a ultilevel converter to achieve hiher power is to use a series of power seiconductor switches with several lowervoltae dc sources to perfor the power conversion by synthesizin a staircase voltae wavefor. Capacitors, batteries, and renewable enery voltae sources can be used as the ultiple dc voltae sources. The coutation of the power switches areate these ultiple dc sources in order to achieve hih voltae at the output; however, the rated voltae of the power seiconductor switches depends only upon the ratin of the dc voltae sources to which they are connected Percentae of TH for R, RL, RLC load taken and siulation results analyse and studied and coparison ade between five level and seven level. KEYWOR: Total horonic distortion(th), Multilevel inverter, PV array P a e

2 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 ACKNOWLEGMENT I ratefully acknowlede the contributions of r. Asha Gaikwad for their help in the preparation of this paper. INTROUCTION The increasin nuber of renewable enery sources and distributed enerators require new starties for the operation and anaeent of the electricity rid in order to aintain and iprove the power supply reliability and quality.the ultilevel inverter have been ainly use in ediu or hih power syste appliation.multilevel inverter concept is usually a unique alternative because it is havin low switchin frequency and also provides voltae and current sharin between power seiconductors.acopilation of the ost coon topoloies of ultilevel converters is presented in[],and it shows which ones are best suitable to ipleent inverters for standalone applications in the rane of a few kilowatts.as an exaple, a prototype of 3 kva was ipleentedin [],andpeak efficiency of 96.0% is shown in[] In [2] by usin feedback controller a diital proportional interal current control alorith is ipleented in P TM320F282 to control overall operation of the invertercontrol.in this Photovoltaic syste is reconised to be in the forefront in renewable electric power eneration, it can enerate dc without environental ipact and containation when track by solar radiation.one of the proble in the PV eneration syste is the aount of electric power enerated by solar arrays always chanin with weather condition, so MPPT ethod ipleented for the optiu results. In [3] in phase disposition level shifted ulticarrier odulation is used as a control stratey, and cascaded Hbride inverter require less no. of coponents as copared to diode claped inverter and developed seven level inverter is interated with PV array and by copared with conventional inverter Renewable Enery ources (RE) are rapidly ainin popularity for sustainable power eneration, they bein less pollutin and readily available resources. Moreover, olarphoto Voltaic (PV) based power eneration has uch ore iportance, it bein ore reliable and requires less aintenance (as it has no rotatin echaniss). The trend of eawatt rane PV plants will deand hiher power ratins for the central rid tied converter, and traditional two level VI topoloies will not be able to fulfill power ratin, power quality and efficiency requireents. The RE (PV source) is connected to the C side of the ulti level Voltae ource Inverter (VI) for interfacin with the rid. The ultilevel VI is utilized as a power converter to inject the power enerated fro the RE (PV source) to the rid [3]. As the world is concerned with the fossil fuel exhaustion and environental proble caused by conventional power eneration, particularly solar have becoe very popular and deandin. PV sources are used in any applications because they have advantae of bein aintenance and pollution free. It is used to convert the dc power fro solar odule to ac power to feed into load or rid. Multilevel inverter is used for PV application [4]. 2 P a e

3 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 Nuerous industrial applications have beun to require hiher power apparatus in recent years. oe ediu voltae otor drives and utility applications require ediu voltae and eawatt power level. For a ediu voltae rid, it is troublesoe to connect only one power seiconductor switch directly. As a result, a ultilevel power converter structure has been introduced as an alternative in hih power and ediu voltae situations. A ultilevel converter not only achieves hih power ratins, but also enables the use of renewable enery sources. Renewable enery sources such as photovoltaic, wind, and fuel cells can be easily interfaced to aultilevel converter syste for a hih power application. The concept of ultilevel converters has been introduced since 975. The ter ultilevel bean with the threelevel converter. ubsequently, several ultilevel converter topoloies have been developed. However, the eleentary concept of a ultilevel converter to achieve hiher power is to use a series of power seiconductor switches with several lowervoltae dc sources to perfor the power conversion by synthesizin a staircase voltae wavefor. Capacitors, batteries, and renewable enery voltae sources can be used as the ultiple dc voltae sources. The coutation of the power switches areate these ultiple dc sources in order to achieve hih voltae at the output; however, the rated voltae of the power seiconductor switches depends only upon the ratin of the dc voltae sources to which they are connected[5]. Multilevel inverters have been ainly used in ediu or hihpower syste applications, such as static reactive power copensation and adjustablespeed drives. In these applications, due to the liitations of the currently available power seiconductor technoloy, a ultilevel concept is usually a unique alternative because it is based on lowfrequency switchin and provides voltae and/or current sharin between the power seiconductors [6]. This paper presents the siulation analysis of seven level cascaded rid connected inverter and also copared with five level inverter for %TH for voltae and current by usin level shifted PWM techniques. The proposed syste are odeled and siulated throuh coputer software tool usin MATLAB /IMULINK. This paper also presents the desin and developent of the seven & five level cascaded rid connected inverter.the LC filter is also use in the output side to further reduce the TH values. even level inverter is utilise as a power converter to inject power enerated fro pv source to the rid. PV array cell is desined in atlab, and solar is taken as input to the seven level inverter and perforance is evaluted. % of TH for R, RL, RLC load taken and siulation results analyse and studied and coparison ade between five level and seven level. BLOCK IAGRAM: PV CELL C LINK CAPACI TOR EVEN LEVEL INVER TER FILTER LOA PWM CONTROLLER Fiure.: Block iara of proposed Multi Level Inverter 3 P a e

4 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 Fi() shows block diara of proposed odel before ipleentation of PV cell as input source seven level & five level inverter is desin with usin separate dc source with dc link capacitor and after ipleentation of PV cell odel in atlab PV cell taken as input of the seven level and five level inverter Need of the inverter: One of the drawback in the solar enery sources is the need of the enery storae for the syste to be utilized for the sinificant percentae of the day, one way to overcoe this disadvantae by utilizin the inverter and its controller circuits for PV based G units durin the day and nihts ties for iprovin the reactive power copensation and haronic eliination on its neihborin G units and the rid by proper exchane of reactive power between the sources. HBride Inverter: Fiure 2: H bride inverter The traditional two or three levels inverter does not copletely eliinate the unwanted haronics in the output wavefor. Therefore, usin the ultilevel inverter as an alternative to traditional PWM inverters is investiated. In this topoloy the nuber of phase voltae levels at the converter terinals is 2N, where N is the nuber of cells or dc link voltaes. In this topoloy, each cell has separate dc link capacitor and the voltae across the capacitor iht differ aon the cells. o, each power circuit needs just one dc voltae source. The nuber of dc link capacitors is proportional to the nuber of phase voltae levels.each Hbride cell ay have positive, neative or zero voltae. Final output voltae is the su of all Hbride cell voltaes and is syetric with respect to neutral point, so the nuber of voltae levels is odd. Five level Inverter: Fiure 3: inle phase diara of 5level CHB inverter 4 P a e

5 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 In five level inverter two Hbrides are used and each H bride required four switch with separate dc source and it is siulated throuh atlab iulinkby usin sipower syste platfor.. even level inverter: Control stratey: Fiure 4: inle phase diara of 7level CHB inverter The followin are the different control strateies for an inverter, (i) Bipolar and Unipolar PWM (ii)carrier based PWM (a) Phase shifted ulticarrier odulation (b) Level shifted ulticarrier odulation (iii)tair case odulation (iv)elective haronic eliination schee (v)pace vector odulation schee Level shifted ulticarrier odulation: For an N level inverter, level shifted ulticarrier odulation requires (N) carriers, all havin the sae frequency and aplitude. The (N) trianular carriers are vertically disposed such that the bands they occupy are contiuous. The frequency odulation index is iven by f=fcr /f and the aplitude odulation index isdefined as a =2V / Vcr (); for 0<a<= where V is the peak aplitude of the odulatin wave and Vcr is the peak aplitude of each carrier wave. hows three schees for the levelshifted ulticarrier odulation: (a) InPhase isposition (IP), where all carriers are in phase; 5 P a e

6 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 (b) Alternative Phase Opposite isposition (APO), where all carriers are alternatively in opposite disposition; and (c) Phase opposite isposition (PO), where all carriers above the zero reference are in phase but in opposition with those below the zero reference. In this paper, IP type level shifted ulticarrier odulation control stratey is eployed because it results in better TH perforance than the PO and APO. For a 7level inverter, six carrier waves with each of 0.33V aplitude and frequency of 000Hz and one reference wave with V aplitude and frequency of 50Hz, required for an aplitude odulation index of and a frequency odulation index of 20. Filter: Filter is use to reduce the haronics and ripples, LC capacitor is used to reduce the %TH and results are taken. Various types of load: Resistive load: Resistive loads are loads which consue electrical enery in a sinusoidal anner. This eans that the current flow is in tie with and directly proportional to the voltae. It is a load that contains no inductance or capacitance, just pure resistance. Therefore; when a resistive load is enerized, the current rises instantly to its steadystate value without first risin to a hiher value. It includes loads such as incandescent lihtin and electrical heaters. Inductive Loads: An Inductive Load is a load that pulls a lare aount of current (an inrush current) when first enerized. After a few cycles or seconds the current "settles down" to the fullload runnin current. Inductive loads can use excessive voltaes to appear when switched. Exaples of Inductive Loads are otors, transforers, and wound control ear. Capacitive Loads: A Capacitive Load is an AC electrical load in which the current wave reaches its peak before the voltae. Capacitive loads are loads that capacitance exceeds inductance. Exaple of a Capacitive Load is the flash of the caera. Matlab siulation of above block diara : Continuous 3 Mosfet Mosfet powerui 5 7 C Voltae ource eries RLC Branch i cope3 Current Measureent 9 s Mosfet2 Mosfet3 To Workspace 2 eries RLC Branch4 4 Out eries RLC Branch3 v Voltae Measureent ubsyste Mosfet5 cope2 Mosfet6 Mosfet4 C Voltae ource Mosfet7 Fiure.5: Five level siulation odel: 6 P a e

7 in and Trianular ubsyste C Voltae ource C Voltae ource C Mosfet Mosfet4 Mosfet5 Mosfet7 Mosfet9 Mosfet Mosfet2 Mosfet3 Mosfet6 Mosfet8 eries RLC Branch eries RLC Branch2 Mosfet0 Mosfet2 eries RLC Branch cope Current Measureent Continuous powerui v Voltae Measureent s To Workspace cope NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 i Fiure. 7: even level inverter siulation odel PV odel: Fiure 8 : Equivalent circuit of olar PV cell Continuous powerui ubsyste Conn Conn2 R v Vo cope Fi (8) olar cell odel 7 P a e

8 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT solar power P iulinkp Converter Ir olar odule (36 cells) I Current ensor Voltae ensor P Piulink Converter 3 ipv Product ppv V P Piulink Converter vpv f(x)=0 2 cope olver Confiuration Electrical Reference Fiure. 9: iulation odel of solar cell PV array reverse saturation current Irs: I rs= [ ( / ) ].. PV array saturation current Io: Io = Irs[T/ Tr ]3 exp[q Eo /Bk{/Tr /T}] 2 The current output of the PV array is: Ipv = Np*IphNp*Io[exp{q (VPVIPV*Rs)/ NsAkT}].3 Where Vpv is output voltae of a PV array (V) Ipv is output current of a PV array (A) Tr is the reference teperature=298 K T is the cell teperature in oc Io is the PV array saturation current (A) A=B is an ideality factor =.6 K is the Boltzann constant =.3805e23J/K q is electron chare=.6e9c Iscr is the PV array short circuit current at 25 C and 000W/sq. =2.55A Ki is the short circuit current teperature coefficient at Iscr =0.007A/ C is the PV array illuination (W/sq.) =000W/sq. Eo is the band ap for silicon =.ev Voc is the output voltae of the PV array 8 P a e

9 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 ubsyste3 Conn Conn2 R2 va 3 siout 5 To Workspace 7 h h7 h8 eries RLC Branch v Voltae Measureent cope Out 6 Out3 h3 h4 ubsyste 2 2 vn eries RLC Branch ubsyste Conn R Conn2 ubsyste2 eries RLC Branch2 Conn R Mosfet6 Mosfet2 Mosfet4 Mosfet3 Mosfet5 Mosfet7 Mosfet8 Mosfet9 Mosfet Mosfet Mosfet0 Mosfet Conn2 Fiure 0: inle phase seven level inverter with solar as input. IMULATION & REULT: The seven level inverter operation and its results at various load condition like R, RL, RLC are studied and discussed below. The siulink output voltae and current are taken for the seven level inverter and its raph is taken and its wavefor is iven below. Fiure.: Output voltae for RLC load seven level inverter (without filter). 9 P a e

10 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 Fiure 2: Graph for RLC load seven level inverter Fiure.3: Output current for RLC load seven level inverter(without filter) Fiure. 5: Graph for output current RLC load seven level inverter 0 P a e

11 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 The total haronic distortion of seven level inverter is taken for voltae and current haronics and it s tabulated below. Multilevel inverter R load RL load RLC load 5 level 24.87% 3.88% 25.88% 7 level 7.59% 8.34% 8.33% Table. Coparison table for 5 level and 7 level inverter (For voltae without filter) Multilevel inverter R load RL load RLC load 5 level 24.87%.87% 3.2% 7 level 7.59% 4.28% 4.30% Table 2. Coparison table for 5 level and 7 level inverter (For Current without filter) The above table & 2 deals with coparison of five levels and seven level inverter, while studyin the table, we can justify that the seven level inverter will ives low haronics copared to five level inverter. The TH siulink output wavefor with for the seven level inverter is below. The TH value of the seven level inverter for voltae is for RLC load is 8.33% and current TH value is 4.30 %, these output are taken without usae of filter, when we use the filter the haronics in the output will be reduced, and results are tabulated below. Multilevel inverter R load RL load RLC load 5 level 8.6% 0.76% 8.40% 7 level.47%.48% 2.24% Table 3. Coparison table for 5 level and 7 level inverter (For voltae with filter) Multilevel inverter R load RL load RLC load 5 level 8.6% 0.48% 8.3% 7 level.47%.27% 2.% Table 4. Coparison table for 5 level and 7 level inverter (For current with filter) Fiure 5:Voltae TH value for RLC load for seven level inverter P a e

12 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 Control stratey Level shifted ulti carrier odulation Fundaental frequency 50 Hz R 0 Oh L 5e3 H C 000e6 F Table (5) ultilevel inverter paraeter Operatin teperature of PV array 25 de.cel Irradiation of PV array 000 w/sq. Output voltae of PV array 2 V Output current of PV array 4.8 A Output power of PV array 57.6 W Table (6) PV array paraeter CONCLUION Cascaded Hbride 5 level inverter is copared with 7 level inverter and concluded that seven level inverter will ives low haronics copared to the five level inverter, iulations has been done usin MATLAB iulink, with developed topoloy and found that the developed topoloy provides the better aount of TH and also there is increase in the fundaental voltae anitude which iplies ood perforance. PV array and boost converter is odelled and its perforance is analysed. Also, the 7level Cascaded Hbride inverter is siulated with the PV array as its input and found to be ood perforance with sae TH as that of Cascaded Hbride inverter with dc link as its input. And also, the developed 7level inverter is interated with the PV array and found to be ood perforance. REFERENCE []. aher, J. chid, and F. L.M. Antunes, Multilevel inverter topoloies for standalone PV systes, IEEE Trans. Ind. Electron., vol. 55, no. 7, pp ,Jul [2] Jeyrajelvaraj and Nasrudin A. Rahi, enior Meber, IEEE, Multilevel Inverter For GridConnected PV yste Eployin iital PI Controller IEEE TRANAC TION ON INUTRIAL ELECTRONIC, VOL. 56, NO., JANUARY [3] P. VENU GOPAL M Tech (Power Electronics), VNR VJIET, Professor and head, EEE ept, VNR VJIET, Analysis and siulation of solar pv based ultilevel converters international journal of professional enineerin studies. 2 P a e

13 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 [4] Adilarwar, Mohaad. J. Ashar, iulation and Analysis of a Multilevel Converter Topoloy for olar PV Based Grid Connected Inverter art Grid and Renewable Enery, 20, 2, 5662 doi:0.4236/sre Published Online February 20. [5]. Naresh Kuar*,. Nareshivakanth **, K. iva Kuar, MultiLevel Inverter for Power Quality Iproveent in Renewable Power Generation yste, International Journal of Enineerin Research & Technoloy (IJERT) Vol.3 Issue8, Auust204 IJERT IN: [6] Reddaiah Polisetty, Nadendla harief, Gopi Pasala, iulation Analysis of Multi level Inverter for olar Power Applications International Journal of Advanced Electrical and Electronics Enineerin, (IJAEEE). [7] Karthika N, anari A, Ua aheswari R Perforance Analysis of Multi Level Inverter with C Link witches for Renewable Enery Resources International Journal of Innovative Technoloy and Explorin Enineerin (IJITEE) IN: , Volue2, Issue6, May 203. [8] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E. Galvan, R. C.PortilloGuisado, M. A. M. Prats, J. I. Leon, and N.MorenoAlfonso, Power electronic systes for the rid interation of renewable enery sources: A survey, IEEE Trans. Ind. Electron., vol. 53, no. 4, pp , Au [9] L. M. Tolbert and T. G. Habetler, Novel ultilevel inverter carrierbased PWM ethod, IEEE Trans. Ind. Appl., vol. 35, no. 5, pp , ep./oct. 999 [0] M.AFIA, T V V PAVAN KUMAR, esin and iulation of Grid Connected PV syste Usin Multilevel Inverters International Journal of Electrical and Electronics Enineerin (IJEEE), IN (PRINT): , Volue4, Issue2, 203. BIOGRAPHIE: Mr.Akshay Bhaurao Zade received the B.E deree fro RCERT, Chandrapur, fro Napur University in Electrical Enineerin.He is doin M.E fro GHRIET, University of Pune, He has presented a paper in an International conference. Three years Industrial experience as an Enineer. His field of interest is Power ystes, Industrial drives and their control, Weldin autoation. 3 P a e

14 NOVATEUR PUBLICATION INTERNATIONAL JOURNAL OF INNOVATION IN ENGINEERING REEARCH AN TECHNOLOGY [IJIERT] IN: VOLUME 2, IUE 0, OCT.205 r. Asha Gaikwad received the B.E and M.Tech deree fro VNIT, Napur fro Napur University in Electrical Enineerin. he conducted her Ph.. studies at GIT, Indore fro RGPV, Bhopal. For the last decade, she has worked as faculty in various Enineerin collees and is currently workin as Associate Professor in Electrical epartent at GHRIET, Pune. Her fields of interest are Power Electronics and Power ystes. 4 P a e