Design of CMOS LNA for Radio Receiver using the Cadence Simulation Tool

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1 MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, August 2013, pp Design of CMOS LNA for Radio Receiver using the Cadence Simulation Tool Neha Rani M.Tech. (VLSI Design) Scholar Deptt. of Electronics and Communication Engineering Laxmi Devi Institute of Engg. & Technology, Alwar, Rajasthan, INDIA Suraj Sharma Asstt. Prof. E & CE Deptt. Deptt. of Electronics and Communication Laxmi Devi Institute of Engg. & Technology, Alwar, Rajasthan, INDIA suraj_4011@yahoo.co.in ABSTRACT A Low Noise Amplifier is the basic building block or key component in the Communication System. Any Radio Receiver is made from Low Noise Amplifier, mixer and Filter (Power Efficient Active Filter) where LNA plays a challenging role of amplificati on in the Radio Receiver Circuit. In this paper, we design and Simulate Low Noise Amplifier using Cadence Virtuoso (R) Schematic Editor XL tool in 0.18µm UMC Technology for lower power consumption. First we design the Common LNA and Cascode LNA in Cadence tool separately. Then compose of these two and make a new schematic of LNA, The benefit to Design the new LNA to save more gain as compared to individual one. In the communication market the demand of LNA is increasing with increasing the market of Cell Phones, GPS, and Bluetooth etc, which is used in day to day life. So the main aim of our paper is to design an efficient and low cost LNA that is suitable and compatible with all radio receivers. Keywords: Low-noise amplifier (LNA), Radio Receiver, Cascode amplifier, filter, cadence virtuoso (R) schematic editor XL tool. I. INTRODUCTION Now-a-day in the Communication field, Radio Receiver plays an important role in our daily lives. The Role of Radio Receivers is to give the exact usable information to users by the conversion of electromagnetic waves or radio Waves present in the environment. These Radio Receivers contain a most important part of amplification that is called a Low Noise Amplifier. A Low Noise Amplifier is the basic building block or key component in the Communication System. Any Radio Receiver is made from Low Noise Amplifier, mixer and Filter (Power Efficient Active Filter) where LNA plays a challenging role of amplification in the Radio Receiver Circuit. We design a Low Noise Amplifier because of its number of benefits and a wide future in communication field in terms of design, cost, environment using 0.18 µm UMC Technology. UMC is the United Microelectronics Corporation Technology is the Taiwan s first semiconductor company where an important thing is that 0.18 µm uses lower power consumptions as compared to all others. To explore techniques to implement a low noise amplifier is also the consideration of our project. LNA design presents a considerable challenge because of its simultaneous requirement for high gain, low noise amplifier, good input and output matching and unconditional stability at the lowest possible draw from an amplifier. Although gain, noise figure, stability, linearity, input and output matching are equally important; they are independent and do not always work in each other s favor. We can say that a Low Noise Amplifier is a key component in the RF front end receiver. This poses challenges in terms of meeting high gain, low noise figure, good linearity and lower power consumption requirement. To design an LNA there are two widely used types of devices S parameters and normal device to design LNA. S parameters is a built in device which does not require any type of external bias that can be applied, in designing the S-parameters most used. In designing a proper selection of transducer is used should have maximum gain and low noise figure where stability plays an important role at the time of noise itself generated in LNA. We enhance the stability by adding series and source resistance generate thermal noise, so we do not use this technique. An ideal inductor zeroes resistance it generates the thermal noise it reduces the stability by reducing the gain of the amplifier. So the main aim of our project is to design an efficient and low cost LNA that is suitable and compatible with all radio receivers.

2 MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, August 2013, pp II. ARCHITECTURE OF RADIO RECEIVER The receiver demodulates and decodes the channel output to recover the original information to the source. Once demodulated, the channel decoder, which is typically a filter matched to the channel encoder, is used to recover one sample estimate per symbol of the channel code word. The channel encoder estimates the digital source code word, which is then converted to an estimate the original data from the source decoder. The first stage of a receiver is typically a low-noise amplifier (LNA), whose main function is to provide enough gain to overcome the noise of subsequent stages (for example, in the mixer or IF amplifier). Aside from providing enough gain while adding as little noise as possible, an LNA should accommodate large signals without distortion, offer a large dynamic range, and present good matching to its input and output, which is extremely important if a passive band select filter and imagereject filter precedes and succeeds the LNA, since the transfer characteristics of many filters are quite sensitive to the quality of the termination. Figure 1: Simplified block diagram of receiver end of radio A simplified diagram of a Radio Frequency (RF) transceiver is shown below (Fig. 1). The antenna receives the input signal which is then filtered by a bandpass filter to ensure only the desired band is processed. The signal is then fed into the LNA which amplifies it. The image reject filter blocks any signals that may be mixed down and produce any distortion of the desired signal. The mixer down converts the RF signal to the Intermediate Frequency (IF) which then can be processed in the receiver s backend. The mixer uses a local oscillator frequency produced by a voltage controlled oscillator to down convert the RF signal to the IF. With the signal down-converted to the IF the signal can be processed in the baseband. In the transmit side, signals are modulated in the baseband and IF stages and upconverted by the mixer which uses a Voltage-Controlled Oscillator (VCO). The upconverted signal is amplified to transmission by the power amplifier. As a result of improved efficiency the power amplifier is usually non-linear and produces many harmonics. The low-pass filter is used to filter out the harmonics for transmission by the antenna [1]. III. POPULAR LNA TOPOLOGIES IN CMOS TECHNOLOGY The LNA usually only involves one or two transistors to achieve low noise operation. The performance of the LNA circuits is very dependent on process technology. CMOS technologies are the best choice to design an LNA because they offer high speed operation, simplicity in fabrication, and low power consumption. The following discussion presents several popular LNA structures possible in a CMOS integrated circuit. The LNA input is directly connected to a filter for impedance and noise matching. Therefore, different LNA structures have different methods to achieve impedance matching. The structure shown in Figure 2 achieves input impedance matching by directly placing a 50 Ω resistor (Rs) in parallel with the gate of transistor M 1. This is the most straightforward method but the noise figure will be exceptionally high. The lower bound of the LNA noise factor is given by: F 2 + (4γ/αg m R s ) (1) Where α = g m /g do, g do is the drain source conductance, and γ is a constant with a value of Since the term (y/αg m R s ) is larger than 1, the noise figure is readily larger than 6 db. The primary contribution of noise comes from the termination resistor Rs and the drain of the transistor. Due to the noise performance limitations this LNA structure is rarely used. By carefully choosing the size of the transistor and biasing conditions, the 50Ω impedance matching can be easily obtained. Ignoring the gate current noise, a lower bound of noise factor for this topology is represented by F > 1 + (γ/α). This minimum noise factor is about 2.2 db and 4.8 db for a long and short channel device, respectively. The gate current noise will make the noise factor larger, but the drain noise will still be the dominant factor. Figure 2: Resistive terminated LNA The shunt series feedback LNA, shown in Figure 3, uses negative shunt feedback to modify the input impedance of a common source stage. Its input impedance can be approximately calculated by:

3 MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, August 2013, pp Z in = R F / ( l + A ) (2) Where A is the voltage gain which is approximately in the order of R in /R out assuming the g m of M 1 is very large. isolation of the LNA, a C gd. The neutralization technique can be used as shown in Figure 5. An inductor LF is added in parallel with this capacitor to provide a different feedback polarity to cancel the effect of C gd. The inductive feedback may incur some potential stability issues because of the negative feedback. During the design of a C gd neutralization LNA, the instability issue must be avoided. Figure 3: Shunt Series Feedback LNA The noise figure of this structure is better than that of the resistively terminated LNA structure but it is still too high to use in applications such as a UWB receiver. The gate noise is the largest noise contributor in the shunt series feedback LNA structure. This is because the gate noise current experiences high impedance due to the resonance of the input matching network [9]. Therefore, in order to reduce the noise figure, the quality factor of the input matching network should be reduced leading to an impact on the signal quality and filtering. The basic issue with using a CMOS transistor for the LNA is its inherently low transconductance and hence low gain. However, if the current reuse technique is employed, transconductance could be increased as much as twofold. Figure 4 shows a simplified schematic of the current reuse LNA. The key point is that given the same bias current the effective transconductance is g m1 + g m2, while it is simply g m1 in the case of the topologies mentioned previously. A major drawback of this design is its high input and output impedances, thus requiring external impedance matching networks. This prevents the use of this LNA in fully integrated applications. Due to the high gain property, the strong Miller effect reduces the reverse isolation of this LNA. In the actual design, two identical stages are cascaded to improve the reverse isolation. Figure 5: Neutralization LNA Figure 6 shows the structure of the inductive source degeneration LNA which is used for the design of LNA in this thesis. Transistor M 1 is in the common source configuration and M 2 is in the common gate configuration, which has a benefit of higher input impedance. Degeneration inductor Ls provides negative feedback to the amplifier and stabilizes the gain. Figure 6: Inductive Source Degeneration LNA Figure 4: Current Reuse LNA The reverse isolation of the LNA is limited by the drainsource parasitic capacitor C gd. In order to improve the reverse Table 1 compares all the topologies discussed before. As shown in Table 1 it can be proven that inductive source degeneration LNA has a good narrowband match and a very small noise figure. Good input output match and noise figure are essential requirements for any UWB LNA design. Since UWB is such a low power technology, one cannot afford to add too much noise into the system. Research has shown that the source degeneration is the best suitable topology for the UWB related LNA.

4 MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, August 2013, pp Table 1: Comparison between various Topologies Topology Plus Point Minus Point Resistive termination Good input match Large NF Common gate Excellent input match Huge NF and power Series shunt feedback Inductive degeneration Broadband i/o match Good narrowband match, Small NF Stability issues Large area Current reuse High gain low power External matching network required Inductor neutralization Good reverse isolation (S22) IV. CADENCE SIMULATION TOOL Increased area, stability concerns Cadence Design Environment is used to create manufacturing robust designs. This is the advance design and simulation environment that gives designers a new parasitic estimation and comparison flow and optimization algorithms for center designs better for yield improvement and advanced matching and sensitivity analysis. Maximum Efficiency is the benefit to design with and a variety of built in analog tools. Also a quick detection of the circuit problems via a clear visualization cockpit. A Schematic view of the circuit is created using the Cadence Composer Schematic Editor. Alternatively, a text net list input can be employed. The circuit is simulated using the Cadence Affirma analog simulation environment. Different simulators can be employed, once circuit specifications are fulfilled in simulation, the circuit layout is created using the Virtuoso Layout Editor. The resulting layout must verify some geometric rules dependent on the technology (design rules). For enforcing it, a Design Rule Check (DRC) is performed. Optionally, some electrical errors (e.g. Shorts) can also be detected using an Electrical Rule Check (ERC). Then, the layout should be compared to the circuit schematic to ensure that the intended functionality is implemented. This can be done with a Layout Versus Schematic (LVS) check. All these verification tools are included in the Diva software in Cadence (more powerful Cadence tools can also be available, like Dracula, or Assura in deep submicron technologies) [14]. V. LOW NOISE AMPLIFIER SCHEMATIC 1. Common LNA Schematic 2. Cascode LNA Schematic 3. Final Schematic Where as We Combine the Final Schematic by both with Common LNA Schematic and Cascode LNA Schematic. Figure 7: Simulation Window (i) Common LNA schematic A common low noise amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a voltage or transconductance amplifier. We can design common LNA using common source, common drain and common gate amplifier. Figure 8: Common LNA Schematic First we design the Common gate amplifier using the cadence tool shows gate as an input signal and drain as an output signal. It is useful in, for example, CMOS RF receivers, especially when operating near the frequency limitations of the FETs; it is desirable because of the ease of impedance matching and potentially has lower noise. (ii) Cascode LNA Schematic The cascade of CS stage and a CG stage is called cascode. This combination may have one or more of the following

5 MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, August 2013, pp characteristics: higher input-output isolation, higher input impedance, high output impedance, higher gain or higher bandwidth. Figure 9: Cascode LNA Schematic VI. SIMULATION RESULTS In LNA design presents a considerable challenge because of its simulations requirement for high gain, low noise figure, good input and output matching and unconditional stability at the lowest possible current draw from the amplifier. The LNA is required to amplify incoming signals and extract them from the noisy environment, thus enabling signal processing by blocks further down the receiver chain. The gain provided by the LNA is generally defined in terms of the voltage gain (A V =V out /V in ) or power gain (S 21 = P out /P in ) [17]. There are several parameters, which are very important in the design and verification of low noise amplifiers and these parameters are simulated and presented below. The chosen scheme of the LNA was simulated using Cadence. AC input signal: The above AC input signal shows the analysis of Power in terms of alternative current. The graph is shown between time in seconds and Voltage in mv. After Observing the Waveform in the Figure we can see that a waveform signal contain in the Graph. (iii) LNA Schematic We used both Cascade LNA and Common LNA in LNA Schematic to achieve high gain as compared to single CMOS Cascade or Common LNA. LNA schematic is designed using Cadence Tool at 0.18 µm technologies µm means lower power consumption of the circuit. The circuit diagram of the Single-Ended LNA is shown in Figure 10. It employs inductive source degeneration (inductor L S connected to the source of transistor M 1 ) [2]. This method has the advantage that one has a greater control over the value of the real part of the input impedance through the choice of inductance. Cascode transistor M 2 is used to reduce the interaction of the tuned output with the tuned input. Figure 11: AC Input Signal Gain at frequency 8.72 GHz Figure 10: LNA Schematic Figure 12: Gain at frequency 8.72 GHz

6 MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, August 2013, pp Noise Figure: The overall noise figure is mainly determined by the first amplification stage, provided that it has sufficient gain. NF is the practical noise figure of a practical RF network and NF min is the ideal or a theoretical noise figure of a circuit, NF = NF min + matched network factor. Figure 13: NF and NF min parameters VII. CONCLUSION LNA has successfully developed with 3.85dB Noise Figure and 15.04dB Gain when the supply voltage is 1.8V only. From the analysis, it consumes four times smaller powers while achieving comparable gain and noise performance to the traditional Low Noise Amplifiers. The LNA is more suitable for RF Radio Receiver circuit whereas it can perform and work with maximum types of Noise Amplifiers. REFERENCES [1] Communications Receivers, Third Edition, Ulrich L. Rohde, Jerry Whitaker, McGraw Hill, New York, 2001, ISBN [2] Superhet Receiver.pdf... Crystal Radio and Superheterodyne Receiver by Ben Godfrey. [3] MOS Inverter, Digital Electronics INEL 4207 by Prof. Manuel Jimenez with contribution by Rafael A. Arce Nazario. [4] Buscar copias de Dr. Jimenez en Reproducciones ($1-$2) Digital circuits using MOS transistors [5] H.C. Lin and L.W. Linholm, An optimized Output Stage for MOS Integrated Circuits, IEEE Journal of Solid-State Circuits, Vol. 10, pp , April [6] R.C. Jaeger, Comments on An optimized output stage for MOS integrated circuits, IEEE Journal of Solid-State Circuits, Vol. 10, pp , June [7] LNA Design Using Spectra RF Application Note Product Version 5.0 December 2003 September by Cadence Design Systems. [8] R. Ramazan, Tutorial simulation of LNA, Linkoeping University, Sweden, [9] The Design of CMOS Radio Frequency Integrated Circuits, Thomas H. Lee. Cambridge University Press, [10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, [11] T.H. Lee, the Design of Cmos Radio Frequency Integrated Circuits, Cambridge University, [12] Sungkyung Park and Wonchan Kim, Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8, Consumer Electronics, IEEE Transactions on, Vol. 47, No. 0098, [13] D.K. Shaeffer, T. Lee, A 1.5V, 1.5GHz CMOS Low Noise Amplifier, IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May [14] Worcester Polytechnic Institute. Cadence Design Tools Tutorial. [15] ECE531 Cadence Simulation Tutorial by Haibo Wang Southern Illinois University Carbondale. [16] B. Razavi, CMOS Technology Characterization for Analog and RF Design, IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, March [17] Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 1987, Holt, Rinehart and Winston, Inc. [18] ZHANG H.; CHEN GUI; (2008): Design of a fully differential CMOS LNA for GHz UWB Communication Systems. [19] Pablo M.G.; Mohammad H. (2006): Design of a CMOS Low- Noise Amplifier,Stanford University. [20] J.P. Silver: MOS Differential LNA design Tutorial.