QPSK Modulation and Demodulation

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1 Report QPSK Modulation and Demodulation ELE 791 Software Radio Design Yinhua Wang Michael Chow Sheng-Mou Yu Dec 14 th 2004 Syracuse University Department of Electrical Engineering

2 1.Project Overview and Scope The stated goal of this project was to design and implement QPSK Modulator and Demodulator. The design consisted of two major sections: QPSK Modulator and QPSK Demodulator. This report outlines the design steps and outcome of the project, which include concept selection, functional specifications, and description of the final design. 2. Introduction: Digital modulation is the process by which digital symbols are transformed into waveforms that are compatible with the characteristics of the channel. Modulation can be used to minimize the effects of interference. Modulation can also be used to place a signal in a frequency band where design requirements, such as filtering and amplification, can be easily met. This is the case when radio-frequency (RF) signals are converted to an intermediate frequency (IF) in a receiver. 2.1 QPSK Modulation Phase Shift keying: Phase shift keying is a modulation process whereby the input signal, a binary PCM waveform, shifts the output waveform to one of a fixed number of states. The general analytic expression for PSK is s i (t)=(2e/t)^1/2*cos[ω 0 t+φ i (t)] 0 t T, i=1,,m,where the phase term φ i (t), will have M discrete values, typically given by φ i (t)=2πi/m time duration, and 0 t T i=1,...,m E is the symbol energy, T is symbol In BPSK modulation, the modulating data signal shifts the phase of the waveform si(t) to one of two states, either zero or π. If the modulating data stream were to consist of alternating ones and zeros, there would be an abrupt change at each transition. The signal waveforms can be represented as vectors or phases on a polar

3 plot ; the vector length corresponds to the amplitude, and the vector direction for the general M-ary case correspond to the signal phase relative to the other M-1 signals in the set. For BPSK, the vectors are formed by two 180 opposing vectors. In Figure 1, the binary vectors s1 and s2 positioned 180 apart. The decision boundary separates the signal space into two regions. On the figure is also shown a noise vector n equal in magnitude to s1. The figure establishes the magnitude and orientation of the minimum energy noise vector that would cause the detector to make a symbol error. In Figure 1, a 4-ary vector positioned 90 apart. The decision lines divide the signal space into four regions. A noise vector is drawn again to illustrate the minimum energy noise vector that would cause the detector to make symbol error. Note that the 4-ary system is more vulnerable to noise than the 2-ary system. The reason is that QPSK system encodes more hits of information than does BPSK. The maximum pulse rate (symbol rate) is proportional to its bandwidth. If the symbol rate is held constant for these two cases, the high-order system transmit more hits of information through the fixed bandwidth channel. Therefore, M-ary systems are termed bandwidth efficient. Decision Line(DL) s2 DL n s3 n s1 s2 s1 s4 M=2 M=4 Figure 1: MPSK Signal Set For M=2, QPSK : QPSK (4-ary PSK) involves changing the phase of the transmitted waveform. Each finite phase change represents unique digital data. A phase-modulated waveform can be generated by using the digital data to change the phase of a signal while its frequency and amplitude stay constant. A QPSK modulated carrier undergoes four

4 distinct changes in phase that are represented as symbols and can take on the values of π/4, 3π/4, 5π/4, and 7π/4. Each symbol represents two binary bits of data. The constellation diagram of a QPSK modulated carrier is shown in Figure 2. Figure 2: The constellation diagram of a OPSK modulated carrier Symbol Bits Expression Phase I Q S1 00 (2E/T)^1/2*cos(ωt+π /4) π /4 2^(-1/2) 2^( -1/2) S2 10 (2E/T)^1/2*cos(ωt+3π /4) 3π /4-2^(-1/2) 2^(-1/2) S3 11 (2E/T)^1/2*cos(ωt+5π /4) 5π /4-2^(-1/2) -2^(-1/2) S4 01 (2E/T)^1/2*cos(ωt+7π /4) 7π /4 2^(-1/2) -2^(-1/2) Table 1 : Four symbols mapping definitions for QPSK Note that I amplitude =( symbol expression ) * cos( phase ) Q amplitude =( symbol expression ) * sin( phase ) T shows the four symbols mapping definitions for QPSK. S1 represents symbol 1 which corresponds to the bits 00. Since the phase change of S1 is π/4, the expression of S1 is (2E/T)^1/2*cos( ωt +π/4 ) and it s represented as I = 2^(-1/2), Q = 2^(-1/2) on the IQ plane. S2 represents symbol 2 which corresponds to the bits 10.

5 The phase change of 3π/4 in S2 leads to the expression of (2E/T)^1/2*cos( ωt +3π/4 ) and it s represented as I = -2^(-1/2), Q = 2^(-1/2) on the IQ plane. S3 represents symbol 3 which corresponds to the bits 11. Since the phase change of S3 is 5π/4, the expression of S3 is (2E/T)^1/2*cos( ωt +5π/4 ) and it s represented as I = -2^(-1/2), Q = -2^(-1/2) on the IQ plane. S4 represents symbol 4 which corresponds to the bits 01. The phase change of 7π/4 in S4 leads to the expression of (2E/T)^1/2*cos( ωt +7π/4 ) and it s represented as I = 2^(-1/2), Q = -2^(-1/2) on the IQ plane Gray Code The system performance of a digital communication network can be enhanced by incorporating a coding technique, within the system, known as Gray coding. The gray encoder is used to map the data in such a way as to help reduce bit errors. A QPSK system takes the input data bits, two at a time, and creates a symbol that represents on of four phase states. The gray encoder therefore is used to map every two input data bits to one of four unique symbol values so that the bit pairs that are used to generate the symbols are only one bit different from each adjacent symbol. This technique proves to help with error performance because if a symbol is received in error, it will contain only one error bit if it was received in error to an adjacent symbol. This can be more easily observed by viewing the QPSK constellation diagram that is shown in Figure 2. This QPSK constellation diagram shows symbols, each represented by two data bits that were first gray encoded. One can see that each adjacent symbol is represented by two data bits that vary by one bit. The performance of digital communication networks can further be enhances by the use of error correcting codes QPSK Modulator: Figure represents the process of a QPSK modulator. First, the input binary bit stream is split into two bit streams which are the even and odd bit streams (in-phase and quadrature streams) by the serial to parallel converter. Then, send alternating bits to I, Q :even bits to Q channel, odd bits to I channel Second, using the method of NRZ, the even and odd bits are converted from a unipolar sequence to a bipolar sequence (0 to -1 ). Next, multiply Q channel with a sine of fc and multiply I channel with a sine but shifted by 90 degree which is cosine. Notice that the 90 degrees block in the figure transmits the upper sine sequence to the lower -cosine sequence. Finally, combining or adding the upper (I) and lower ( Q ) parts and passing the result through a harmonic or channel filter will get the QPSK modulated output.

6 Figure3 :QPSK Modulator Figure shows the mathematic representation of the process of the QPSK modulator. First, the data stream is divided into two parts, the left side of the data stream represents the even part and the right side represents the odd part. Then, the 0 in both the even and odd parts are converted into -1 while the 1 keep the same. Next, the even part is multiplied by (2E/T)^1/2*sin(ωt) to be Q. On the other hand, the odd part is multiplied by (2E/T)^1/2*sin(ωt) to be I. Therefore, the upper part becomes a group of sine sequences and the lower part, the cosine sequences. After adding I and Q, the result is a matrix of (2E/T)^1/2*cos( ωt +π/4 ), (2E/T)^1/2*cos( ωt +3π/4 ),(2E/T)^1/2*cos( ωt +5π/4 ), and (2E/T)^1/2*cos( ωt +7π/4 ).

7 Figure 4 :The Mathematic representation of the process of the QPSK modulator Figure 5 shows the Simulink of the QPSK Modulator. In the figure, we use a pulse generator to represent the input bit streams, then we make a scope right after it to see how its waveform behaves every time we change the components or coefficients in the schematic. The unipolar to bipolar converter is used to transform bit sequences into polar signals(convert 0 to -1).Another scope is put after the converter to see how the waveform has changed. Next, we use two product components to multiply the sine and cosine to the outputs of the converters respectively. At last, an add components sums the upper and lower parts up to get the result. We put a scope after to observe its waveform as well. Figure5 :Simulink of the QPSK Modulator Figure 6 shows the waveform for components in the schematic. On the left side are two scopes which represent the input bit streams. The upper left and the lower left scopes illustrate the even and odd bits respectively. i.e., 10, 00 input sample go through the modulator to get sin wave with different phase respectively.

Figure 6:The scopes of the schematic 2.2 PSK Demodulation 2.2.1 PLL Phase-locked loops (PLL) are frequently used in Communication applications.

8 Figure 6:The scopes of the schematic 2.2 PSK Demodulation PLL Phase-locked loops (PLL) are frequently used in Communication applications. For example, they recover the clock from digital data signals, and recover the carrier from satellite transmission signals, perform frequency and phase modulation and demodulation, and synthesize exact frequencies for receiver tuning Phase-lock loops (PLL) have been one of the basic building blocks in modern communication systems. They have been widely used in communications, multimedia and many other applications. The theory and mathematical models used to describe PLL come in two types: linear and non-linear. Non-linear theory is often complicated and difficult to deal with in real-world designs. There are many kinds of Phase Lock Loops; the Costas Loop, which is named by J.P. Costas, a pioneer in synchronous

9 communications, is chosen for this experiment. The reason is that the implementation is quite simple and the structure is very powerful and useful in many situations. Principles of PLL A PLL is a circuit, which causes a particular system to track with another one. More precisely, a PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized (called locked) state the phase error between the oscillator s output signal and the reference signal is zero or very small. If a phase error builds up, a control mechanism acts on the oscillator in such a way that the phase error is again reduced to a minimum. In such a feedback control system the phase of the output signal is actually locked to the phase of the reference signal. This is why it is referred to as a phase-locked loop. The operating principle of the PLL is explained by the example of the linear PLL. The PLL consists of three basic functional blocks: 1 A voltage-controlled oscillator (VCO) 2 A phase detector (PD) 3 A Loop filter (LF) Figure 7 VCO BLOCK the PLL circuit are defined as follows

10 The reference (or input) signal U 1(t) The angular frequency ω1 of the reference signal The output signal U 2(t) of the VCO The angular frequency ω2 of the output signal The output signal U d(t) of the phase detector The output signal U f(t) of the loop filter The phase error θe, defined as the phase difference between signals U1(t) and U2(t).Let us now see how the three building block work together. First, we assume that the angular frequency of the input signal U1(t) is equal to the center frequency ω0. The VCO then operate at its center frequency ω0. As we see, the phase error θe, is zero. If θe is zero, the output signal Ud of the phase detector must also be zero. Consequence the output signal of the loop filter Uf will also be zero. This is the condition that permits the VCO to operate at its center frequency If θe were not zero initially, the phase detector would develop a nonzero output signal Ud, After some delay, the loop filter would also produce a finite signal Uf, This would cause the VCO to change its operating frequency in such a way that phase error finally vanishes Assume now that the frequency of input signal is changed suddenly at tim we t0 by the amount. As shown in the phase of the input signal then starts leading the phase of the output signal. A phase error is built up and increases with time. The phase detector develops a signal, which also increases with time. With a delay given by the loop filter, Uf(t) will also rise. This causes the VCO to increase its frequency. The phase error becomes smaller now, and after some settling time the VCO will oscillate at a frequency that is exactly the frequency of the input signal. Depending on the type of loop filter used, the final phase error will have been reduced to zero or to a finite value.

Figure 8 Transient response of a PLL onto step variation of the reference frequency a) Reference signal u1(t) b)output signal u2(t) of the VCO c)the phase difference between signals θe(t) as a

11 Figure 8 Transient response of a PLL onto step variation of the reference frequency a) Reference signal u1(t) b)output signal u2(t) of the VCO c)the phase difference between signals θe(t) as a function of time. d) Frequency ω2 of VCO e) Frequency ω1 of the reference signal One of the most intriguing capabilities of the PLL is its ability to suppress noise superimposed on its input signal. Let us suppose that the input signal of the PLL is buried in noise. The phase detector tries to measure the phase error between input and output signals.the noise at the input causes the zero crossings of the input signal U1(t) to be advanced or delayed in a stochastic manner. This causes the phase detector output signal U d(t) to jitter around an average value. If the corner frequency of the loop filter is low enough, almost no noise will be noticeable in the signal U f(t), and the VCO will operate in such way that the phase of the signal U2(t) is equal to the average phase of the input signal U1(t). Therefore, we can state that the PLL is able to detect a signal that is buried in noise. These simplified consideration have shown that the PLL is nothing but a servo system which controls the phase of the output signal U2(t)

Figure 9 Some typical exciting functions as applied to the reference input of a PLL a) Phase error applied at t=0,b) Frequency step applied at t=0 c)frequency ramp starting at t=0 lists a number of

12 Figure 9 Some typical exciting functions as applied to the reference input of a PLL a) Phase error applied at t=0,b) Frequency step applied at t=0 c)frequency ramp starting at t=0 lists a number of phase signals which are frequently used to excite a PLL. We will not lose too much time considering nonlinear PLL models but will show the most important phenomena by means of a simple analogy. For the engineer it is not of major concern to know exactly what the PLL does when it is in the unlocked state. The interesting questions are rather Under what condition will the PLL get locked? How much time does the lock-in process need? Under what condition will the PLL lose lock? According to the Reference Paper, as already stated there is no exact solution for this problem. But we found that it is almost identical to the differential equation of a somewhat special mathematical pendulum.and we could get conclusion that Roland E. Best,Phase locked Loops: Design,Simulation, and Applications,3 rd Edition, McGraw-Hill, Three Condition

13 The frequency of the reference signal must be within the hold range The maximum frequency step applied to the reference input of a PLL must be smaller than the pull-out range The rate of change of the reference frequency must be lower than (ωn)^2 Whenever a PLL has lost tracking because one of these conditions has not been fulfilled, the question arises whether it will return to stable operation when all the necessary conditions are met again. The answer is clearly no.for a PLL, this means that buildup of the phase error will decelerate if the reference-frequency offset is decreased below another critical value, the PULL-IN frequency. If the slope of the average phase error becomes smaller, the frequency of the VCO more and more approaches the frequency of the reference signal, and the system will finally lock. The pull-in frequency is markedly smaller than the hold range, as can be expected from the mechanical analogy. The pull-in processor is relatively slow one. In most practical applications it is desired that the locked state be obtained within a short time period. A PLL can become locked within one single-beat note between reference frequency and output frequency, provided the frequency offset is reduced below a critical value called the lock range. This process is called the LOCK-IN process. The LOCK-IN process is much faster than the pull-in process, but the lock range is smaller than the PULL-IN range. The hold range :PLL can statically maintain phase tracking.a PLL is conditionally stable only within this range, static limits of stability The hold range : This is the frequency range in which a PLL can statically maintain phase tracking.a PLL is conditionally stable only within this range The pull-out range :This is the dynamic limit for stable operation of a PLL The pull-in range:this is the range within which an LPLL will always become locked, but the process can be rather slow dynamic limit of stability The lock range : Normally the operating frequency range of an LPLL is restricted to the lock range Figure 10 Scope of the static and dynamic limits of stability of PLL

14 FIGURE 11 PLL BY SIMULINK Figure 12 PLL Waveform

15 As shown in Figure 11 is that PLL Designed by SIMULINK. Though it we could see the whole processing clearly. Scope 3, is the Sine wave, i.e. our input signal.and Scope 1, is the signal out of the VCO.Scope 2 is showing the signal out of the Low pass filter, and it also represent the how PLL operate to get the final locked. Phase of input signal is 3*pi/4, and from the Figure 12 we see the VCO do not have the same initial phase.however they have the same frequency, i.e. that VCO oscillate at a frequency that is exactly the frequency of the input signal. And final phase error will be reduced to zero. It make me understand the principle of PLL deeply Demodulation: It might appear that QPSK offers advantages over ASK, FSK, and PSK. However, the demodulation of these signals requires various degrees of difficulty and hence expense. The method of demodulation is an important factor in determining the selection of a modulation scheme. We know that there are two types of demodulation, which are distinguished by the need to provide knowledge of the phase of the carrier. Demodulation schemes requiring the carrier phase are termed coherent. Those that do not need the phase are termed incoherent. And Incoherent modulation is inexpensive but has poorer performance. Coherence demodulation requires more complex circuitry, but has better performance. The demodulation process can be divided into three major subsections. As shown by Figure 13. First, since the incoming waveform is suppressed carrier in nature, coherent detection is required. The methods by which a phase-coherent carrier is derived from the incoming signal are termed, carrier recovery, and will be covered first. Next, the raw data are obtained by coherent multiplication, and used to derive clock-synchronization information. The raw data are then passed through the channel filter, which shapes the pulse train so as to minimize inter symbol interference distortion effect. This shaped pulse train is then routed, along with the derived clock, to the data sampler which outputs the demodulated data Figure 13 Carrier Recovery

16 The Costas Loop The conventional Coastas Loop for BPSK suppressed carrier recovery is shown in Figure 12 Figure 14 Coastas Loop How does it work? From the following calculation, we may see the theatrical process -Input X(t) = k cos (ωt +ψ)+n(t) -Output of upper LP filter S1(t)=1/2kcos(ε- ψ)+1/2x(t)cos ε +1/2y(t)sin(ε) Zc(t)=1/2k cos(ε- ψ) -Output of lower LP filter S2(t)=1/2ksin(ε- ψ)+1/2x(t)sin ε +1/2y(t)cos(ε) Zs(t)=1/2ksin(ε- ψ) -Input to loop filter S3(t)=1/8c^2 sin2(ε- ψ) The Costas loop performs both phase-coherent suppressed carrier reconstruction and synchronous data detection within the loop. The upper loop is referenced to as the quadrature, or tracking loop and functions as a typical PLL, providing a data-corrupted error signal, The lower in-phase, or decision loop provides data extraction at the output of the lower mixer, and corrects the data corruption, The corrected error signal is applied through loop filter to the VCO, according to the reference paper, a limiter introduces a signal suppression factor into the analysis which can improve or degrade performance. Results indicate that for higher E/No ratios, there is an actual improvement in the loop s squaring loss.

17 . Figure 15 Hard-limited Costas Loop Note Hard-limited: When the voltage of the input is way different from VCO, it will waste a lot of time for VCO to keep tracking until it matches the voltage of input. Therefore, in the beginning, the VCO sets a range of voltage, if the incoming voltage is a lot different from the voltage of VCO; it will directly make this input voltage to be in the specification of range, i.e. -1 to 1. The purpose of doing hard-limit is to save time. Figure 15 shows a very common implementation called the hard-limited,or polarity loop modified (hard-limited), Costas-loop used for the demodulation of QPSK signals. Figure 16 QPSK Costas Loop

18 Figure 17 QPSK Demodulator by simulink Figure 18 QPSK Demodulator

19 Scope 4, the first one in the row, is input,sine wave, Scope 3, the secod in first row, the wave represents signal out of VCO, Scope 6, the third in the top, represent the hard limit, Scope 5, the first in the below, represents that the 90 degree shift, and Scope 2, it shows that the whole processing of Demodulator, and Scope 1,it shows that the hard limit. From 6 scopes, we could draw conclusion that the demodulate is evolved from the PLL, and its function is that make the data-out signal the same frequency and phase finally, so it is easy to detect. So it is the step of demodulator. 3. Conclusion: Within our limitations, we could able to design QPSK Modulator and Demodulator with SIMULINK, as dynamic systems in a block diagram format. And understand the principles of PLL (Frequency synchronization) and Carrier Loop. Our future work is that we will continue writing MATLAB code to achieve the processing of our modulation and demodulation.

20 Reference [1].Schwartz, M. Information Transmission, Modulation, and Noise, McGraw Hill, New York, [2]. Blanchard, A., Phase Locked Loops, Wiley, New York, 1976, [3]. a. Simon, M. K., and Lindsey, W. C., Optimum Performance of Suppressed Carrier Receivers with Costas Loop Tracking, IEEE Transactions on Communications, VOL COM-25, No. 2 (Feb. 1977) pp. [4].Simon, M. K., Tracking Performance of Costas Loops with Hard-Limited In Phase Channel, IEEE Transactions on Communications, VOL COM-26, No, 4, April1978, pp [5]. Le-Ngoc, T., and Feher, K., A Digital Approach to Symbol Timing Recovery Systems, IEEE Transactions on Communications, VOL COM-28, No. 12, Dec. 1980, pp [6]. Texas Instrument Applications Report, Bulletin SCA-206, Digital Phase-Locked Loop Design using [7]. Feher, K., and DeCristofaro, R., Transversal Filter Design and Application in Satellite Communications, IEEE Transactions on Communications, VOL COM-24, No. 11, Nov. 1976, pp [8]. Digital Communications: Fundamentals and Applications (2nd Edition) Bernard Sklar

Chapter 4. Part 2(a) Digital Modulation Techniques

Chapter 4. Part 2(a) Digital Modulation Techniques Chapter 4 Part 2(a) Digital Modulation Techniques Overview Digital Modulation techniques Bandpass data transmission Amplitude Shift Keying (ASK) Phase Shift Keying (PSK) Frequency Shift Keying (FSK) Quadrature