Real-Time Processing of Multi-Frequency Eddy Currents Testing Signals

Transcription

1 Real-Time Processing of Multi-Frequency Eddy Currents Testing Signals Luis S. Rosado Instituto de Telecomunicações, Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento, Instituto Superior Técnico, Universidade Técnica de Lisboa, Lisbon, Portugal luis.rosado@ist.utl.pt Moisés Piedade Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento, Instituto Superior Técnico, Universidade Técnica de Lisboa, Lisbon, Portugal msp@inesc-id.pt Abstract In this paper, a real-time Digital Signal Processing (DSP) architecture is proposed to generate and process multi-frequency signals for eddy currents testing. This architecture was implemented on a dedicated instrument whose processing core is a Field-Programmable Gate Array (FPGA) for DSP purposes. Stimulus generation is achieved using Direct Digital Synthesis (DDS) with some improvements to remove spurious frequency components. An In-phase and Quadrature (IQ) demodulation scheme is implemented to estimate the real and imaginary part of the probes output signals. A Cascaded Integrator Comb (CIC) decimator is used to lower the sampling frequency allowing narrowband IIR filtering using low resources. The proposed architecture is able to generate and process the stimulus and input data at 125 MSamples/s and to estimate the input data components at 1.25 MSamples/s rate for frequencies between 5 khz and 1 MHz. Keywords Eddy Currents Testing; Digital Signal Processing; Multi-Frequency Stimulus;Field-Programmable Gate Array; I. INTRODUCTION Non-Destructive Testing (NDT) is an important tool to ensure components reliability on a broad range of industries. From the several available testing methods, eddy currents and ultra-sonic methods have become the most commonly applied to in service metallic components whose failure may lead to human, economic or environmental losses. The eddy currents method [1] is based on the induction and sensing of electrical currents on the surface of the metallic components through electromagnetic principles. Typically, a probe featuring a coil is positioned on the surface of the component under test. This coil carries a sinusoidal alternating current producing a time varying magnetic field and inducing the eddy currents on the superficial layers of the component. Interactions between the eddy currents and existent defects modify the magnetic field. Detection and characterization of the defects is then possible by measuring the changes in the coil electrical impedance. Tiago Catarrunas Instituto Superior Técnico, Universidade Técnica de Lisboa, Lisbon, Portugal tiago.catarrunas@ist.utl.pt Pedro M. Ramos Instituto de Telecomunicações, Instituto Superior Técnico, Universidade Técnica de Lisboa, Lisbon, Portugal pedro.m.ramos@ist.utl.pt The frequency used on the coil current is an important parameter since it determines the distribution of the eddy currents density. For a given frequency f, the eddy current density at depth x is ( ) J x J e x π fµσ = (1) where J is the current density at the surface ( x= ), µ is the magnetic permeability and σ the electrical conductivity of the material. Using multiple frequencies while testing, increases the information acquired and allows enhanced defects detection and characterization. The use of several frequencies can be implemented multiplexing the selected frequencies periodically or using arbitrary spectrum stimulus. Yet, its implementation by multiplexing will decrease testing speed. The referred advantages motivated the research of synthesizing and demodulation techniques dedicated for multi-frequency stimulus. In [2] the advantages of using multiharmonic signals were experimentally demonstrated. Demodulation is achieved by computing a spectrogram of the digitally acquired testing signals. Another multi-frequency technique was evaluated on the corrosion detection on multilayered structures in [3]. The improved detectability of hidden corrosion was experimentally demonstrated. Other approaches use pulsed waveforms and the corresponding spectral composition as stimulus. This approach doesn t allow as much flexibility on the selection of test frequencies and amplitudes since the stimulus spectrum is determined by the waveform time-domain parameters. Advantages such as immunity to electromagnetic interferences and simple stimulus synthesizing motivated the development of dedicated eddy current probes [4]-[5]. Processing of the testing signals can be done in the frequency domain as in [6] and [7]. More frequently, time domain features are extracted from the testing signals and used to detect defects as in [8] and [9]. In this work, a Digital Signal Processing (DSP) architecture able to process eddy currents testing with multi-frequency

2 signals is presented. This architecture was developed targeting a DSP based eddy currents instrument previously presented in [1]. This instrument was specially developed to operate a new eddy current probe type which demonstrated very good results on the inspection of Friction Stir Welding Joints [11]. The instrument features a Xilinx FPGA XC3SD34A processing core with more than one hundred dedicated multiply and accumulate units. Data conversion is done using external 14 bit analog to digital (ADC) and digital to analog converters (DAC) operating at 125 MSamples/s. Inside the FPGA, a softcore processor is assigned to control, communications and low speed DSP tasks. The main DSP operations are performed in peripherals connected to the processor. In the next sections, the development of peripherals for multi-frequency signals generation and demodulation is described. II. STIMULUS GENERATION Generation of the multi-frequency stimulus is done by combining the outputs from several Direct Digital Synthesis (DDS) sinusoidal waveform generators as shown in Figure 1. In each DDS, the amplitude, phase and frequency of each frequency component can be adjusted so the desired stimulus can be synthesized. Although the phase is not an important parameter when using multi-frequency stimulus in general, it is an important parameter to generate multi-harmonic stimulus with low crest factor (maximizing the energy within the dynamic range). In addition to the main output, each DDS generates two sinusoidal references which are used by the developed demodulator. The internal structure of each DDS is represented in Figure 2. Basically, a accumulator generates a sawtooth waveform whose MSBs are used to address a sine/cosine Look-Up Table (LUT). Frequency is set by the accumulated constant, the phase offset is included on the LUT address word and the amplitude appears multiplied on its output. It should be noted that the address is truncated otherwise large LUT sizes would be required. Figure 1. Multi-frequency stimulus generator. The quality of the synthesized signals and references is an important aspect since it influences both the output stimulus and the demodulation of the signals. An identified issue on DDS based waveform generation are the spurious components caused by the phase truncation [12]. These spurious components are normally located at frequencies multiple of the generated signal fundamental frequency. Its amplitude also depends on the signal fundamental frequency. Thus, the presence of these spurious components should be evaluated on the overall range of synthesizable frequencies. To cope with this issue, two correction mechanisms were simultaneously implemented on the designed DDS. Figure 2. DDS internal structure. To reduce the number of truncated bits without increasing table size, linear interpolation is included. Although this solution requires an additional table which generates an additional point required for a linear regression, interpolation can save substantial memory resources (mainly when using high interpolation ratios). The other correction mechanism, known as phase dithering, is based on the addition of a pseudo-random value to the instantaneous phase. This introduction reduces the periodic repetition of the LUT points at the DDS output reducing the spurious components magnitude. The cost of this randomization is reflected on an higher noise floor (which depends on the magnitude of the added pseudo-random value). Figure 3 shows the effect of the used mechanisms on the quality of a 1 MHz synthesized sinusoidal signal using a LUT with 124 points. The selected interpolation ratio was 32 and the dithering value has 22 bits width. As shown, using both the mechanisms, the Spurious Free Dynamic Range (SFDR) was improved by almost 3 db db 6.2 db No correction x 1 7 With interpolation 78.3 db x 1 7 With interpolation and dithering x 1 7 Figure 3. Frequency spectrum for a 1 MHz synthesized sinusoidal signal without any correction mechanism (top), using only interpolation (middle) and with interpolation and phase dithering (bottom) simulataneously.

3 To evaluate the synthesized single frequency signals, the SFDR was computed on 1 logarithmically spaced frequency values between 1 khz and 1 MHz, Figure 4. As shown, the worst SFDR for the single frequency waveform was db. would have significant bias levels if no correction mechanisms were implemented. 85 SF DR[dB] Figure 4. Single Frequency SFDR between 1 khz and 1 MHz. III. SIGNALS DEMODULATION Estimation of the multi-frequency input signals parameters is done using IQ demodulation, a commonly used technique on the demodulation of radio-frequency signals as described in [13]. In this demodulator, the input signal is multiplied by two references (in phase and in quadrature with the output stimulus) of each frequency component as shown in Figure 5. At the multipliers output, the input signal is down-converted with the reference frequency being positioned at the spectrum origin. Alongside, a replica of the input signal spectrum is created with the reference frequency shifted towards twice its value. As the reference amplitude is constant and with unitary amplitude, the mean value of the multipliers outputs can be taken as estimates of the real and imaginary components of the probe output signal (after its multiplication by two). To remove the remaining and unwanted frequency components the signal must be low pass filtered. The filtering chain is composed by two different types of filters to achieve an overall cut-off frequency of 1 khz. A Cascaded Integrator Comb (CIC) filter is firstly used to cut components higher than 625 khz and to decimate the input sampling rate by a factor of 1 to 1.25 MSamples/s. Its function is to remove components that otherwise may cause aliasing on the decimation process. At a lower data rate, the implementation of a narrow band filter becomes easier thus justifying the decimation process. The final estimates are achieved by filtering the signal with a fourth order Infinite Impulse Response (IIR) filter. After the two filtering stages, the estimates are compensated for the IQ demodulator gain (by doubling its value shifting the binary number) and for the analog amplification gain (using the Microblaze soft-processor). As described on Section II, the quality of the DDS synthesized signal and references may have a significant influence on the quality of the demodulation. If the described spurious components appear at both the input and the references used by the IQ demodulator, its combination at the multiplier output will result on an additional DC component. Thus, the estimates for the real and imaginary components A. CIC decimator Figure 5. Multi-frequency IQ demodulation. The CIC decimator [14] is composed by a section of integrator stages, a decimation register and a section of comb stages, Figure 6. The main advantages of this type of filtering structures are its simple implementation and an efficient use of resources since multiplications are not required. Input Integrators Section... N Fs/R... - Figure 6. CIC decimation filter. COMB Section N M - Output Configuration of the filter response is done by selecting suitable values for the number of integrators and comb stages (N), the number of delays in each comb stage (M), and the decimation ratio (R). The values N = 4, M = 2 and R = 1 were selected using a filter simulation tool so an attenuation of at least 5 db is achieved after the Nyquist limit stated for the output sampling rate. The filter magnitude frequency response (normalized to the input sampling rate) is sin( ) ( ) N π RMf H f = sin π f ( ). (2) This response has a low pass profile and, as highlighted on equation (2), has periodic notches at integer multiples of 1 RM f=. The frequency response of the implemented filter is shown in Figure 7. The integrator section operates at the input sampling rate (125 MSamples/s) thus it was decided to assign a dedicated adder to each stage. In a first approach, the comb section was pipelined, including a register between each stage, and an adder was also assigned to each operation required. Since this section operates at the output sampling rate (1.25 MSamples/s),

4 serialization can be used in order to reduce the resources needed. Another advantage that resulted from this process is the possibility of using dedicated continuous memory instead of the distributed memory making a more efficient overall use of the FPGA resources. A datapath was designed to perform the comb section operations. The control of the operations is done by a Finite State Machine. A maximum operation frequency of 183 MHz can be used to clock the serial comb section and a total of 12 cycles are required to process each input. To avoid generating additional clock references, the 125 MHz is used on the integrators section and thus up to 8 channels can be processed by the same serial comb section. H [db] 5 CIC IIR Figure 7. Implemented CIC and IIR filters frequency response. B. IIR Narrow-Band filtering To filter the decimated signal in a way such that the adjacent frequency components can be removed, a fourth order IIR filter was used. The IIR filter was designed so it has a lowpass cut-off frequency at 1 khz and at least 4 db attenuation at 5 khz. Although the cut-off frequency may seem high, this value enables the estimator to perform well even when testing at high speed (note that this value is inherently related with the filter response transient time). Nevertheless, the filter coefficients can be easily modified accordingly with the testing requirements. The minimum attenuation at 5 khz defines the minimum frequency gap between adjacent components that can be properly demodulated. The filter coefficients were obtained using the Butterworth design method and two cascaded biquadratic sections were used to implement the filter. This decision was taken to reduce the coefficients quantification influence on the filter response and to allow easy modification of the filter if necessary. Each biquadratic section is as shown in Figure 8 and implements a second order filter with transfer function B B z B z 1 2 H( z) = K 1 A z A z , (3) where B to B are the zeros coefficients while A and A are the poles coefficients. As done in the CIC comb section, a serial computing architecture was designed to save FPGA resources. This serial architecture operates at 125 MSamples/s and to handle all the operations required on each biquadratic section six clock cycles are required. Thus, it was decided to process on the same serial architecture the samples (arriving at 125 MSamples/s) from 16 channels. The cascaded biquadratic sections frequency response is shown in Figure 7. Figure 8. IIR Biquadratic section. IV. EXPERIMENTAL RESULTS In this section application examples of the proposed architecture are illustrated. A signal composed of four harmonic components was synthesized and demodulated while testing an artificial defect with the eddy currents probe presented in [11]. The defect is a surface breaking notch with.4 mm width and.5 mm depth processed using Electro- Discharge Machining (EDM) on an aluminum sample. The selected frequency components are 1 MHz, 4 MHz, 7 MHz and 1 MHz and its amplitudes were made equal to a quarter of the DAC dynamic range. The DDS synthesized signal was acquired and later processed using Fast Fourier Transform to obtain the result in Figure 9. The eddy currents probe output signal was also acquired, subject to the same processing and represented on Figure 9. As shown in the figure, frequency components on the probe output have different magnitudes since the probe sensitivity increases with the operating frequency. Also, the presence of noise can also be observed DDS output x 1 7 Probe output x 1 7 Figure 9. Four frequencies synthesized stimulus and probe output spectrum. The real and imaginary part of each frequency component of the input signal were registered while moving the eddy currents probe over the defect, Figure 1. The defect is located at X = 1 mm and the probe is moved in a 2 mm sweep. The differential operation of the probe makes the output value close to zero when the defect is away from the probe (in example for X values smaller than 5 mm). As soon as the probe overlaps the defect, each frequency component increases describing a pattern symmetric to the defect location. As described, the probe sensitivity increases with the operating frequency thus, the real and imaginary components of the higher frequencies of the signal have higher amplitude.

5 Real[V ] 1 x MHz 4 MHz 7 MHz 1 MHz On Figure 12, the real and imaginary components of the 1 khz frequency show the presence of substantial noise. This is a consequence of the analog amplification gain which was selected so the high amplitude of the highest frequencies does not result in analog saturation. One possible solution to this issue (which happens due to the unequal probe sensitivity) would be the amplitude scaling of the generated components inversely with its frequency. x khz 2 khz 1 2 MHz khz 5 khz 2 MHz 5 MHz 2 khz 5 khz 2 MHz 5 MHz 5 khz 1 MHz 5 MHz 1 MHz Imaginary[V ] x Figure 1. Demodulated input signal real (top) and imaginary part (bottom) for each frequency component of the four components signal. An additional multi-frequency signal was evaluated using the proposed architecture. In this signal, a set of seven of frequencies (1 khz, 2 khz, 5 khz, 1 MHz, 2 MHz, 5 MHz and 1 MHz) with amplitude equal to 1/7 of the available dynamic range were generated. Figure 11 shows both the DDS output and the probe output for this signal. Notice that the spectrum of the probe output is truncated to 2 MHz to proper show the lowest frequency components. The probe response using the described stimulus is shown in Figure DDS output x Probe output x 1 7 Figure 11. Eight frequencies synthesized stimulus and probe output spectrum. Real[V ] Imaginary[V ] x Figure 12. Demodulated input signal real and imaginary part for each frequency component of the eight components signal. V. CONCLUSIONS A DSP based processing architecture able to generate multi-frequency stimulus and to process eddy currents testing signals was described. The proposed approach makes use of DDS signal generation and IQ demodulation to achieve real time processing at 125 MSamples/s. Implemented spurious correction mechanisms allowed to achieve almost -9 db frequency SFDR on the stimulus generation. The developed demodulation of the input signal real and imaginary parts estimates up to 1.25 MSamples/s for frequencies between 5 khz and 1 MHz. The developed architecture can be easily modified and scaled to process stimulus with more than eight frequencies. Experimental results confirmed the correct operation of the method in two different illustration cases.

6 Further developments will focus on the statistical characterization of the generated IQ estimates and some minor improvements to reduce the amount of required FPGA resources for both signal generation and demodulation. The reduction of the peak value of the synthesized stimulus using optimization procedures on the different frequencies phases will also be considered. This will allow the improvement of the signal to noise ratio for the same available dynamic range and the consequent gains on the demodulation process. Other developments will focus the time multiplexing of different sets of up to eight frequencies to expand the number of measured frequencies during a single probe sweep. The development of a FPGA signal generation and demodulation architecture for pulsed eddy currents stimulus will also be addressed soon. ACKNOWLEDGEMENTS The authors would like to acknowledge Fundação para a Ciência e Tecnologia (FCT) for its financial support via the PhD scholarship FCT-SFRH/BD/6586/29 and projects PEST-OE/EEI/LA21/211 and PTDC/EEI-PRO/3219/212 and also the project IMAGIC FP The first author would also like to acknowledge IEEE IMS for the travel grant given to attend the I2MTC 213 conference. REFERENCES [1] J. Martín, J. Gil, E. Sánchez, "Non-Destructive Techniques Based on Eddy Current Testing," Sensors, vol. 11, pp , 211. [2] T. Chady, M. Enokizono, "Multi-frequency Exciting and Spectrogrambased ECT Method," Journal of Magnetism and Magnetic Materials, vol , pp. 7-73, 2. [3] D. Bos, S. Sahlén, J. Anderson, "Automatic Scanning With Multifrequency Eddy Current on Multi-layered Structures." Proceedings of the 15 th World Conference on Non-Destructive Testing (WCNDT), Rome, Italy, October 2. [4] L. Shu, H. Songling, Z. Wei, Y. Peng, "Study of pulse eddy current probes detecting cracks extending in all directions," Sensors and Actuators A, vol. 141, pp. 13 9, 28. [5] L. Shu, H. Songling, Z. Wei, "Development of differential probes in pulsed eddy current testing for noise suppression," Sensors and Actuators A, vol. 135, pp , 27. [6] Y. He, M. Pan, F. Luo, G. Tian, "Pulsed Eddy Current Imaging and Frequency Spectrum Analysis for Hidden Defect Nondestructive Testing an Evaluation," NDT&E International, vol. 44, pp , 211. [7] D. He, M. Yoshizawa, "Saw-Wave Excitation Eddy-Current NDE Based on HTS RF SQUID," IEEE Transactions on Applied Superconductivity, vol. 13, n. 3, 23. [8] I. Abidin, C. Mandache, G. Tian, M. Morozov, "Pulsed eddy current testing with variable duty cycle on rivet joints," NDT&E International, vol. 42, pp , 29. [9] Y. He, F. Luo, M. Pan, F. Weng, X. Hu, J. Gao, B. Liu, "Pulsed Eddy Current Technique for Defect Detection in Aircraft Riveted Structures," NDT&E International, vol. 43, pp , 21. [1] L. Rosado, M. Piedade, P. Ramos, T. Santos, P. Vilaça, A Reconfigurable Digital Signal Processing System for Eddy Currents Non-Destructive Testing, Proceedings of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Austin, EUA, May 21. [11] L. Rosado, T. Santos, M. Piedade, P. Ramos, P. Vilaça, Advanced Technique for Non-Destructive Testing of Friction Stir Welding of Metals, Measurement, vol. 43, n. 8, pp , 21. [12] "A Technical Tutorial on Digital Signal Synthesis," Analog Devices, [13] B. Priyanto, C. Law, Y. Guan, "Design & implementation of all digital I-Q modulator and demodulator for high speed WLAN in FPGA," Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and signal Processing (PACRIM), August 23. [14] E. Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 29, n. 2, 1981.