An Adaptive Tuning Mechanism for Phase-Locked Loop Algorithms for Faster Time Performance of Interconnected Renewable Energy Sources

Transcription

1 .9/TIA , IEEE Transactions on Instry Applications An Aaptive Tning Mechanism for Phase-Locke Loop Algorithms for Faster Time Performance of Interconnecte Renewable Energy Sorces Lenos Hajiemetrio, Elias Kyriakies Department of Electrical an Compter Engineering KIOS Research Center, University of Cyprs Nicosia, Cyprs Free Blaabjerg Department of Energy Technology Aalborg University Aalborg, Denmark Abstract Interconnecte renewable energy sorces reqire fast an accrate falt rie throgh operation in orer to spport the power gri when falts occr. This paper proposes an aaptive Phase-Locke Loop (aaptive αβpll) algorithm, which can be se for a faster an more accrate response of the gri sie converter control of a renewable energy sorce, especially ner falt rie throgh operation. The aaptive αβpll is base on moifying the tning parameters of the αβpll accoring to the type an voltage characteristics of the gri falt with the prpose of accelerating the performance of the phase-locke loop algorithm. The propose aaptive tning mechanism ajsts the PLL parameters in real time accoring to the propose falt classification nit in orer to accelerate the synchronization performance. The beneficial effect of the propose aaptive tning mechanism on the performance of αβpll is verifie throgh simlation an experimental reslts. Frthermore, the benefits of sing a faster synchronization metho on the control of the GSC of RES are also emonstrate in this paper. Aitionally, a new synchronization techniqe name FPD-αβPLL is presente, which applies a freqency-phase ecopling techniqe from the literatre in the strctre of αβpll with the prpose of improving the performance of αβpll. Finally, the aaptive tning mechanism propose in this paper is combine with the FPD-αβPLL in orer to introce the aaptive FPD-αβPLL, which presents an even faster time performance an is an ieal soltion for the synchronization of RES ner gri falts. I. INTRODUCTION Interconnecte Renewable Energy Sorces (RES) reqire Rie Throgh (FRT) capability accoring to gri reglations []-[5], in orer to provie voltage an freqency spport to the gri, when falts occr. Therefore, the fast an accrate performance of RES ner FRT operation is very critical in orer to avoi any cascaing an catastrophic events to the power system case by low-voltage gri falts. «This work was co-fne by the Eropean Regional Development Fn an the Repblic of Cyprs throgh the Research Promotion Fonation (Project ΝΕΑ ΥΠΟΔΟΜΗ/ΣΤΡΑΤΗ/38/6)» The appropriate performance of RES, sch as win an photovoltaic power systems, is base on the response of the power electronics Gri Sie Converter (GSC) [6]-[8], which is responsible for injecting the proce energy to the power gri. The control of the GSC is base on the estimation of the phase angle an amplite of the gri voltage at the Point of Common Copling (PCC) throgh a Phase-Locke Loop (PLL) algorithm [8], as shown in Fig.. The synchronization of RES ner balance gri voltages can easily be achieve by sing some conventional PLL algorithms [8]-[], esigne in the synchronos or stationary reference frames. The loop filter of this PLL is sally a Proportional-Integral (PI) controller in orer to attenate the high freqency harmonics an enable the accrate etection of the gri phase angle. In case of nbalance gri voltage, the synchronization of the RES is not a trivial aspect e to the copling effect between positive an negative voltage seqence. Several PLLs have been propose to enable accrate synchronization ner falty nbalance gri conitions [3]-[7], which are mainly base on the ecomposition of the symmetrical voltage seqences in combination with a conventional PLL algorithm. One main rawback of the above-mentione PLLs is the relatively high overshoot on the estimation of the phase angle an freqency of the gri. The high estimation overshoot can be minimize by sing a Proportional- Integral-Derivative (PID) controller, instea of a PI controller, in the loop filter block of the PLL. The erivative Power from Win Power System or Solar Power System VDC-link - DC GSC AC PWM molation LC Filter Vabc_ref θ - PLL, θ PLL v, v - Fig.. Strctre of an interconnecte renewable energy system. Iabc_meas RES Controller Vabc Aaptive αβpll with FCU PCC Lgri Power Gri Vgri (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

2 .9/TIA , IEEE Transactions on Instry Applications coefficient of the PID controller can rece the overshoot as prove in [8], bt on the other han the extra zero in the transfer fnction of the PID controller can affect the low pass filtering capability of the PLL. Therefore, to attenate inaccracies e to the effect of high freqency harmonics of the gri voltage, the se of PID controllers is sally avoie in PLL algorithms. Another important isse is that the time performance of the PLLs (ajste by the PLL tning parameters) is inversely proportional to the estimate freqency overshoot as shown in [4]. This means that for the esire fast operation of the PLL there is a anger of violating the freqency winow of the gri coes. Frthermore, the PLL presente in [4] (ecople voltages in stationary reference frame PLL αβpll) ensres an accrate estimation of the phase angle ner balance an nbalance gri falts an frthermore presents a faster performance within the same freqency limits compare to the PLL presente in [3]. The main prpose of this paper is to improve even more the performance of the αβpll ner gri falts by proposing the aaptive αβpll. The aaptive αβpll is base on the strctre of the αβpll, bt instea of sing constant control parameters for the PLL, it ses the propose tning parameter aaptation techniqe in orer to accelerate the performance of the PLL. The parameters are aapte base on a pre-calclate look-p table accoring to the type an voltage characteristic of the gri falt, which are estimate in real-time throgh a Classification Unit (FCU). The parameter aaptation will offer a significant acceleration on the response of the propose aaptive PLL withot violating the gri coes. Similar tning aaptation techniqes of the PLL have also been evelope in [9]-[] to enhance the performance of the synchronization. An elegant soltion has been propose in [9] an applie to single-phase PLLs an to the conventional three-phase qpll [9], where an intelligent aaptive mechanism has been introce to ajst the integral coefficient of the PI controller in orer to mitigate the freqency variation e to sen large phase istrbances. Another important moification of a PLL strctre is sggeste in [9], which allows recing the copling between the freqency an phase estimation loops. This ecopling between the freqency an phase, in combination with the aaptation of the integral coefficient, achieves a significant improvement on the synchronization performance. Base on the response of PLL transfer fnction in [9], the aaptation of integral coefficient is not possible to improve the time performance of the PLL. It can only affect the freqency overshoot e to the effect on the amping coefficient of the transfer fnction. Therefore, the improvements presente in [9] are case mainly from the freqency-phase ecopling an seconly from the aaptive mechanism. Frther, the aaptation techniqe of [9] oes not consier how the type an voltage rop of a gri falt can ifferently affect the PLL response. A simple freqency feeback term is se in [] to aapt the tning of the PLL. This can rece the ripple noise an accelerate the PLL performance, bt the nesire overshoot is also increase in this case. In [] the PI parameters of the PLL can be change between two ifferent possible vales in orer to enable a slow an a fast response. The slow-tne PLL can attenate the harmonic oscillations ner normal gri conition an the fast-tne PLL can achieve a ynamic transient response in case of gri falts. The PLL in [] ses a non-linear PI controller, where the tning parameters are ajste accoring to the phase estimation error to improve the transient PLL response. In general, the tning aaptation of the PLL can achieve significant performance improvement accoring to the aaptation prposes. The tning aaptation techniqe propose in this paper aims to obtain the faster possible synchronization time performance an at the same time to ensre that the freqency estimation will not violate the gri coe limits. The implementation of the propose tning aaptive mechanism for the PLL reqires an online estimation of the falt characteristic (in less than half cycle) throgh the propose FCU. The FCU is base on space vector analysis of the gri voltage symmetrical seqences, which has been se in [3]-[5] for off-line characterization of the falts. The novel iea of sing a real-time FCU is enable in this paper by obtaining the reqire information for the gri voltage seqences from an avance PLL, sch as the aaptive αβpll, instea of a Fast Forier Transformation (FFT), in orer to enable the faster an online estimation of the falt characteristics. The information abot the gri falt will be se for the aaptive tning of the propose PLL in sch a way to obtain the fastest possible synchronization withot any violation of the gri coe freqency limits. The implementation of the online FCU col also be very sefl in eciing the FRT control algorithm an also in the recovery procere after the falt is cleare. The performance acceleration of the aaptive αβpll e to the propose tning aaptation mechanism (accoring to the gri falt characteristics) is verifie throgh simlation an experimental reslts. The beneficial effects of the propose PLL on the FRT control of the GSC of an interconnecte RES are emonstrate in this paper, where it is shown that the aaptive PLL can lea to a faster an more appropriate control of the RES when falts occr. The Freqency an Phase Decopling (FPD) of the estimation loops propose in [9], in combination with the aaptation of the integral coefficient of the PLL emonstrate significant performance improvement as mentione alreay. Frthermore, the aaptation techniqe propose in this paper can enhance the time performance of the PLL. Since the performance improvements case by the propose in this paper tning aaptation mechanism an by the FPD of [9] are completely inepenent, it is obvios that the combination of the two techniqes can lea to even faster synchronization performance. Therefore, the FPD metho with the aaptation of the integral coefficient that is propose in [9], are applie to the strctre of αβpll by implementing the new FPD-αβPLL, which presents an (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

3 .9/TIA , IEEE Transactions on Instry Applications improve time response compare to the αβpll. Frthermore, the tning aaptation mechanism propose in this paper, is applie to ajst the tning parameters of FPDαβPLL accoring to the gri falt characteristics an therefore the new aaptive FPD-αβPLL is propose. The aaptive FPD-αβPLL presents the best performance compare to the other PLLs since it inherits the improvement case from the propose aaptive tning mechanism an the improvement of the ecopling between the freqency an the phase estimation loop. Section II escribes the implemente algorithm for the FCU, which enables the real-time estimation of the Type. Section III presents the propose aaptive PLL an the simlation an experimental reslts are shown in Sections IV an V respectively. Finally, the new FPD-αβPLL an the propose aaptive FPD-αβPLL are presente in Section VI. II. FAULT CLASSIFICATION UNIT The propose online FCU ses space vector analysis of the symmetrical seqences of the gri voltage [3]-[5] in orer to etee the type of falt an the characteristics of each low-voltage gri falt. The FCU shol be able to classify the falts into seven ifferent types (A-G) accoring to [6]. The fast online performance of the FCU is enable e to the novel se of the estimate phase angle an amplite of the positive an the negative seqence of the gri voltage (θ p, θ n, V an V - ) from the PLL, instea of sing FFT. The falt characteristics estimate by the FCU will be se by the aaptive tning mechanism to aapt the parameters of the PLL. A. Characteristics on Space Analysis The balance or nbalance gri voltage can be written as a smmation of a positive an a negative anglar freqency phasors (v an v - ), as given in (). The θ p, θ n, V an V - are estimate in real-time by the avance PLL that will be propose in Section III. where jωt jωt v v e v e v V e jθ p jθn an v V e The representation of the gri voltage in the complex plane base on space vector analysis [4] leas to an ellipse with major axis (r maj ), minor axis (r min ), inclination angle (φ incl ) an a Shape Inex (SI) as shown in (3), r v v, r v v maj min r φinc ( θp θn ), SI r min maj The above-mentione space vector analysis of the gri voltage is se to etee the characteristics of each falt accoring to [3]-[5], as also shown in Table I. These characteristics are reqire in orer to classify the type of gri falt. Type TABLE I. CHARACTERISTICS OF EACH TYPE OF FAULT Shape Inex (SI) Space Vector Analysis Inclination Angle (φ incl) Minor Axis (r min) Major Axis (r maj) Amplite of Zero Seqence A - (-)V n (-)V n B -.67 ±3 o, 9 o (-.67)V n V n.33. V n C - o, ±6 o (-)V n V n D - ±3 o, 9 o (-)V n V n E F G Type B rops () 3( ) 3 3( ) 3 3( ) 3 φincl=±3 o,9 o Phase ip (Type B,D or F) rmaj & Vo Type D rops () o, ±6 o (-)V n ±3 o, 9 o (-)V n (-.33)V n (-.33)V n.33. V n o, ±6 o (-)V n (-.33)V n V,V - an θp,θn From aaptive αβpll V,V - θp,θn Space Vector Analysis (SI,φinc,,rmaj) <.93 occrs SI SI<.93 Unbalance Type F rops () φincl Vabc Type C >.93 SI>.93 φincl= o,±6 o No Phases ip (Type C,E or G) rmaj & Vo Type E Fig.. The falt classification algorithm which etects the type an the characteristics of each low-votlage gri falt. B. Classification Algorithm The FCU algorithm takes as inpts the θ p, θ n, V an V - from the propose PLL an it is rnning the space vector analysis. The reslts from the space vector analysis in combination with the characteristic of each type of the falt (Table I) are se from the FCU to etee the type an voltage ip () of the falt as shown in Fig.. The FCU algorithm ses the r min to etee if there is a falt. When a falt occrs, the SI is examine in orer to clarify if the falt is balance (Type A) or nbalance (Type B-G). If the falt is nbalance, then the φ inc is se to separate between phases ip (C, E, or G) an phase ip (B, D, or F). Then, the characteristics r maj an the zero seqence voltage (V ) of each falt base on Table I are se in orer to classify the falt to the right falt type. Finally, when the falt type has been etecte, the information from r min is se to specify the rops () rops () Balance Type A Type G rops () rops () (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

4 .9/TIA , IEEE Transactions on Instry Applications θ, θ - v, v - Aaptive Tning q Vabc Classification Unit θ αβ Vαβ αβpll T αβ TABLE II. Type ip (%) Vαβ type Level of rop Vα Vα Vβ Vβ Vα Vβ cos(θgr) x T T q q voltage rop characteristic () of the falt. The propose falt classification algorithm, which enables the on-line classification of the gri falt is epicte in Fig.. III. - sin(θgr) x - sin θerror PI controller cos Parameter Estimation Unit (Τable II) (kp,ti)=f(falt type,voltage rop) DC q - q Decopling θ Cell THE ADAPTIVE PLL The propose aaptive αβpll is motivate throgh the fact that the overshoot on the estimate freqency is varie accoring to the tning of the PLL an the characteristics of the gri falts [4]. Therefore, this paper proposes to se an aaptive tning techniqe for the PLL (instea of niformly constant tning) in orer to achieve the faster esire time TI /(Ti. s) Kp kp q Δω ωnom LPF LPF /π /s z - z - z - z - q LPF DC q - Decopling q - LPF q Cell θ / x arctan θ - Fig. 3. The strctre of the propose aaptive αβpll. fest θ q q LOOK-UP TABLE FOR THE KP AND TI TUNING PARAMETERS OF THE ADAPTIVE DΑΒPLL (Initial Tnning Parameters K p=.35, T i=.3) A B C D E F G k p T i k p T i k p T i k p T i k p T i k p T i k p T i k p T i v v - 4 performance of the PLL for each falt, withot casing any violation on the freqency winow of the gri reglations. A. The strctre of the aaptive αβpll The aaptive αβpll inherits the strctre of the αβpll [4], bt instea of constant parameters in the PI controller, the PI parameters are change aaptively accoring to the falt characteristics as shown in Fig. 3. The strctre of the aaptive αβpll is base on a cross feeback network with two ecopling cells to ecompose the positive an negative voltage seqences. A elay of one sample (z - ) is reqire on the cross feeback network to avoi any algebraic loop on the igital implementation of the PLL. The ecomposition of the voltage seqences enable accrate estimation of each voltage seqence an a conventional PLL algorithm is then se to track the phase angle of the positive seqence of the gri voltage. The main iea of the aaptive αβpll is that the PI parameters of the phase angle tracking algorithm can be aaptively ajste accoring to the falt characteristics, obtaine by the FCU (Section II), in orer to achieve the fastest possible response of the PLL an conseqently a faster performance of the RES when a falt occrs. The tning of the low pass filters (LPF) an the etails abot the ecopling cells are escribe in [3] an [4]. The tning of the aaptive PI parameters is escribe in the next sb-section. B. The methoology for the tning aaptation In the case of low-voltage gri falts, the moern gri coes reqire that the RES shol remain interconnecte with the gri an provie spport to the power system ring the falt. The appropriate freqency operation winow of a RES accoring to German gri coes [4]-[5] is from -.5 Hz to.5 Hz aron 5 Hz. The violation of these limits will case the isconnection of the RES from the gri, which is nesire becase it can lea to cascaing failres of the gri. Therefore, the PLL algorithms that are se for the synchronization of the RES with the power gri shol be tne in a way always to operate within the freqency limits for any permitte low-voltage gri falts. On the other han, in [4] it has been prove that the time performance of the PLLs (ajste by the PLL parameters) is inversely proportional to the estimate freqency overshoot. Hence, for faster operation of a PLL there is a risk of violating the freqency winow of the gri coes. The investigation in [4] also shows that the estimate freqency overshoot of the PLL epens on the type an voltage characteristics of the falt. Accoring to the above-mentione conclsions, the knowlege of the type an voltage ip of the falt can be very sefl for the faster possible tning of the PLL withot any violation on the freqency winow. The aaptive αβpll proposes that the tning of the PLL shol be aaptively change accoring to the falt characteristics in orer to obtain the fastest possible synchronization performance ner any low-voltage gri falts. Therefore the (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

5 .9/TIA , IEEE Transactions on Instry Applications Magnite (B) Phase (eg) tning (PI parameters) of the propose PLL is aaptively change base on a pre-calclate look-p table accoring to the real-time estimation of the type an voltage ip of the falt throgh the implemente FCU, as shown in Table II. The tning of the PLL is base on the linearize small signal analysis of the PLL as presente in [], [4], [7]- [8]. When the PI controller transfer fnction is given by K p /(T i s) an the PLL is esigne for per nit voltage, the transfer fnction of the PLL can be obtaine by the seconorer transfer fnction of (4) kp s θ ζωn s ω n Ti θ s ζω n s ω s k n p s Ti where θ is the estimate phase angle by the PLL, θ is the Imaginary Axis (ra/s) (secons - ) Pole-Zero S-Plane Map Decrease of settling time Initial(slow)-tne-PLL Fast-tne-PLL Real Axis (ra/s) (secons - ) Fig. 4. Root locs of the propose aaptive PLL transfer fnction showing the zero an poles placement in the whole range of possible tning conitions. Boe Diagram of Aaptive PLL for ifferent tning Initial(slow)-tne-PLL Fast-tne-PLL Freqency (ra/s) Fig. 5. Boe iagram of the propose aaptive PLL for the two ege tning conitions gri phase angle, is the natral freqency an is the amping coefficient. The transfer fnction of (4) shows that the PLL presents low-pass filtering capabilities, which is very a sefl featre to attenate inaccracies ner high freqency harmonics in the gri voltage. The esire response of the secon-orer system in (4) can be efine by the settling time (ST), which is given by ST=4.6/(ζ. ω n ) an ζ shol be set to for an optimally ampe response. Therefore, the tning of the PLL can be achieve by ajsting the PI parameters shown in (5) in orer to efine the time response of the PLL. 9. k p an Ti.47 ST ζ ST The PI parameters shown in Table II have been precalclate accoring to (5) an offline teste throgh simlations for each falt in orer to obtain the fastest possible performance of the PLL withot violating the freqency limits for each specific falt. Therefore, when the FCU etects no falt conitions (normal operation) the PLL parameters are set as k p =.35 an T i =.3 so that the German gri coes can be satisfie for the worst case gri falts (same tning with the αβpll-initial parameters). In case that the FCU etects any low-voltage gri falt, which cases a lower voltage istrbance than the worst case falt, the PLL parameters are aapte from the initial parameters to the appropriate vale accoring to Table II in orer to accelerate the performance of the PLL an conseqently to obtain a better response of the RES. This col initially cost a higher freqency overshoot (bt always withot violating the freqency constraints). However, it can also lea to a faster an more accrate estimation of the phase angle an amplite of the gri voltage. The accrate an fast estimation of the gri voltage characteristics (θ, θ -, v an v - ) will fee the FRT control algorithm of the RES to generate faster the reference crrents an it will also assist the crrent control of the GSC to operate more accrately, when a falt occrs. The faster an more accrate synchronization of the RES ner gri falts is beneficial for the power system since the RES will provie a more appropriate spport to the power gri ner falty conitions. It is obvios that throgh the propose aaptive PLL algorithm, the PI parameters can be varie within a wie range of vales. Therefore, a frther analysis is reqire to verify the stability of the propose PLL in the whole range of possible tning conitions. Since ζ is always set to for an optimally ampe response, the root locs is a fnction of the ST. The root locs of the propose aaptive PLL transfer fnction is presente in Fig. 4 as a fnction of the ST, for all possible tning conitions (from the initial-slow-tne PLL to the fastest possible by the Table II fast-tne PLL). The stability of the propose PLL is prove in Fig. 4, since the two poles of the PLL are always place on the left half S- plane for any selecte tning parameters of Table II. The stability of the propose PLL is also prove by the boeiagram of Fig. 5, where the slowest an the fastest possible (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

6 .9/TIA , IEEE Transactions on Instry Applications Ti freq (Hz) Kp (%) Vabc (p) Type(A-G) freq. (Hz) Vpos (p) Vneg (p) freq. (Hz) Vabc (p) tning scenarios are shown. Since ζ is always a constant, the aaptive tning of the PLL is only affecting the natral freqency of the system an the stability of the propose PLL is ensre within the range of the possible tning conitions. The effect on the natral freqency of the PLL can case ifferent attenation of high orer harmonics, bt the PLL still presents significant filtering capabilities. IV. SIMULATION RESULTS A simlation moel has been implemente in MATLAB/SIMULINK to verify the accrate performance of the aaptive αβpll ner several gri falts. The appropriate operation of the propose PLL nees to be ensre, an afterwars the se of the propose aaptive αβpll in an interconnecte RES will be investigate. A. Performance of the aaptive αβpll The operation of the aaptive αβpll reqires to be emonstrate. Here, the response of the FCU an then the performance of the aaptive αβpll will be shown. For example, at time s a type B falt ( phase to gron) occrs with a voltage rop eqal to 3%. Fig. 6 shows that the FCU etects the type of the falt ( Type==B) an the voltage rop (=3%) within 4.8 ms (less than T/4). Then, Operation of Aaptive abpll for Type B falt (=3%) FCU response Parameters of aaptive abpll Freqency of Aaptive abpll Fig. 6. Simlation reslts showing the operation of the propose aaptive αβpll, incling the response of the FCU, ner falt type B with a voltage rop eqal to 3%. the parameters of the propose αβpll are aaptively moifie in orer to accelerate the performance of the propose PLL. The parameter k p an T i are change from the initial parameters.35 an.3 to 9.44 an.3 respectively, which are the esire parameters for the faster possible response ner the specific falt accoring to Table II. Therefore, the estimation of the gri freqency is accelerate as shown in Fig. 6. To prove the otstaning performance of the propose aaptive αβpll, it is necessary to compare the response with the αβpll. The comparison is taking place for the same falt (Type B, =3%). The simlation reslts of the comparison are illstrate in Fig. 7 where it is shown that the freqency estimation from the aaptive αβpll has a higher freqency overshoot bt withot violating the freqency limits. From Fig. 7 (c) the settling time of the aaptive αβpll (for the reqire accracy of.% of the maximm allowe istrbances) is 44.3 ms instea of 7 ms of the αβpll. Therefore, the aaptive αβpll is 6% faster than the αβpll on the estimation of the gri freqency in this case. The aaptive αβpll can also estimate faster an more accrately the amplite of the positive an negative seqence voltages as shown in Fig. 7 () (e). The accracy of the estimate voltages can affect the RES performance. Compare of Aaptive abpll w ith abpll (a) Gri (b) Freqency aaptive abpll abpll..3 (c) Zoom in Freqency () Positive seqence of voltage (e) Negative seqence of voltage Fig. 7. Simlation reslts comparing the performance of the aaptive αβpll to the αβpll, ner falt type B with voltage rop eqal to 3% (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

7 .9/TIA , IEEE Transactions on Instry Applications Power from Win Power System or Solar Power System VDC-link - DC AC Fig. 8. Control strctre of the GSC of a RES with FRT capability sing the new aaptive αβpll for the optimal synchronization. Power from Win Power System or Solar Power System VDC-link - DC GSC PWM molation Vabc_ref LC Filter Iabc_meas Enhance Crrent Controller Fig.. Time schele for the FRT control ring the falt. B. Using the new aaptive αβpll in an interconnecte RES ner FRT operation It is interesting to observe the effect of the propose aaptive αβpll on the control of the GSC of an interconnecte RES (Fig. 8), especially ner FRT operation. The appropriate operation of the RES ner gri falts reqires that the controller of the GSC is enhance with an FRT control algorithm, sch as the Flexible Positive an Negative Seqence Control (FPNSC) algorithm [8]- [3] an an avance crrent controller [3]-[34] with the capability of accrate injection of positive an/or negative seqence crrents. The FPNSC algorithm is responsible to limit the crrent injection accoring to the converter ratings an to generate the positive an negative seqence reference crrents that will fee the enhance Crrent Controller ring the falt so that the interconnecte RES provies the appropriate spport to the gri accoring to (6) an (7). P P ip k v ( k ) v v v Q P iq k v ( k ) v v v Power Gri The P an Q are the power set-points (accoring to the pre-falt proce power) an k an k are parameters that can be se easily to ajst between positive or negative Iref Iref - Vabc αβpll Kp & Ti The propose Aaptive αβpll θ, θ - v, v - θ, θ - v, v - FPNSC Algorithm PCC GSC Control enhance with FRT operation L5 θ, θ - v, v - Lgr Vgr Classification Unit (FCU) Type & voltage ip of falt AC T T GSC.69/kV /3kV 3MVA 3MVA MW RES Fig. 9. A MW RES interconnecte to a small power system. FRT is Start control cleare is applie Normal Operation Conventional Control ring FRT Control (FPNSC) ring L LB L P Q LA Normal Operation ( is cleare) L Time (sec) 3kV crrent injection accoring to the FRT control plan an the gri coes. Therefore, the control col aim to raise the falty positive seqence voltage (positive crrent injection) or to compensate the nbalance voltage conition (negative crrent injection), or both. The avance crrent controller [3]-[34] has to be able to provie accrate control ner nbalance falts to inject the appropriate positive or negative seqence crrents accoring to the FRT algorithm. The simlation reslts are base on a realistic scenario, where a MW GSC of a RES is interconnecte to a small power system as shown in Fig. 9. The falt occrs in the mile of line (Fig. 9) an the RES observes this falt as a voltage sag at the PCC. The time schele of the operation of the test be system is epicte in Fig., where the falt occrs at.5 s an the GSC operates base on the conventional control ntil.6 s. Then, the FRT operation is applie ntil the falt is cleare at.7 s. Simlation reslts are shown in Fig. for the case that a Type B falt ( phase to gron) is observe at the PCC with a voltage ip (=3%). The FRT control provies spport to the gri by operating accrately an injecting fll positive crrents (with ratio Q/P=3/ voltage/freqency spport), assming that the RES proce energy is constant ring the falt. Fig. emonstrates that the RES (with the new aaptive αβpll) col operate accrately ner nbalance falt conitions. The RES spports the gri by proviing voltage spport (the positive seqence of the gri voltage rises from.95 p to.99 p) an freqency spport (by injecting 3.6 MW ring the falt) (Fig. ). Another interesting point that reqires to be consiere is the effect of the faster an more accrate performance of the aaptive αβpll in the control of the GSC of RES. In Section IV.A it has been shown that the aaptive αβpll presents a faster an more accrate performance on the estimation of the phase angle an the amplite of the gri voltage. This fact col affect the accracy of the reference crrents that are generate from the FPNSC algorithm, which are a fnction of the positive an negative seqence of the voltage accoring to (6) an (7). Frthermore, the response of the crrent controller can be affecte since the accracy of calclating the seqence of the gri voltage an injecting crrent measrements are base on the accrate estimation of the phase angle from the aaptive αβpll. As shown in Fig., the crrent controller of the RES that ses the propose aaptive αβpll presents an otstaning performance compare to the RES that ses the αβpll since the injecte crrents are more accrate an a faster performance of the crrent control is achieve e to the better performance of the sggeste PLL. When the falt occrs, a faster an more accrate performance of I q is achieve by sing the aaptive αβpll. Frthermore, a more precise an faster performance for I an I q is achieve especially for FRT operation as illstrate in Fig.. This faster an more accrate performance is very critical when the gri falt occrs, since the RES can operate in an appropriate way to provie spport to the gri an avoi any cascaing failres (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

8 .9/TIA , IEEE Transactions on Instry Applications V(p) Iq(p) freq(hz) I(p) Vabc(p) Iabc(p) P&Q(p) Seqence s.5 FRT performance of an interconnecte RES Active an Reactive Pow er P Q V V Injecte crrents Fig.. Simlation reslts for the FRT performance of the RES sing the new aaptive αβpll, ner falt type B with the voltage rop eqal to 3%. occrs FRT operation I ref(abpll) I meas(abpll) I ref(a.abpll) I meas(a.abpll) is cleare 5.5 Fig.. Simlation reslts comparing the crrent control performance of the GSC of a RES ner FRT operation, when sing the new aaptive αβpll an when sing the αβpll, ner falt type B with a voltage ip eqal to 3% f (A.abPLL) f (abpll) V. EXPERIMENTAL RESULTS The performance of the aaptive αβpll also reqires experimental valiation; therefore, an experimental setp is implemente sing a Chroma 674 programmable AC sorce, a Delta Elektronika SM6- DC sorce power spply an a Danfoss FC3 (. kw) inverter as the GSC, as shown in Fig. 3. A three-phase loa resistance has been connecte in parallel to the AC sorce in orer to prevent the absorption of active power from the AC sorce, since the AC sorce can only eliver active power. Therefore, the power generate by the GSC can be consme from the parallel loa an the proper operation of the AC sorce is ensre. The propose PLL an the control of RES have been igitally evelope sing the Matlab/Simlink Real Time Workshop an the SPACE DS 3 DSP boar with a sampling freqency of 5 khz. A. Performance of the aaptive αβpll The response of the propose PLL is experimentally valiate in this section. The GSC is operating ner normal operating conitions an at.788 s a Type D (propagation of a two phase falt with no gron throgh a yd transformer) falt occrs with a voltage rop at the PCC eqal to 4.7% as shown in Fig. 4. The FCU etects the gri an classifies the falt within 4. ms (less than T/4). Then the information abot the type an the voltage ip of the gri falt is se by the aaptive PLL in orer to ajst immeiately the tning of the PLL (the K p an T i are change from the initial vales to 5.46 an.75 respectively). Therefore, the time performance of the propose PLL is accelerate an conseqently the accrate estimation of the phase angle, freqency an seqences of the gri voltage is achieve faster. The performance acceleration of the aaptive PLL cases a higher freqency estimation overshoot, bt it is always within the limits of the German gri reglations. B. Using the new aaptive αβpll in an interconnecte RES ner FRT operation The performance of the RES when sing the propose PLL an the effect of the otstaning performance of the PLL are experimentally emonstrate in this section. The control strctre of the GSC in the experimental setp is implemente as shown in Fig. 8, in the same way with the simlation moel. The accrate an fast synchronization of the RES with the power gri is obtaine throgh the aaptive αβpll. The FPNSC FRT control algorithm [8]-[3] is se for generating the reference crrents accoring to (6) an (7) when a low-voltage falt occrs an an enhance VDC-link V DC GSC DELTA ELEKTRONIKA POWER SUPPLY SM 6- (DC Sorce) 6 AC 3.6mH 4.7μF LC Filter A 3 3 SPACE DS3 DSP boar V 5kVA 4V:4V Isolation Transformer PCC y D LOAD Fig. 3. Schematic of the experimental setp. Vgri Chroma 674 Programmable AC SOURCE SPACE Control Desk & Matlab/ Simlink RTW (aaptive αβpll an RES control) (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

9 .9/TIA , IEEE Transactions on Instry Applications Vabc(p) Iabc(A) Type Vabc(p) Kp Type (p) P&Q(kVA) freq (Hz) freq (Hz) (p) V &V - (p) phase(ra) crrent controller [3]-[34] is se for the accrate crrent injection ring nbalance falts. The performance of the interconnecte RES with the propose PLL ner FRT operation is emonstrate in Fig. 5. A rate. kw interconnecte GSC is operating ner normal operating conitions an it is injecting kw (4.8 A peak) an kvar to the power gri. At.86 s a Type C (two phase with no gron) falt occrs with 3% voltage ip at PCC. The FCU etects the falt type an voltage ip of the falt within 4.4 ms an the tning parameters of the propose PLL are immeiately aapte to accelerate the accrate synchronization withot violating the freqency limits of the gri coe. The control of the RES is etecting the occrrence of the gri falt an therefore the FRT control is immeiately applie to enable the accrate operation of the RES an the appropriate spport of the falty power system [8]-[3]. The FRT control strategy for low-voltage falt conitions is base on proviing voltage an freqency spport with a ratio Q:P=3 to the gri accoring to the gri coes []-[5]. The FRT control in this case sty ses the assmption that the proce apparent power from the RES is constant ring the falt an eqal to the pre-falt proce power ( kw an kvar) as shown in Fig. 5. Conseqently, when the falt occrs at.86 s the FRT control is activate an ajsts the injecte positive seqence of the power to.63 kw an.89 kvar respectively in orer to provie spport to the power system (Fig. 5). The injecte active power (.63 kw) is acting as freqency spport to the gri (since the RES is injecting an amont of active power instea of isconnecting the RES from the gri) an the injecte reactive power (.89 kvar) is acting as voltage spport an it is trying to increase the positive seqence of the voltage of the gri. The injecte crrent by the enhance crrent controller is prely sinsoial, espite the nbalance voltage conitions an the FRT control accomplishes to keep the injecte crrent within the converter limits (4.5 A peak). The otstaning performance of the aaptive αβpll is beneficially affecting the operation of the RES. The effect of sing the propose PLL can be observe in the accracy of the crrent controller an on the accracy of the generate reference crrents from the FRT. The effect of the propose PLL is emonstrate throgh the accracy of the reference crrents in Fig. 6. In case where the RES ses the aaptive αβpll for the synchronization the reference crrent are settling own ms after a Type C (=%) falt occrs at.78 s. On the other han, where the RES se the αβpll for the synchronization the reference crrents reqires 5 ms to settle own. The faster an more accrate performance achieve by the RES, when the propose PLL is se, is beneficial for the FRT operation of the RES an conseqently for the power system since all the RES will spport the gri in a more appropriate way. Kp aap.abpll Ti aap.abpll Fig. 4. Experimental reslts showing the operation of the propose aaptive αβpll, incling the response of the FCU, ner falt type D with a voltage rop eqal to 4.7% Fig. 5. Experimental reslts showing the FRT performance of the GSC of the RES when se the propose PLL ner a type C gri falt with a voltage rop eqal to 3% P Q (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

10 .9/TIA , IEEE Transactions on Instry Applications Vabc(p) I ref (A) FT & Kp Iq ref (A) FT (p) I q ref(a.abpll) I q ref(abpll) the PLL accoring to the response of the secon orer transfer fnction [7]. On the other han, the aaptive tning mechanism accoring to the type an voltage rop of the gri falt sggeste in Section III can irectly affect the settling time of the PLL an lea to a faster synchronization response withot violating the freqency limits. Therefore, the improvements on the synchronization performance in the case of aaptive PLL presente in Section III an the aaptive PLL presente in [9] are case by completely ifferent reasons. Ths, the combination of the two techniqes can lea to a new otstaning synchronization metho that will present an even faster time performance. A. The FPD-αβPLL For this prpose, the ecopling between phase an freqency estimation loop has to be applie on the strctre of αβpll accoring to the theory of [9]. The freqency estimation in case of the conventional αβpll is given by (8), bt in the case of the new Freqency-Phase Decopling αβpll (FPD-abPLL) the freqency estimation is given by (9) withot consier the term Κ p. θ error Fig. 6. Experimental reslts comparing the generate reference crrent from the FRT control when the synchronization is obtaine from the aaptive αβpll an from the conventional αβpll, ner falt type C with a voltage rop eqal to %. VI. A CHALLENGING PLL EXPANSION So far, the propose aaptive mechanism for ajsting the tning parameters of the αβpll, which has been presente in Section II Section V, has prove that it can enhance the time performance of synchronization accoring to the type an the voltage rop of the gri falt. Another very interesting moification of the PLL algorithm has been recently presente in [9], which can also lea to significant acceleration of the time performance of the PLL. The metho in [9] sggests the ecopling between the freqency an phase estimation loop in orer to avoi nesire freqency swings e to phase or voltage variations. In [9], the Freqency-Phase Decopling (FPD) techniqe is combine with an aaptation techniqe for ajsting the T i parameter of the PI controller in orer to rece the sen freqency variations. The reslts presente in [9] show a significant rection of the freqency overshoot ner phase falts, which can also be translate to acceleration of the time performance, since the tning of the PLL can be set for faster operation withot violating the freqency limits of the gri coes. The beneficial effect on the settling time an freqency overshoot of [9] is mostly case by the FPD techniqe an less by the aaptive tning of T i. The ajstment of T i can only lea to over-ampe operation (small rection of the freqency overshoot), bt it can not actally effect the settling time of fest ( αβpll) θ error K p ωnom π Ts i f est ( FPDαβPLL ) θerror ω nom π Ts i The ecopling between the freqency an the phase in the new FPD-αβPLL is achieve by not consiering the term Κ. p θ error on the freqency estimation loop, an only consiering it on the phase estimation loop as shown in Fig. 7. The implementation of the FPD-αβPLL accoring to [9] also reqires an aaptive mechanism for ajsting the T i parameter accoring to the phase error (θ error ) an the amplite of the positive seqence of the voltage. The aaptive mechanism is achieve by mltiplying the parameter T i with the term escribe in () θ error λ q where the vale of λ can be set in the range 5 λ. The vale of λ in this paper has been set to accoring to [9]. The aaptive mechanism of () is actally ajsting the amping coefficient of the PLL algorithm (by ajsting the T i parameter) in orer to mitigate istrbances in the freqency e to the occrrence of a large phase error. The strctre of the new FPD-αβPLL, which is actally the moification propose by [9] applie to the strctre of αβpll, is presente in Fig. 7 (in this case parameters K p an T i shol consiere as constant). The tning parameter of FPD-αβPLL are set to K p =6.33 an T i =.53, which are the parameters achieving the faster possible performance withot violating the German gri coe for the worst case low-voltage falt. B. The Aaptive FPD-αβPLL Now to achieve an even faster synchronization time performance, it is necessary to combine the aaptive tning mechanism of Section III with the new FPD-αβPLL (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

11 .9/TIA , IEEE Transactions on Instry Applications θ, θ - v, v - q Vabc Classification Unit Aaptive Tning θ αβ αβpll Vαβ T αβ Vαβ V cos(θgr) α x Vα Vβ Vβ Vα Vβ type Level of rop T T - sin(θgr) x q q - sin θerror Aaptive Eqation () cos Parameter Estimation Unit (Τable III) (kp,ti)=f(falt type,voltage rop) DC q - q Decopling θ Cell Fig. 7. The strctre of the new aaptive FPD-αβPLL. (presente in Section VI.A), which is base on the theory of [9]. The propose otstaning synchronization metho, name aaptive FPD-αβPLL is presente in Fig. 7. The propose aaptive FPD-αβPLL inherits the strctre of the new FPD-αβPLL an combines it with the aaptive mechanism of Section III to ajst the tning parameters of the PLL accoring to the type an the voltage rop of the gri falt. Therefore, the aaptive tning mechanism reqires the FCU, as presente in Fig., to etee the falt type an voltage ip an then the parameter estimation nit to ajst the tning parameters. The parameter estimation nit is base on a pre-calclate look-p table (Table III) which contains the faster possible tning parameters (withot violating the freqency operation winow) of the FPDαβPLL for any possible type of low-voltage gri falt with a -% voltage rop. The initial parameters of the aaptive FPD-αβPLL are set to the slower tning parameters of Table III (worst case falt), which are the same with those of FPD-αβPLL, in orer to avoi any violation on the freqency operation winow of German gri coes. If any other gri falt occrs, the FCU will etect the characteristics of the falt an the performance of the aaptive FPD-αβPLL will accelerate, bt always withot exceeing the gri coe limits. The strctre of the propose aaptive FPD-αβPLL is presente in Fig. 7 with all the reqire moles. The improvements case from the FPD PLL algorithm an case from the aaptive tning accoring to the gri falt are completely inepenent, an therefore, the performance of the aaptive FPD-αβPLL is expecte to overcome the performance of FPD-αβPLL an the aaptive αβpll. C. Performance Comparison A fair performance comparison of the for synchronization methos presente in this paper is reqire q TI /(Ti. s) Kp LPF LPF z - z - q LPF DC q - Decopling q - LPF q Cell θ / x arctan kp ωnom /π z - z - fest /s FPD-PLL q θ - q θ v v - 4 Type ip (%) TABLE III. LOOK-UP TABLE FOR THE KP AND TI TUNING PARAMETERS OF THE ADAPTIVE FPD-αβPLL (Initial Tning Parameters K p=6.33, T i=.53) A B C D E F G k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) k p T i ( x -6 ) at this point. Therefore, in this section the performance of the αβpll, the aaptive αβpll, the FPD-αβPLL an the aaptive FPD-αβPLL will be investigate. The performance of the for PLL algorithms is presente in Fig. 8 when a Type E nbalance gri falt occrs at s with 33% of voltage rop. The comparison focses on the phase error settling time (the reqire time for the phase error to remain within % of the maximm istrbance) an the freqency error settling time (the reqire time for the freqency error to remain within mhz of the gri freqency) which are presente in Table IV. The aaptive αβpll an the FPD-αβPLL present similar time performance an are faster than the αβpll (as expecte), as shown in Table IV. In the case of the aaptive αβpll, the improvements are case by the exploitation of the ifferent falt characteristics in the aaptation mechanism in orer to accelerate the PLL response. In the case of the FPD-αβPLL, the improvements are base on the ecopling between the freqency an the phase estimation loops an the aaptive mechanism of the integral coefficient ner large phase variations. The propose aaptive FPD-αβPLL presents an otstaning time performance, which is approximately three times faster than the aaptive αβpll an the FPD-αβPLL an approximately for times faster than the αβpll. The otstaning performance of the propose aaptive FPDαβPLL was expecte since the propose PLL inherits the improvements of the aaptive αβpll an the improvements of the FPD-αβPLL, which are completely inepenently. Eventally, the propose aaptive FPDαβPLL presents the best time performance of the for ner investigation PLLs ner low-voltage gri falt an therefore can affects beneficially the FRT performance of the GSC of an interconnecte RES (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See

12 .9/TIA , IEEE Transactions on Instry Applications f zoom-in (Hz) V abc (p) f(hz) Fig. 8. Simlation reslts comparing the performance of all the implemente PLL algorithms for a Type E nbalance falt with 33% of voltage rop. TABLE IV. SYNCHRONIZATION PERFORMANCE OF PLL ALGORITHMS UNDER AN UNBALANCED GRID FAULT (TYPE E AND =33%) Synchronization Metho (a) Gri (b) Phase Error(Zoom In) (c) Freqency Estimation error (eg o ) () Freqency Estimation(Zoom In) PLL FPD-PLL a. PLL Phase Error Settling Time (ms) VII. CONCLUSIONS a. FPD-impr-PLL Freqency Error Settling Time (ms) αβpll 69 Aapt. αβpll 5 7 FPD-αβPLL 6 4 Aapt. FPD-αβPLL This paper proposes a new aaptive αβpll, which achieves a faster response an an accrate estimation of the phase angle an amplite of the gri voltage ner lowvoltage gri falts. The propose PLL improves the synchronization of the RES by sing the propose tning aaptation mechanism accoring to the online estimation of the gri falt characteristics. The faster performance of the aaptive PLL affects beneficially the performance of the GSC of an interconnecte RES, especially ner FRT operation. Frthermore, a new synchronization metho, name FPD-αβPLL, is presente in this paper, where a metho that ecoples the freqency an phase estimation loop is applie to the strctre of the αβpll in orer to improve the performance of the PLL. Finally, the freqencyphase ecopling metho is combine with the propose tning aaptation techniqe an therefore the aaptive FPDαβPLL is propose. The new aaptive FPD-αβPLL presents an otstaning performance, which overcomes the other ner investigation synchronization methos in terms of time response. The acceleration of the synchronization by the propose PLL can improve the FRT performance of the RES, which is very critical in orer to provie the appropriate spport to the power gri when falts occr. REFERENCES [] IEEE Stanar for Interconnecting Distribte Resorces With Electric Power Systems, IEEE St 547-3, 3, pp. 7. [] Eltra an Elkraft, Win trbines connecte to gris with voltage below kv, 4. [3] I. Erlich,W. Winter, an A. Dittrich, Avance gri reqirements for the integration of win trbines into the German transmission system, in Proc. of IEEE-PES General Meeting, pp , Montreal, Canaa, Jne 6. [4] M. Tsili an S. Papathanassio, A review of gri coe technical reqirements for win farms, IET Renewable Power Generation, vol. 3, pp , 9. [5] M. Altın, O. Gooks, R. Teooresc, P. Rorigez, B. B. Jensen an L. Helle, Overview of recent gri coes for win power integration, in Proc. of th OPTIM Intern. Conference, pp.5 6, Brasov, Romania, May. [6] F. Blaabjerg, Z. Chen an S. Kjaer "Power electronics as efficient interface in isperse power generation systems", IEEE Trans. Power Electron., vol. 9, no. 5, pp Sep. 4 [7] Z. Chen, J. M. Gerrero an F. Blaabjerg, "A review of the state of the art of power electronics for win trbines", IEEE Trans. Power Electronics, vol. 4, no. 8, pp , Ag. 9. [8] F. Blaabjerg, R. Teooresc, M. Liserre, an A. V. Timbs, Overview of control an gri synchronization for istribte power generation systems, IEEE Trans. Instrial Electronics, vol. 53, no. 5, pp , Oct. 6. [9] V. Kara an V. Blasko, Operation of a phase locke loop system ner istorte tility conitions, IEEE Trans. Instry Applications, vol. 33, no., pp , Jan [] G.-C. Hsich an J. Hng, Phase-locke loop techniqes A srvey, IEEE Trans. Instrial Electronics, vol. 43, pp , Dec [] R. Teooresc an F. Blaabjerg, Flexible control of small win trbines with gri failre etection operating in stan-alone an griconnecte moe, IEEE Trans. Power Electronics, vol. 9, no. 5, pp , Sep. 4 [] N. Hoffmann, R. Lohe, M. Fchs, L. Aiminoaei, an P. Thogersen, A review on fnamental gri-voltage etection methos ner highly istorte conitions in istribte power-generation networks, in Proc. of IEEE ECCE, Phoenix, Arizona, pp , Sep.. [3] P. Rorigez, J. Po, J. Bergas, J. I. Canela, R. P. Brgos, an D. Boroyevich, Decople oble synchronos reference frame PLL for power converters control, IEEE Trans. Power Electronics, vol., no., pp , Mar. 7. [4] L. Hajiemetrio, E. Kyriakies, an F. Blaabjerg, A new hybri PLL for interconnecting renewable energy systems to the gri, IEEE Trans. Instry Applications, vol. 46, no. 6, pp , Nov. 3. [5] F. Xiong, W. Ye, L. Ming, W. Ke, an L. Wanjn, A novel PLL for gri synchronization of power electronic converters in nbalance (c) 3 IEEE. Personal se is permitte, bt repblication/reistribtion reqires IEEE permission. See