Digital Transceiver V605

Size: px

Start display at page:

Download "Digital Transceiver V605"

Phyllis Newton
5 years ago
Views:

Embedded PC-based Instrument with up-to 4 Independent DDCs, 4 DUCs and Dual Spectrum Analyzers System Features Intel i7 Quad Core, 8 GB RAM, 240 GB SSD, Win 7 Pro 64-bit Sustained logging rate up-to

1 Embedded PC-based Instrument with up-to 4 Independent DDCs, 4 DUCs and Dual Spectrum Analyzers System Features Intel i7 Quad Core, 8 GB RAM, 240 GB SSD, Win 7 Pro 64-bit Sustained logging rate up-to 1600 MByte/s v1.2 Per-Module Features Two 14-bit, 400 MHz ADCs; analog bandwidth: MHz (AC Coupled) Two 16-bit, 500 MHz DACs; analog bandwidth: MHz (AC Coupled) Xilinx Virtex-6 SX475T-2 FPGA Embedded power meter 32 digital-io bits Digital Down-Converter (DDC) Two independent 16-bit DDC channels Programmable tuner: DC MHz; resolution Hz Programmable bandwidth: 2 KHz - 43 MHz DDC outputs SNR > 60 db; SFDR > 80 db Spectrum inversion for ADC under-sampling Support synchronous down-sampling on multiple channels and modules using external clock/trigger Synchronous VITA 49 timestamp Digital Up-Converter (DUC) Two independent 16-bit DUC channels Programmable tuner: DC MHz; resolution Hz Programmable bandwidth: 2 KHz 43 MHz Spectrum inversion Spectrum Analyzer Single wide-band/narrow-band 32K points FFT Eight Windowing available Programmable FFT update rate Programmable maximum hold mode Threshold limited spectrum monitoring up-to 512 bins Applications Digital Receiver Surveillance Arbitrary Waveform Generator/Player Description The V605 digital transceiver supports one or two plug-in modules, each featuring two independent channels of DDC, DUC, and one spectrum analyzer embedded in the Xilinx Virtex-6 FPGA. It allows users to monitor the wide-band or narrow band spectrum and record the data directly from the ADCs or down-convert the channels modulated on the IF band. The embedded PC can do contiguous recording at 1600 MByte until running out of disk space. The transmitter can play the recorded baseband waveform of different bandwidth, up-convert and modulate it on the IF band on the DACs. Each DDC/DUC has its own programmable tuner, programmable low-pass filtering, gain control, and decimation/interpolation setting, supporting two independent channel bandwidths up-to 43 MHz. The DDC data is packetized in VITA 49 format with the accurate timestamps, synchronous to the external PPS signal. The DDC channel can be enabled and disabled on the fly to save the storage and bandwidth to the host computer. The embedded power meter monitors the power (dbfs) of the ADC inputs, allowing users to perform possibly analog gain control in the external front-end device, not included in the system. The spectrum analyzer, including windowing, calculates the wideband spectrum of the ADC data or the narrow-band spectrum of the DDC output data at the programmable update rate. The maximum hold helps to retain the information in the spectrum and the programmable threshold monitoring spectrum detects the spectral activities up-to 512 bins. A development kit is available for the custom design. Users can insert custom-made cores to create even more advanced applications. 09/18/14 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarily include testing of all parameters. Innovative Integration phone fax of 10

2 System Characteristics System Parameters (See epc datasheet for full embedded PC details) Number of XMC Modules Support 1 or 2 SBC Type Sustained Logging Rate Intel i7 Quad Core, 8 GB RAM, 240 GB SSD, USB2.0 x4, 1 Gb Ethernet x1 400 MByte/s; 1600 MByte/s with additional SSD drives Module Parameters (See X6-400M datasheet for full module details) A/D Converter D/A Converter FPGA Type VITA 49 Timestamp Digital-IO Digital Down-Converter Channel Number 2 Channel Tuning Channel Bandwidth Two 14-bit, sampling rate up-to 400 MHz; analog bandwidth MHz (AC Coupled) Two 16-bit, sampling rate up-to 500 MHz; analog bandwidth MHz (AC Coupled) Xilinx Virtex-6 SX475T-2 Yes 32-bit Programmable from DC to Fs/2; default to 70 MHz Programmable from 2 KHz - 43 MHz; default to 10 MHz Decimation Rate Independent decimation rate of 8*N, where N is from 1 to 8192; default to 32. Spectrum Inversion SNR SFDR Digital Up-Converter Channel Number 2 Channel Tuning Channel Bandwidth Yes > 60 db > 80 db Programmable from DC to Fs/2; default to 70 MHz Programmable from 2 KHz - 43 MHz; default to 10 MHz Interpolation Rate Independent interpolation rate of 8*N, where N is from 1 to 8192; default to 32. Spectrum Inversion Spectrum Analyzer Number of Core 1 Windowing Update Rate Maximum Hold Spectrum Mode Yes Rectangular, Hann, Chebyshev, Taylor, Blackman-Harris, Hamming, Gaussian, and Flat top. Programmable Programmable Full spectrum (FS): points FFT in natural order; Threshold limited spectrum (TLS): Programmable threshold monitoring up-to 512 bins Innovative Integration phone fax of 10

3 System Block Diagram SSD 240 GB VGA x1 USB2.0 x4 Ethernet x1 COM Express Module - i7 Quad, 8GB RAM 4x PCIE 8x PCIE XMC0 XMC1 X6-400M DIO Mezanine Module Block Diagram Figure 1. Digital transceiver block diagram Power Meter ADC Intf mux IP-DDC- 500msps 1 of 2 chs Post- Processing mux Vita Framer Vita Router DDR Intf DIG-TRX FPGA Velo Packetizer mux IP- FFT32K Post- Processing Vita Framer alert PCIe Intf DAC Intf sum sum IP-DUC- 500msps IP-DUC- 500msps Pre- Processing Pre- Processing DDR Intf DDR Intf Vita Deframer Vita Deframer SID Router Velo Deframer Figure 2. X6-400M block diagram Innovative Integration phone fax of 10

4 Magnitude (db) Magnitude (db) Programmable DDC Filter Characteristics Fs=400 MHz, DDC Bandwidth=10 MHz DDC-500MSPS Frequency Response Frequency (MHz) Figure 3. Bandwidth 10 MHz DDC frequency response Fs=400 MHz, DDC Bandwidth=43 MHz DDC-500MSPS Frequency Response Frequency (MHz) Figure 4. Bandwidth 43 MHz DDC frequency response Innovative Integration phone fax of 10

5 Example Bandpass Filter Figure 5. Test environment; anti-aliasing filter is used between the digital receiver and functional generator Amplitude Input signal Fs/2 Tuning freq=70 =200 Fs=400 Freq(MHz) Figure 6. Bandwidth 10 MHz input signal modulated at 70 MHz; blue line is the shape of anti-aliasing filter; Fs is the ADC sampling frequency. Amplitude Spectrum-inverted image Figure 7. rate Fddc Fddc/2 =12.5 Freq(MHz) =6.25 Down-converted signal to the baseband; red line is the shape of DDC filter; Fddc is the DDC output Innovative Integration phone fax of 10

6 Fs=400 MHz, Fin=71 MHz, Ftune=70 MHz, DDC Bandwidth=10 MHz; source: Agilent N5181A, Ampl: 10 dbm Figure 8. DDC output complex spectrum in BinView; SNR: 63.8 db, SFDR: 84.9 db, ENOB: 10.3 bits. Fs=400 MHz, Fin=71 MHz, Ftune=70 MHz, DDC Bandwidth=43 MHz; source: embedded test generator Figure 9. DDC output complex spectrum in BinView; SNR: 74.9 db, SFDR: 97.9 db, ENOB: 12.1 bits. Innovative Integration phone fax of 10

7 Figure 10. DDC output FFT plot of down-converted to baseband FM signal (deviation 5 MHz) Innovative Integration phone fax of 10

8 Software GP-400M Figure 11. Qt-version of application software. MSVC (Windows) version also available. Innovative Integration phone fax of 10

9 Ordering Information Digital Transceiver Instrument Product Part Number Description V605 Digital Transceiver Instrument L0 Basic Instrument with single X6-400M module, SW/FW PKG, epc, 240GB SSD, Win7 Pro 64-Bit Second X6-400M Module X6-400M with SX475T2 FPGA, PCIe 8-lane gen2, AC-coupled, providing two additional transceiver channels for DDCs, DUCs and FFT Development Kit Product Part Number Description X6-400M Framework Logic DDC, DUC and Spectrum Analysis X6-400M Framework Logic board support package for RTL and Matlab Framework logic 2 channels of IP-DDC-500msps, 2 channels of IP-DUC and 1 channel of IP-FFT32K for Virtex-6 SX475T2 Accessories and Hardware Product Part Number Description Cables SMA to BNC Cable IO cable with SMA (male) to BNC (female), 1 meter Storage SSD Solid State Drive, SAMSUNG 840 Pro Series MZ-7PD512BW 2.5" 512GB SATA III MLC Internal. Up to three additional drives supported. Innovative Integration phone fax of 10

10 IMPORTANT NOTICES Innovative Integration Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to Innovative Integration s terms and conditions of sale supplied at the time of order acknowledgment. Innovative Integration warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Innovative Integration s standard warranty. Testing and other quality control techniques are used to the extent Innovative Integration deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. Innovative Integration assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Innovative Integration products. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. Innovative Integration does not warrant or represent that any license, either express or implied, is granted under any Innovative Integration patent right, copyright, mask work right, or other Innovative Integration intellectual property right relating to any combination, machine, or process in which Innovative Integration products or services are used. Information published by Innovative Integration regarding third-party products or services does not constitute a license from Innovative Integration to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from Innovative Integration under the patents or other intellectual property of Innovative Integration. Reproduction of information in Innovative Integration data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. Innovative Integration is not responsible or liable for such altered documentation. Resale of Innovative Integration products or services with statements different from or beyond the parameters stated by Innovative Integration for that product or service voids all express and any implied warranties for the associated Innovative Integration product or service and is an unfair and deceptive business practice. Innovative Integration is not responsible or liable for any such statements. For further information on Innovative Integration products and support see our web site: Mailing Address: Innovative Integration, Inc. 2390A Ward Avenue, Simi Valley, California Copyright 2007, Innovative Integration, Incorporated Innovative Integration phone fax of 10

IP-DDC Channel Digital Downconversion Core for FPGA FEATURES DESCRIPTION APPLICATIONS IMPLEMENTATION SUPPORT HARDWARE SUPPORT

IP-DDC Channel Digital Downconversion Core for FPGA FEATURES DESCRIPTION APPLICATIONS IMPLEMENTATION SUPPORT HARDWARE SUPPORT 128 Channel Digital Downconversion Core for FPGA v1.0 FEATURES 128 individually tuned DDC channels 16 bit 200MHz input Tuning resolution Fs/2^32 SFDR 96 db for 16 bits input Decimation range from 512 to