REVISIONS LTR DESCRIPTION DATE APPROVED. Update boilerplate to current MIL-PRF requirements. - PHN Thomas M. Hess

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED Update boilerplate to current MIL-PRF requirements. - PHN Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES PMIC N/ Original date of drawing YY MM DD REV PGE PREPRED BY Phu H. Nguyen CHECKED BY Phu H. Nguyen PPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITL-LINER, 10 MHz TO 66 MHz, 10:1 LVDS SERILIZER/DESERILIZER, MONOLITHIC SILICON CODE IDENT. NO. REV PGE 1 OF 20 MSC N/ V115-14

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance10 MHz to 66 MHz, 10:1 LVDS serializer/deserializer microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 SN65LV1023-EP 10 MHz to 66 MHz, 10:1 LVDS serializer 02 SN65LV1224B-EP 10 MHz to 66 MHz, 10:1 LVDS deserializer Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 28 MO-187 Plastic small outline Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other REV PGE 2

3 1.3 bsolute maximum ratings. 1/ Supply voltage range ( V CC to GND) V to 4.0 V LVTTL input voltage V to V CC V LVTTL output voltage V to V CC V LVDS receiver input voltage V to 3.9 V LVDS driver output voltage V to 3.9 V LVDS output short circuit duration ms Electrostatic discharge: HBM... up to 6 kv MM... up to 200 V Junction temperature C Storage temperature C to 150 C 2/ Lead temperature (soldering, 4 seconds) C Maximum package power dissipation (T = 25 C) W Package derating mw/ C above 25 C 1.4 Recommended operating conditions. Supply voltage range ( V CC ) V to 3.6 V 3/ Receiver input voltage range... 0 V to 2.4 V V Receiver input common mode range... ID V to ID V 2 2 Maximum supply noise voltage mvp-p Operating free air temperature C to +125 C 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 1/ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Long term high temperature storage and/or extended use at maximum operating conditions may result in a reduction of overall device life. 3/ By design, DV CC and V CC are separated internally and does not matter what the difference is for DV CC-V CC, as long as both are within 3 V to 3.6 V. REV PGE 3

4 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Deserializer table. The deserializer truthn table shall be as shown in figure Block diagrams. The block diagrams shall be as shown in figure Timing diagrams and test circuits. The timing diagrams and test circuits shall be as shown in figures REV PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Symbol Conditions -55 C T 125 C Limits Unit Device type: ll Unless otherwise specified Min Max Serializer LVCMOS/LVTTL DC specifications 2/ High level input voltage V IH 2 V CC V Low level input voltage V IL GND 0.8 Input clamp voltage V CL I CL = -18 m -1.5 Input current 3/ I IN V IN = 0 V to 3.6 V μ Deserializer LVCMOS/LVTTL DC specifications High level input voltage V IH 2 V CC V Low level input voltage V IL GND 0.8 Input clamp voltage V CL I CL = -18 m -1.5 Input current (pull-up and pull-down I IN V IN = 0 V to 3.6 V μ resistors on inputs) High level output voltage V OH I OH = -5 m 2.2 V CC V Low level output voltage V OL I OL = 5 m GND 0.5 Output short circuit current I OS V OUT = 0 V -85 m High impedance output current I OZ PWRDN or REN = 0.8 V, V OUT = 0 V or V CC μ Serializer LVDS DC specifications (pply to pins DO+ and DO ) Output differential voltage (DO+)-(DO-) V OD R L = 27 Ω, See figure mv Output differential voltage unbalance ΔV OD 35 Offset voltage V OS V Offset voltage unbalance ΔV OS 35 mv Output short circuit current I OS D0 = 0 V, D INx = high, PWRDN and DEN = 2.4 V -90 m High impedance output current I OZ PWRDN or DEN = 0.8 V, D0 = 0 V or V CC μ Power off output current I OX V CC = 0 V, DO = 0 V or 3.6 V μ Output single ended capacitance C O 1 Typ pf Deserializer LVDS DC specifications (pply to pins RI+ and RI ) Differential threshold high voltage V TH V CM = 1.1 V 50 mv Differential threshold low voltage V TL -50 Input current I IN V IN = 2.4 V, V CC = 3.6 V or 0 V μ V IN = 0 V, V CC = 3.6 V or 0 V Input single ended capacitance C I 0.5 Typ pf Serializer supply current (applies to pins DV CC and V CC) Serializer supply current worst case I CCD R L = 27 Ω, See figure 7 f = 10 MHz 25 m f = 66MHz 70 Serializer supply current I CCXD PWRDN = 0.8 V 500 μ Deserializer supply current (applies to pins DV CC and V CC) Deserializer supply current worst case I CCR C L = 15 pf, See figure 7 f = 10 MHz 35 m f = 66MHz 95 Deserializer supply current, power down I CCXR PWRDN = 0.8 V, REN = 0.8 V 1 See footnote at end of table. REV PGE 5

6 TBLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55 C T 125 C Limits Unit Device type: ll Unless otherwise specified Min Max Serializer timing requirement for TCLK Transmit clock period t TCP ns Transmit clock high time t TCIH 0.4T 0.6T Transmit clock low time t TCIL 0.4T 0.6T TCLK input transition time T t(clk) 6 TCLK input jitter t JIT See figure ps (RMS) Frequency tolerance ppm Serializer switching characteristics LVDS low to high transition time t TLH(L) R L = 27 Ω, C L = 10 pf to GND, 0.2 Typ ns LVDS high to low transition time t THL(L) See figure Typ DIN0-DIN9 setup to TCLK t su(di) R L = 27 Ω, C L = 10 pf to GND, 0.5 DIN0-DIN9 hold from TCLK t h(di) See figure 11 4 DO± high to high impedance state delay t d(hz) R L = 27 Ω, C L = 10 pf to GND, 2.5 Typ DO± low to high impedance state delay t d(lz) See figure Typ DO± high to high impedance state to high t d(zh) 5 Typ delay DO± high to high impedance state to low delay t d(zl) 6.5 Typ SYNC pulse duration t w(spw) R L = 27 Ω, See figure 14 6xt TCP Serializer PLL lock time t (PLD) 1026xt TCP Serializer delay t d(s) R L = 27 Ω, See figure 15 t TCP t TCP+3 Deterministic jitter t DJIT R L = 27 Ω, C L = 10 pf to GND 230 Typ ps 150 Typ Random jitter t RJIT R L = 27 Ω, C L = 10 pf to GND 10 Typ ps (RMS) Deserializer timing requirement for REFCLK REFCLK period t RFCP ns REFCLK duty cycle t RFDC 30% 70% REFCLK transition time t t(rf) 6 ns Frequency tolerance ppm See footnote at end of table. REV PGE 6

7 TBLE I. Electrical performance characteristics Continued. Test Symbol Conditions Limits Unit PIN/REF -55 C T 125 C Device type: ll Min Max Unless otherwise specified Deserializer switching characteristics Receiver out clock period t (RCP) t (RCP) = t (TCP), See figure 15 RCLK ns CMOS/TTL low to high transition time CMOS/TTL low to high transition time Deserializer delay t TLH(C) t THL(C) t d(d) 5/ C L = 15 pf, See figure 9 T = 25 C, 3.3 V See figure 16 R OUT0-R OUT9, LOCK, RCLK 1.2 Typ 1.1 Typ 10 MHz 1.75xt (RCP) xt (RCP) MHz 1.75xt (RCP) xt (RCP)+9.7 R OUTx data valid before RCLK t (ROS) See figure 17 RCLK 10 MHz 0.4xt (RCP) RCLK 66 MHz 0.4xt (RCP) R OUTx data valid after RCLK t (ROH) 10 MHz -0.4xt (RCP) 66 MHz -0.4xt (RCP) RCLK duty cycle t (RDC) 40% 60% ns High to high impedance state t d(hz) See figure 18 R OUT0-R OUT9 6.5 Typ ns delay Low to high impedance state t d(lz) 4.7 Typ delay High impedance state to high t d(hr) 5.3 Typ delay High impedance state to low delay t d(zl) 4.7 Typ Deserilaizer PLL lock time from PWRDN (with SYNCPT) Deserilaizer PLL lock time from SYNCPT High impedance state to high delay (power up) Deserializer noise margin t RNM See figure 21 7/ See footnote at end of table. t (DRS1) See figure 19 and MHz 850xt RFCP μs 66 MHz 850xt RFCP 6/ t (DRS2) 10 MHz 2 66 MHz t d(zhlk) LOCK 3 ns 10 MHz 3680 Typ ps 66 MHz 540 Typ REV PGE 7

8 TBLE I. Electrical performance characteristics Continued. 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ pply to D IN0-D IN9, TCLK, PWRDN, TCLK_R/ F, SYNC1, SYNC2, and DEN. 3/ High I IN values are due to pullup and pulldown resistors on the inputs. 4/ pply to pins PWRDN, RCLK_R/ F, REN, and REFCLK = inputs; apply to pins R OUTx, RCLK, and LOCK = outputs (see deserializer truth table) 5/ The deserializer delay time for all frequencies does not exceed two serial bit times. 6/ t (DSR1) represents the time required for the deserialzer to register that a lock has occurred upon power up or when leaving the power down mode. t (DSR2) represents the time required to register that a lock has occurred for power up and enabled deserializer when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPTs). In order to specify deserializer PLL performance, t (DSR1) and t (DSR2) are specified with REFCLK active and stable and specific conditions of SYNCPTs. 7/ t RNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur. REV PGE 8

9 Case X Dimension Symbol Millimeters Symbol Millimeters Min Max Min Max 2.00 E E b e 0.65 Typ c L D NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion. 3. Falls within JEDEC MO-187 variation D. FIGURE 1. Case outline. REV PGE 9

10 Terminal number Case X Device type 01 Device type 02 Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 SYNC1 15 DGND 1 GND 15 R OUT9 2 SYNC2 16 DGND 2 RCLK_R/ F 16 R OUT8 3 D IN0 17 V CC 3 REFCLK 17 R OUT7 4 D IN1 18 GND 4 V CC 18 R OUT6 5 D IN2 19 DEN 5 R I+ 19 R OUT5 6 D IN3 20 GND 6 R I 20 DGND 7 D IN4 21 DO- 7 PWRDN 21 DV CC 8 D IN5 22 DO+ 8 REN 22 DGND 9 D IN6 23 GND 9 RCLK 23 DV CC 10 D IN7 24 PWRDN 10 LOCK 24 R OUT4 11 D IN8 25 GND 11 V CC 25 R OUT3 12 D IN9 26 V CC 12 GND 26 R OUT2 13 TCLK_R/ F 27 DV CC 13 GND 27 R OUT1 14 TCLK 28 DV CC 14 DGND 28 R OUT0 FIGURE 2. Terminal connections. Inputs Outputs PWRDN REN ROUT(0:9) 1/. LOCK 2/ RCLK 1/ 3/ H H Z H Z H H ctive L ctive L X Z Z Z H L Z ctive Z 1/ ROUT and RCLK are 3-stated when LOCK is asserted high. 2/ LOCK output reflects the state of the deserializer with regard to the selected data stream 3/ RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by RCLK_R/ F. FIGURE 3. Deserializer truth table. REV PGE 10

11 FIGURE 4. Block diagrams. FIGURE 5. Timing diagrams and test circuits. REV PGE 11

12 FIGURE 6 Timing diagrams and test circuits. FIGURE 7 Timing diagrams and test circuits. REV PGE 12

13 FIGURE 8 Timing diagrams and test circuits. FIGURE 9 Timing diagrams and test circuits. FIGURE 10 Timing diagrams and test circuits. REV PGE 13

14 FIGURE 11 Timing diagrams and test circuits. FIGURE 12 Timing diagrams and test circuits. FIGURE 13 Timing diagrams and test circuits. REV PGE 14

15 FIGURE 14 Timing diagrams and test circuits. FIGURE 15 Timing diagrams and test circuits. REV PGE 15

16 FIGURE 16 Timing diagrams and test circuits. FIGURE 17 Timing diagrams and test circuits. FIGURE 18 Timing diagrams and test circuits. REV PGE 16

17 FIGURE 19 Timing diagrams and test circuits. REV PGE 17

18 FIGURE 20 Timing diagrams and test circuits. t SW: Setup and hold tiem (Internal data sampling window) t DJIT: Serializer output bit position jitter that results from jitter on TCLK t RNM: Receiver noise margin time FIGURE 21 Timing diagrams and test circuits. REV PGE 18

19 VOD = (D O+) (D O-) Differential output signal is shown as (D O+) (D O-) FIGURE 22. Timing diagrams and test circuits. FIGURE 23. Timing diagrams and test circuits. REV PGE 19

20 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top side Marking -01XE SN65LV1023MDBREP LV1023MEP -02XE SN65LV1224BMDBREP LV1224BMEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV PGE 20