DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL, CMOS, THREE-PORT CABLE TRANSCEIVER/ARBITER, MONOLITHIC SILICON

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED dd device type -02 as a substitute for device type -01. Obsolete device type -01. Correct vendor datasheet errors for limits of V DD, V OD, I OZ parameters. Update boilerplate to current revision. - CFS Thomas M. Hess B dd device type PHN Thomas M. Hess C Update boilerplate paragraphs to current requirements. - PHN Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV C C C C C C C C C C C C C C C C PGE PMIC N/ PREPRED BY Charles F. Saffle Original date of drawing CHECKED BY Charles F. Saffle PPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITL, CMOS, THREE-PORT CBLE TRNSCEIVER/RBITER, MONOLITHIC SILICON CODE IDENT. NO. REV C PGE 1 OF 16 MSC N/ 5962-V083-12

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Three-Port Cable Transceiver/rbiter microcircuit, with an operating temperature range of -40 C to +110 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 1/ TSB41B3-EP Three-Port Cable Transceiver/rbiter 02 1/ TSB41B3-EP Three-Port Cable Transceiver/rbiter 03 TSB41B3B-EP Three-Port Cable Transceiver/rbiter Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 80 JEDEC MS-026 Plastic Quad Flatpack Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium 1/ Device type -02 is a substitute for the obsolete device type -01. REV C PGE 2

3 1.3 bsolute maximum ratings. 2/ Supply voltage range (V DD) V to +4.0 V 3/ Input voltage range (V I) V to V DD V 3/ Output voltage range at any output (V O) V to V DD V Continuous total power dissipation:... See dissipation rating table Operating free-air temperature range (T ) C to +110 C Storage temperature range (T STG) C to +150 C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds C Dissipation rating table: Case T 65 C Outline Power Rating Derating Factor 4/ bove T = 25 C T = 70 C Power rating T = 110 C Power rating Case X 5/ 5.05 W 52.5 mw/ C 2.69 W 587 mw Case X 6/ 3.05 W 31.7 mw/ C 1.62 W 355 mw Case X 7/ 2.01 W 20.3 mw/ C 1.1 W 284 mw 1.4 Recommended operating conditions. 8/ Supply voltage range (3.3 V DD): Source power node V to + Non-source power node V to + 9/ Supply voltage range (1.8 V DD) V to +2.0 V Minimum high level input voltage (V IH): LREQ, CTL0, CTL1, D0-D7, LCLK_PMC V Device 01: S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE,TPBIS0_SD0, TPBIS1_SD1, TPBIS2_SD xV DD Device 02, 03: S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIS0_SD0, TPBIS1_SD1, TPBIS2_SD xV DD RESETz or RESET xV DD 10/ Maximum low level input voltage (V IL): LREQ, CTL0, CTL1, D0-D7, LCLK_PMC V Device 01: S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIS0_SD0, TPBIS1_SD1, TPBIS2_SD xV DD Device 02, 03: S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIS0_SD0, TPBIS1_SD1, TPBIS2_SD xV DD RESETz or RESET xV DD 10/ 2/ Stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3/ ll voltage values, except differential I/O bus voltages, are with respect to network ground. 4/ This is the inverse of the traditional junction to ambient thermal resistance (R θj). 5/ 2 oz. trace copper pad with solder. 6/ 2 oz. trace copper pad without solder. 7/ For more information see manufacturer application report. 8/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer /or distributor maintain no responsibility or liability for product used beyond the stated limits. 9/ For a node that does not source power; see Section in IEEE 1394a / RESETz is for device type 01 02; RESET is for device type 03 REV C PGE 3

4 1.4 Recommended operating conditions - Continued. Output current (I OL/OH): Device 01: CTL0, CTL1, D0-D7, S5_LKON_DS2, PINT, PCLK m to +4.0 m Device 02, 03: CTL0, CTL1, D0-D7, S5_LKON, PINT, PCLK m to +4.0 m Output current (I O) (TPBIS outputs) m to +1.3 m Operating free-air temperature range (T ) C to +110 C Maximum junction temperature (T J): R θj = 19 C/W (T = 110 C) C 1394b Differential input voltage (V ID): Cable inputs, during data reception mv to 800 mv 1394a Differential input voltage range (V ID): Cable inputs, during data reception mv to 260 mv Cable inputs, during arbitration mv to 265 mv 1394a Common-mode input voltage (V IC): TPB cable inputs, source power node V to V TPB cable inputs, non-source power node V to V 9/ Minimum power-up reset time (t (pu)) (RESETz or RESET input)... 2 ms 10/ 11/ Maximum receive input jitter: TP, TPB cable inputs, S100 operation... ±1.08 ns TP, TPB cable inputs, S200 operation... ±0.5 ns TP, TPB cable inputs, S400 operation... ±0.315 ns Maximum receive input skew: Between TP TPB cable inputs, S100 operation... ±0.8 ns Between TP TPB cable inputs, S200 operation... ±0.55 ns Between TP TPB cable inputs, S400 operation... ±0.5 ns 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEP95 Registered Stard Outlines for Semiconductor Devices (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ) THE INSTITUTE OF ELECTRICL ND ELECTRONICS ENGINEERS (IEEE) IEEE (1394) Stard for High-Performance Serial Bus IEEE 1394a (1394) Stard for High-Performance Serial Bus Supplement IEEE 1394b (1394) Stard for High-Performance Serial Bus Supplement (Copies of these documents are available online at or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ / Time after valid clock received at PHY XI input terminal. REV C PGE 4

5 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently legibly marked with the manufacturer s part number as shown in 6.3 herein as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number with items C (if applicable) above. 3.3 Electrical characteristics. The maximum recommended operating conditions electrical performance characteristics are as specified in 1.3, 1.4, table I herein. 3.4 Design, construction, physical dimension. The design, construction, physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in figure Block diagrams. The block diagrams shall be as shown in figure Terminal connections. The terminal connections shall be as shown in figure Timing waveforms test circuit. The timing waveforms test circuit shall be as shown in figure 4. REV C PGE 5

6 TBLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions unless otherwise specified V DD Temperature, T Device type Min Limits Max Unit DEVICE Supply current 3.3 V DD I DD 2/ 3.3 V 25 C ll 75 Typ m Power status threshold, CPS input V (TH) 3/ 400 kω resistor 3.0 V -40 C to +110 C V High level output voltage V OH I OH = -4 m For CTL0, CTL1, D0-D7, PCLK, S5_LKON_DS2 or S5_LKON outputs. 3.0 V 2.8 V Low level output voltage V OL I OL = 4 m For CTL0, CTL1, D0-D7, PCLK, S5_LKON_DS2 or S5_LKON outputs. 3.0 V 0.4 V Positive peak bus holder current I BH+ V I = 0 V to V DD For CTL0, CTL1, D0-D7, LREQ m Negative peak bus holder current I BH- V I = 0 V to V DD For CTL0, CTL1, D0-D7, LREQ m Off-state output current I OZ V O = V DD or 0 V For CTL0, CTL1, D0-D7, S5_LKON_DS2 or S5_LKON I/Os 3.0 V ±30 µ Pullup current, RESETz or RESET input 4/ Output voltage, TPBIS I IRST V I = 1.5 V or 0 V 3.0 V V O t rated I O current. 3.0 V µ V See footnotes at end of table. REV C PGE 6

7 TBLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified V DD Temperature, T Device type Min Limits Max Unit DRIVER 1394a differential output voltage 1394b differential output voltage V OD R L = 56Ω See figure V -40 C to +110 C ll mv V OD mv Driver difference current I DIFF Drivers enabled, speed signaling off For TP+, TP-, TPB+, TPB / / m Common-mode speed signaling current I SP200 S200 speed signaling enabled For TPB+, TPB / / m I SP400 S400 speed signaling enabled For TPB+, TPB / / m Off state differential voltage V OFF Drivers disabled. See figure mv RECEIVER Differential impedance z id Drivers disabled. 3.0 V Common-mode impedance -40 C to +110 C ll 4 kω 4 pf z ic Drivers disabled. 20 kω 24 pf Receiver input threshold voltage V TH-R Drivers disabled mv Cable bias detect threshold voltage V TH-CB Drivers disabled. For TPB+ TPB- cable inputs V Positive arbitration comparator threshold voltage Negative arbitration comparator threshold voltage V TH+ Drivers disabled mv V TH- Drivers disabled mv Speed signal threshold V TH-SP200 TPBIS-TP common mv V TH-SP400 mode voltage, drivers disabled mv See footnotes at end of table. REV C PGE 7

8 TBLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified V DD Temperature, T Device type Min Limits Max Unit Thermal Characteristics Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance R θj 7/ 3.3 V +25 C ll Typ C/W R θjc 0.17 Typ C/W R θj 8/ Typ C/W R θjc 0.17 Typ C/W R θj 9/ Typ C/W R θjc 3.11 Typ C/W Switching Characteristics TP differential rise time, transmit TP differential fall time, transmit t r 10% to 90% t 1394 connector. t f 90% to 10% t 1394 connector. 3.0 V -40 C to +110 C ll ns ns Setup time, CTL0, CTL1, D1-D7, LREQ to PCLK Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK t su 1394a % to 50% See figure 4. t h 1394a % to 50% See figure ns 0 ns Setup time, CTL0, CTL1, D1-D7, LREQ to LCLK_PMC t su 1394b 50% to 50% See figure ns Hold time, CTL0, CTL1, D1-D7, LREQ after LCLK_PMC t h 1394b 50% to 50% See figure 4. 0 ns Delay time, PCLK to CTL0, CTL1, D1-D7, PINT t d 1394a b 50% to 50% See figure ns See footnotes at end of table. REV C PGE 8

9 TBLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions unless otherwise specified V DD Temperature, T Device type Min Limits Max Unit LPS Timing Parameters LPS low time T LPSL When pulsed. 10/ 3.0 V -40 C to 01, µs LPS high time T LPSH When pulsed. 10/ +110 C µs LPS duty cycle When pulsed. 11/ 20% 60% LPS reset time T LPS_RESET Time for PHY to recognize LPS deasserted reset the interface. LPS disable time, T LPS_DISBLE Time for PHY to recognize LPS deasserted disable the interface µs µs Restore time T RESTORE Time to permit optional isolation circuits to restore during an interface reset / µs PCLK activation time T CLK_CTIVTE Time for PCLK to be activated from reassertion of LPS. PHY not in low-power state. 60 ns Time for PCLK to be activated from reassertion of LPS. PHY in low-power state ms See footnotes on next sheet. REV C PGE 9

10 TBLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization /or design. 2/ Repeat Max Packet (1 port receiving maximum size isochronous packet 4096 bytes, sent on every isochronous interval, data value of 0xCCCCCCCCh for device type 01, or 0x00FF00FFh for device type 02; 2 ports repeating; all ports with S400 betamode connection), V DD3.3 = 3.3 V, internal regulator, T = 25 C. 3/ Measured at cable power side of resistor. 4/ RESETz is for device type 01 02; RESET is for device type 03. 5/ Limits defined as algebraic sum of TP+ TP- driver currents. Limits also apply to TPB+ TPB- algebraic sum of driver currents. 6/ Limits defined as absolute limit of each of TPB+ TPB- driver currents. 7/ Board mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal l with 2 oz. copper. 8/ Board mounted, no air flow, high conductivity TI recommended test board with thermal l but no solder or grease thermal connection to thermal l with 2 oz. copper. 9/ Board mounted, no air flow, high conductivity JEDEC test board with 1 oz. copper. 10/ The specified T LPSL T LPSH times are worst-case values appropriate for operation with the TSB41B3. These values are broader than those specified for the same parameters in the 1394a-2000 Supplement (i.e., an implementation of LPS that meets the requirements of 1394a-2000 operates correctly with the TSB41B3). 11/ pulsed LPS signal must have a duty cycle (ratio of T LPSH to cycle period) in the specified range to ensure proper operation when using an isolation barrier on the LPS signal. 12/ The maximum value for T RESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less than T PLS_DISBLE. REV C PGE 10

11 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max D D TYP 9.50 TYP TYP 0.25 TYP E E b e TYP 0.50 TYP C NOM 0.13 NOM K D NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MS The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically thermally connected to the backside of the die possibly selected leads. 4. Body dimensions include mold flash or protrusions. FIGURE 1. Case outline. REV C PGE 11

12 REV C PGE 12

13 Device type 01 FIGURE 2. Block diagrams. REV C PGE 13

14 Device type 02, 03 Note: 1. RESETz is for device type 02 RESET is for device type 03. FIGURE 2. Block diagrams - Continued. REV C PGE 14

15 Case X Device type 01, Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 PINT 21 GND 41 TPB0-61 GND 2 S5_LKON_DS2/ S5_LKON 1/ 22 R1 42 TPB0+ 62 GND 3 LREQ 23 R0 43 GND 63 VDD 4 DGND 24 VDD 44 VDD 64 DGND 5 PCLK 25 PLLGND 45 TP0-65 DVDD DVDD XO 46 TP0+ 66 S2_PC0 7 LCLK_PMC 27 XI 47 TPBIS0_SD0 67 S1_PC1 8 DVDD PLLGND 48 TPB1-68 S0_PC2 9 CTL0 29 PLLVDD TPB1+ 69 DVDD CTL1 30 PLLVDD GND 70 DVDD D0 31 PLLVDD VDD 71 DVDD D1 32 S4_DS1 52 TP1-72 DGND 13 D2 33 S3_DS0 53 TP1+ 73 VREG_PD 14 DGND 34 CPS 54 TPBIS1_SD1 74 BMODE 15 D3 35 SE 55 TPB2-75 RESETz / RESET 2/ 16 D4 36 SM 56 TPB2+ 76 DGND 17 D5 37 DVDD VDD 77 PD 18 DVDD DGND 58 TP2-78 TESTM 19 D6 39 VDD 59 TP2+ 79 SLPEN 20 D7 40 GND 60 TPBIS2_SD2 80 LPS Notes: 1/ S5_LKON_DS2 is for device type 01 S5_LKON is for device type 02. 2/ RESETz is for device type 02 RESET is for device type 03. FIGURE 3. Terminal connections. REV C PGE 15

16 FIGURE 4. Timing waveforms test circuit. REV C PGE 16

17 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection test requirements as indicated in their internal documentation. Such procedures should include proper hling of electrostatic sensitive devices, classification, packaging, labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, marking shall be in accordance with the manufacturer s stard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL L Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top-Side Marking -01XE 2/ TSB41B3TPFPEP TSB41B3TEP -02XE TSB41B3TPFPEP TSB41B3TEP -03XE TSB41B3BTPFPEP TSB41B3BTEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ No longer available from an approved source of supply. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV C PGE 17