DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, 17 V, 1.5 A SYNCHRONOUS STEP-DOWN CONVERTER, MONOLITHIC SILICON REVISIONS

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED dd device type PHN Thomas M. Hess B dd device type PHN Thomas M. Hess C dd test conditions to the P-channel MOSFET current limit test under Table I. dd footnote 4/ under paragraph 1.4. Update document paragraphs to current requirements. - ro Charles F. Saffle CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV C C C C C C C C C C PGE PMIC N/ PREPRED BY Phu H. Nguyen Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen PPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, LINER, 17 V, 1.5 SYNCHRONOUS STEP-DOWN CONVERTER, MONOLITHIC SILICON CODE IDENT. NO. REV C PGE 1 OF 10 MSC N/ 5962-V119-14

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 17 V, 1.5 synchronous step-down converter microcircuit, with an extended operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s). 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device Generic Output voltage Circuit function 01 TPS62110-EP djustable 1.2 V to 16 V 17-V, 1.5- synchronous step-down converter 02 TPS62111-EP 3.3 V 17-V, 1.5- synchronous step-down converter 03 TPS62112-EP 5.0 V 17-V, 1.5- synchronous step-down converter Case outline(s). The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-220 Plastic quad flatpack Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other REV C PGE 2

3 1.3 bsolute maximum ratings. 1/ Supply voltage at VIN, VIN V to 20.0 V Voltage at SW (V I ) V to V I Voltage at EN, SYNC, LBO, PG (V I ) V to 20.0 V Voltage at LBI, FB (V I ) V to 7.0 V Output current at SW (I O ) m Maximum junction temperature (T J ) C 2/ Storage temperature (T STG ) C to +150 C Lead temperature 1.6 mm (1/16 in) from case for 10 seconds C Dissipation rating 3/ Case T 25 C Derating factor T = 70 C T = 85 C outline Power rating above T = 25 C Power rating Power rating X 2.5 W 25 mw/ C W 1 W 1.4 Recommended operating conditions. 4/ Supply voltage at VIN, VIN (V CC ) V to 17 V Maximum voltage at power good, LBO, EN, SYNC V Operating junction temperature (T J ) C to +125 C 1/ Stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Long term high temperature storage and/or extended used at maximum recommended operating conditions may result in a reduction of overall device life. See manufacturer for additional information about enhanced plastic packaging. 3/ Based on a thermal resistance of 40 K/W soldered onto a high K board. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. REV C PGE 3

4 2. PPLICBLE DOCUMENTS JEDEC Solid State Technology ssociation JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as specified on figure Functional Block diagram. The functional block diagram shall be as specified on figure 3. REV C PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ unless otherwise specified Device type Limits Unit Supply current Min Max Input voltage range 3/ V I ll V Operating quiescent current Shutdown current I (Q) I (SD) I O = 0 m, SYNC = GND, V I = 7.2 V, T = 25 C 4/ I O = 0 m, SYNC = GND, V I = 17 V 4/ ll 20 typical μ , EN = GND ll 5 μ EN = GND, V I = 7.2 V, T = 25 C 3 Enable EN high level input voltage V IH ll 1.3 V EN low level input voltage V IL ll 0.3 V EN trip point hysteresis ll 170 typical mv EN input leakage current I IKG EN = GND or V I, V I = 17 V ll 0.2 μ EN input current I (EN) 0.6 V V (EN) 4 V ll 10 typical μ Undervoltage lockout threshold V (UVLO) Input voltage falling ll V Undervoltage lockout hysteresis ll 250 typical mv Power switch P-channel MOSFET on resistance r DS(ON) V I 5.4, I O = 350 m ll 250 m V I = 3.5 V, I O = 200 m V I = 3 V, I O = 100 m 340 typical 490 typical P-channel MOSFET leakage current V DS = 17 V ll 1 μ P-channel MOSFET current limit V I = 7.2 V, V O = 3.3 V ll 2400 typical m N-channel MOSFET on resistance r DS(ON) V I 5.4, I O = 350 m ll 200 m V I = 3.5 V, I O = 200 m V I = 3 V, I O = 100 m 170 typical 200 typical N-channel MOSFET leakage current V DS = 17 V ll 3 μ Power good output low battery input (LBI), low battery output (LBO) PG trip voltage V (PG) ll V O 1.6% typical V PG delay time V O ramping positive ll 50 typical μs V O ramping negative 200 typical PG, LBO output low voltage V OL V FB = 1.1 x V O nominal, I OL = 1 m ll 0.3 V PG, LBO sink current I OL ll 1 typical m PG, LBO output leakage current V FB = V O nominal ll 0.25 μ See footnote at end of table. REV C PGE 5

6 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Test conditions 2/ unless otherwise specified Device type Limits Unit Min Max Power good output LBI, LBO continued. Minimum supply voltage for valid PG, LBI, LBO signal ll 3 typical V LBI trip voltage V LBI Input voltage falling ll typical V LBI input leakage current I LBI ll 100 n LBI trip point accuracy ll 1.5% LBI hysteresis Oscillator Oscillator frequency V LBI,HYS f S ll 25 typical mv ll khz Synchronization range f (SYNC) CMOS logic clock signal on SYNC pin ll khz SYNC high level input voltage SYNC low level input voltage V IH V IL ll 1.5 V ll 0.3 V SYNC input leakage current I lkg SYNC = gnd or V IN ll 0.2 μ SYNC trip point hysteresis ll 170 typical mv SYNC input current Duty cycle of external clock signal 0.6 V V (SYNC) 4 V ll 20 μ ll 30% 90% See footnote at end of table. REV C PGE 6

7 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Test conditions 2/ unless otherwise specified Device type Limits Unit Output Min Max djustable output voltage range 3/ V O V FB voltage V FB typical V FB leakage current n FB voltage tolerance 4/ V I = 3.1 V to 17 V, 0 m I O 1500 m 5/ Fixed output voltage tolerance 6/ V I = 3.8 V to 17 V, 0 m I O 1500 m 5/ V I = 5.5 V to 17 V, % m I O 1500 m 5/ Maximum output current I O V I 3 V (once undervoltage lockout voltage exceeded) Current into internal voltage divider for fixed voltage versions V I 3.5 V V I 4.3 V V I 6 V ll 100 typical m 500 typical 1200 typical 1500 typical ll 5 typical μ Efficiency ŋ V I 7.2 V, V O = 3.3 V, I O = 600 m ll 92% typical V I 12 V, V O = 5 V, I O = 600 m Duty cycle range for main switches t 1 MHz ll 10% 100% Minimum t on time for main switch ll 100 typical ns Shutdown temperature ll 145 typical C Startup time I O = 800 m, V I = 12 V, V O = 3.3 V ll 1 typical ms 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ V I = 12 V, V O = 3.3 V, I O = 600 m, EN = V I, T = T J = -55 C to 125 C. 3/ Not production tested. 4/ Device is not switching. 5/ The maximum output current depends on the input voltage. 6/ The output voltage accuracy includes line and load regulation over the full temperature range T = -55 C to 125 C. See the section for no-load operation in the manufacturer data. REV C PGE 7

8 Case X Symbol Millimeters Symbol Millimeters Min Max Min Max D/E e 0.65 BSC REF e BSC b S Notes: 1. ll liner dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Quad flatpack, no leads (QFN) package configuration. 4. The package thermal pad must be soldered to the board for thermal and mechanical performance. See manufacturer data for details regarding the exposed thermal pad dimensions. 5. Falls within JEDEC MO-220. FIGURE 1. Case outline. REV C PGE 8

9 Terminal number Case X Terminal symbol Terminal number Terminal symbol 1 PGND 9 GND 2 VIN 10 FB 3 VIN 11 GND 4 EN 12 GND 5 SYNC 13 PG 6 LBO 14 SW 7 LBI 15 SW 8 VIN 16 PGND FIGURE 2. Terminal connections. FIGURE 3. Functional block diagram. REV C PGE 9

10 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Top side marking Vendor part number -01XE TPS62110-EP TPS62110MRSREP -02XE TPS62111-EP TPS62111MRSREP -03XE TPS62112-EP TPS62112MRSREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV C PGE 10