3-W High-Voltage Switchmode Regulator

Transcription

1 End of Life. Last Available Purchase Date is -Dec-0 Si900 -W High-Voltage Switchmode Regulator FEATURES 0- to 0-V Input Range Current-Mode Control On-Chip 50-V, 5- MOSFET Switch Reference Selection Si900 % High Efficiency Operation (> 0%) Internal Start-Up Circuit Internal Oscillator ( MHz) SHUTDOWN and RESET DESCRIPTION The Si900 high-voltage switchmode regulators are monolithic BiC/DMOS integrated circuits which contain most of the components necessary to implement high-efficiency dc-to-dc converters up to watts. They can either be operated from a low-voltage dc supply, or directly from a 0- to 0-V unregulated dc power source. The Si900 may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward), or by using a level shift circuit can generate a +5-V or a 5-V non-isolated output from a -V source. The Si900 is available in both standard and lead (Pb)-free -pin plastic DIP and 0-pin PLCC packages which are specified to operate over the industrial temperature range of 0 C to 5 C. FUNCTIONAL BLOCK DIAGRAM FB COMP DISCHARGE OSC IN OSC OUT (0) () 9 () () (0) V REF 0 () Ref Gen + Error Amplifier V (%) V + +. V Current-Mode Comparator C/L Comparator OSC Clock ( / OSC ) R Q S (5) 5 () DRAIN V IN (BODY) BIAS () (9) Current Sources To Internal Circuits () SOURCE +V IN () +. V 9. V + Undervoltage Comparator Q S R () () SHUTDOWN RESET Note: Figures in parenthesis represent pin numbers for 0-pin package. Applications information, see AN0 and AN.

2 ABSOLUTE MAXIMUM RATINGS Voltages Referenced to V IN ( < +V IN + 0. V) V +V IN V V DS V I D (Peak) (Note: 00 s pulse, % duty cycle) A I D (rms) ma Logic Inputs (RESET, SHUTDOWN, OSC IN) V to + 0. V Linear Inputs (FEEDBACK, SOURCE) V to V HV Pre-Regulator Input Current (continuous) ma Storage Temperature to 5 C Operating Temperature to 5 C Junction Temperature (T J ) C Power Dissipation (Package) a -Pin Plastic DIP (J Suffix) b mw 0-Pin PLCC (N Suffix) c mw Thermal Impedance ( JA ) -Pin Plastic DIP C/W 0-Pin PLCC C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate mw/ C above 5 C c. Derate. mw/ C above 5 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Voltages Referenced to V IN V to.5 V +V IN V to 0 V f OSC khz to MHz R OSC k to M Linear Inputs to V Digital Inputs to SPECIFICATIONS a Reference Parameter Symbol Test Conditions UnlessOtherwise Specified Limits DISCHARGE = V IN = 0 V = 0 V, +V IN = V R BIAS = 90 k, R OSC = 0 k Temp b Min c Typ d Max c Unit Output Voltage V R OSC IN = V IN (OSC Disabled), R L = 0 M Room V Output Impedance e Z OUT Room k Short Circuit Current I SREF V REF = V IN Room A Temperature Stability e T REF Full mv/ C Oscillator Maximum Frequency e f MAX R OSC = 0 Room MHz Initial Accuracy f OSC R OSC = 50 k, See Note f Room R OSC = 0 k, See Note f Room khz Voltage Stability f/f f/f = f(.5 V) f, (9.5 V)/f(9.5 V) Room 0 5 % Temperature Coefficient e T OSC Full ppm/ C Error Amplifier Feedback Input Voltage V FB FB Tied to COMP OSC In = V IN (OSC Disabled) Room V Input BIAS Current I FB OSC IN = V IN, V FB = V Room na Input OFFSET Voltage V OS Room 5 0 mv Open Loop Voltage Gain e A VOL Unity Gain Bandwidth e OSC IN = V IN, (OSC Disabled) BW Room 0 0 db Room MHz Dynamic Output Impedance e Z OUT Room SOURCE (V FB =. V) Room.0. Output Current I OUT SINK (V FB =.5 V) Room ma Power Supply Rejection PSRR OSC IN = V IN, (OSC Disabled) Room 50 0 db

3 SPECIFICATIONS a Test Conditions UnlessOtherwise Specified Limits Parameter Symbol DISCHARGE = V IN = 0 V = 0 V, +V IN = V R BIAS = 90 k, R OSC = 0 k Temp b Min c Typ d Max c Unit Current Limit Threshold Voltage V SOURCE R L = 00 from DRAIN to V FB = 0 V Delay to Output e t d R L = 00 from DRAIN to V SOURCE =.5 V, See Figure Room.0.. V Room ns Pre-Regulator/Start-Up Input Voltage +V IN I IN = 0 A Room 0 V Input Leakage Current +I IN 0 V Room 0 A Pre-Regulator Start-Up Current I START Pulse Width 00 s = V UVLO Room 5 ma Pre-Regulator Turn-Off Threshold Voltage V REG I PRE-REGULATOR = 0 A Room Undervoltage Lockout V UVLO R L = 00 from DRAIN to See Detailed Description Room V V REG V UVLO V DELTA Room Supply Supply Current I CC Room ma Bias Current I BIAS Room A Logic SHUTDOWN Delay e t SD V SOURCE = V IN, See Figure Room SHUTDOWN Pulse Width e t SW Room 50 RESET Pulse Width e t RW See Figure Latching Pulse Widthe t SHUTDOWN and RESET Low LW Room 50 ns Room 5 Input Low Voltage V IL Room.0 Input High Voltage V IH Room.0 Input Current, Input Voltage High I IH V IN = 0 V Room 5 Input Current, Input Voltage Low I IL V IN = 0 V Room 5 5 MOSFET Switch V A Breakdown Voltage V (BR)DSS V SOURCE = SHUTDOWN = 0 V I DRAIN = 00 A Full 50 0 V Drain-Source On Resistance g r DS(on) V SOURCE = 0 V, I DRAIN = 00 ma Room 5 Drain Off Leakage Current I DSS V SOURCE = SHUTDOWN = 0 V V DRAIN = 00 V Room 0 A Drain Capacitance C DS V SOURCE = SHUTDOWN = 0 V Room 5 pf Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 5 C, Full = as determined by the operating temperature suffix. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. f. C STRAY Pin = 5 pf g. Temperature coefficient of r DS(on) is 0.5% per C, typical.

4 TIMING WAVEFORMS SOURCE 0 DRAIN 0.5 V 50% t d t r 0 ns 0% SHUTDOWN 0 DRAIN 0 50% t SD t f 0 ns 0% FIGURE. FIGURE. SHUTDOWN 0 RESET 0 t SW t 50% 50% r, t f 0 ns t LW 50% 50% t RW 50% FIGURE. TYPICAL CHARACTERISTICS 0 +V IN vs +I IN at Start-Up M Output Switching Frequency vs. Oscillator Resistance = V IN 0 00 (V) +V IN 0 0 (Hz) f OUT 00 k k M +I IN (ma) r OSC Oscillator Resistance ( ) FIGURE. FIGURE 5.

5 PIN CONFIGURATIONS PDIP- PIN DESCRIPTION Pin Function -Pin DIP 0-Pin PLCC* BIAS +V IN DRAIN 5 Top View SOURCE V IN 5 PLCC-0 9 OSC OUT OSC IN DISCHARGE V REF 0 SHUTDOWN RESET COMP FB 0 *Pins,,,, 5, and 9 = N/C 9 0 Top View ORDERING INFORMATION Standard Part Number Lead (Pb)-Free Part Number Temperature Range Package Si900DJ0 Si900DN0 Si900DJ0 E Si900DN0 E 0 to 5 C PDIP- PLCC-0 DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si900 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary bootstrap winding on the output inductor or transformer. When power is first applied during start-up, +V IN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +V IN and. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the pin. The constant current is disabled when exceeds 9. V. If is not forced to exceed the 9.-V threshold, then will be regulated to a nominal value of 9. V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until exceeds the undervoltage lockout threshold (typically. V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to such that the constant current source is always disabled. 5

6 DETAILED DESCRIPTION (CONT D) Note: During start-up or when drops below 9. V the start-up circuit is capable of sourcing up to 0 ma. This may lead to a high level of power dissipation in the IC (for a -V input, approximately W). Excessive start-up time caused by external loading of the supply can result in device damage. Figure gives the typical pre-regulator current at start-up as a function of input voltage. BIAS To properly set the bias for the Si900, a 90-k resistor should be tied from BIAS to V IN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 5 A. Reference Section The reference section of the Si900 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is V. During the reference trimming procedure the error amplifier is connected for unity gain in order to compensate for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with around-the-amplifier compensation. A MOS differential input stage provides for low input leakage current. The noninverting input to the error amplifier (V REF ) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to V IN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization is accomplished by capacitive coupling of a positive SYNC pulse into the OSC IN terminal. For a 5-V pulse amplitude and 0.5- s pulse width, typical values would be 00 pf in series with k to OSC IN. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Table. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN RESET Output H H Normal Operation H Output Switch Normal Operation (No Change) L H Off (Not Latched) L L Off (Latched) L Off (Latched, No Change) The output switch is a 5-, 50-V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic body-drain diode. However, the body contact in the Si900 is connected internally to V IN and is independent of the SOURCE.

7 APPLICATIONS C 0 F R 50 k C 0. F Si900DJ U L ADC C F R. k C5 0 F 0 V N50 CR R5 00 k Q MPSA9 C 0. F R.9 k R % R9 % R0 5 k GND +5 V 00 ma V C 0. F C 0. F 0 R 90 k 5 9 R / W R TL C U FIGURE. Buck-Boost, Non-Isolated -W Supply C 0 F R 50 k C 0. F Si900DJ U N50 CR C F C5 0 F 0 V L ADC R R5. k 00 k Q MPSA9 C 0. mf R.9 k R % R9 % R0 5 k GND 5 V 00 ma V C 0. F C 0. F 0 R 90 k 5 9 R / W R TL C U 5 V FIGURE. Non-Isolated -W Supply (Buck)

8 +V IN 00 H N59 GND +5 V 0 F 50 H 0. F 0 F 5 GND k 0. F F 90 k 0 k 0.0 F 5 V Si900DJ N F / W 50 k 0. F k N V IN ( VDC) FIGURE. -W Flyback Converter for Telecommunications Power Supplies* * For additional information on using the Si900 in telecommunications and ISDN power supplies, see AN and AN0. maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see

9 Package Information PLCC: O-LEAD (POWER IC ONLY) DSQUARE A D SQUARE e B B D MILLIMETERS INCHES Dim Min Max Min Max A A A B B D D D e. BSC BSC A ECN: S-00 Rev. A, 0-Feb-0 DWG: 59 A 0.0 mm 0.00 Document Number: -Jan-0

10 Package Information PDIP: -LEAD (POWER IC ONLY) 0 9 E E 5 S D Q A A L B e B C e A 5 MAX MILLIMETERS INCHES Dim Min Max Min Max A A B B C D E E e e A L Q S ECN: S-00 Rev. A, 0-Feb-0 DWG: 599 Document Number: -Jan-0

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