E M27C Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM

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1 6 Mbit (2Mb x 8 or Mb x 6) UV PROM and OTP PROM 5V ± 0% SUPPLY VOLTAG in RAD OPRATION ACCSS TIM: 50ns BYT-WID or WORD-WID CONFIGURABL 6 Mbit MASK ROM RPLACMNT LOW POWR CONSUMPTION Active Current 70mA at 8MHz Standby Current 00µA PROGRAMMING VOLTAG: 2.5V ± 0.25V PROGRAMMING TIM: 50µs/word LCTRONIC SIGNATUR Manufacturer Code: 20h Device Code: Bh FDIP42W (F) 42 SDIP42 (S) PDIP42 (B) DSCRIPTION The is a 6 Mbit PROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organised as either 2 Mbit words of 8 bit or Mbit words of 6 bit. The pin-out is compatible with a 6 Mbit Mask ROM. The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the is offered in PDIP42, SDIP42, PLCC44 and SO44 packages. PLCC44 (K) Figure. Logic Diagram V CC 20 A0-A9 G 44 SO44 (M) Q5A 5 Q0-Q4 BYTV PP V SS AI00739B

2 Figure 2. DIP Connections Figure 3. PLCC Connections A8 A7 A7 A6 A5 A4 A3 A2 A A0 V SS G Q0 Q8 Q Q9 Q2 Q0 Q3 Q A9 A8 A9 A0 A A2 A3 A4 A5 A6 BYTVPP VSS Q5A- Q7 Q4 Q6 Q3 Q5 Q2 Q4 V CC A4 A3 A2 A A0 VSS G Q0 Q8 Q 2 A5 A6 A7 A7 A8 VSS Q9 Q2 23 Q0 Q3 Q NC A9 A8 44 V CC Q4 A9 A0 A Q2 Q5 Q3 34 A2 A3 A4 A5 A6 BYTV PP VSS Q5A Q7 Q4 Q6 AI0302 AI00740 Figure 4. SO Connections NC A8 A7 A7 A6 A5 A4 A3 A2 A A0 VSS G Q0 Q8 Q Q9 Q2 Q0 Q3 Q AI0264 NC A9 A8 A9 A0 A A2 A3 A4 A5 A6 BYTVPP VSS Q5A- Q7 Q4 Q6 Q3 Q5 Q2 Q4 V CC Table. Signal Names A0-A9 Address Inputs Q0-Q7 Data Outputs Q8-Q4 Data Outputs Q5A Data Output / Address Input Chip nable G Output nable BYTV PP Byte Mode / Program Supply V CC Supply Voltage V SS Ground NC Not Connected Internally

3 Table 2. Absolute Maximum Ratings () Symbol Parameter Value Unit T A Ambient Operating Temperature (3) 40 to 25 C T BIAS Temperature Under Bias 50 to 25 C T STG Storage Temperature 65 to 50 C V IO (2) Input or Output Voltage (except A9) 2 to 7 V V CC Supply Voltage 2 to 7 V V A9 (2) A9 Voltage 2 to 3.5 V V PP Program Supply Voltage 2 to 4 V Note:. xcept for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. xposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SUR Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is V CC +0.5VwithpossibleovershoottoV CC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode G BYTV PP A9 Q5A Q8-Q4 Q7-Q0 Read Word-wide V IL V IL V IH X Data Out Data Out Data Out Read Byte-wide Upper V IL V IL V IL X V IH Hi-Z Data Out Read Byte-wide Lower V IL V IL V IL X V IL Hi-Z Data Out Output Disable V IL V IH X X Hi-Z Hi-Z Hi-Z Program V IL Pulse V IH V PP X Data In Data In Data In Verify V IH V IL V PP X Data Out Data Out Data Out Program Inhibit V IH V IH V PP X Hi-Z Hi-Z Hi-Z Standby V IH X X X Hi-Z Hi-Z Hi-Z lectronic Signature V IL V IL V IH V ID Code Codes Codes Note: X = VIH or VIL, VID = 2V ± 0.5V. Table 4. lectronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q Q0 Hex Data Manufacturer s Code V IL h Device Code V IH Bh Note: Outputs Q5-Q8 are set to '0'.

4 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times 0ns 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages.5V 0.8V and 2V Figure 5. AC Testing Input Output Waveform High Speed 3V Figure 6. AC Testing Load Circuit.3V N94.5V 0V 3.3kΩ Standard 2.4V 2.0V DVIC UNDR TST C L OUT 0.4V 0.8V AI0822 C L = 30pF for High Speed C L = 00pF for Standard C L includes JIG capacitance AI0823B Table 6. Capacitance () (T A =25 C,f=MHz) Symbol Parameter Test Condition Min Max Unit C Input Capacitance (except BYTV PP ) V IN =0V 0 pf IN Input Capacitance (BYTV PP ) V IN =0V 20 pf C OUT Output Capacitance V OUT =0V 2 pf Note:. Sampled only, not 00% tested. DVIC OPRATION The operating modes of the are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for V PP and 2V on A9 for the lectronic Signature. Read Mode The has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTV PP pin. When BYTV PP is at V IH the Word-wide organisation is selected and the Q5A pin is used for Q5 Data Output. When the BYTV PP pin is at V IL the Byte-wide organisation is selected and the Q5A pin is used for the Address Input A. When the memory is logically regarded as 6 bit wide, but read in the Byte-wide organisation, then with A at V IL the lower 8 bits of the 6 bit data are selected and with A at V IH the upper 8 bits of the 6 bit data are selected. The has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Byte- wide organisation must be selected. Chip nable () is the power control and should be used for device selection. Output nable (G)isthe output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the address access time (t AVQV ) is equal to the delay from to output (t LQV ). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that has been low and the addresses have been stable for at least t AVQV -t GLQV.

5 Table 7. Read Mode DC Characteristics () (T A =0to70 Cor 40to85 C;V CC = 5V ± 5% or 5V ± 0%; V PP =V CC ) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC ± µa I LO Output Leakage Current 0V V OUT V CC ±0 µa I CC Supply Current =V IL,G=V IL, I OUT = 0mA, f = 8MHz =V IL,G=V IL, I OUT = 0mA, f = 5MHz 70 ma 50 ma I CC Supply Current (Standby) TTL =V IH ma I CC2 Supply Current (Standby) CMOS >V CC 0.2V 00 µa I PP Program Current V PP =V CC 0 µa V IL Input Low Voltage V V IH (2) Input High Voltage 2 V CC + V V OL Output Low Voltage I OL = 2.mA 0.4 V V OH Output High Voltage TTL I OH = 400µA 2.4 V Note:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is V CC +0.5V. Standby Mode The has a standby mode which reduces the active current from 50mA to 00µA. The is placed in the standby mode by applying a CMOS high signal to the input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control Because PROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the RAD line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations The power switching characteristics of Advanced CMOS PROMs require careful decoupling of the supplies to the devices. The supply current I CC has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device outputs. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.µF ceramic capacitor is used on every device between V CC and V SS. This should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. In addition, a 4.7µF electrolytic capacitor should be used between V CC and V SS for every eight devices. This capacitor should be mounted near the power supply connection point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

6 Table 8. Read Mode AC Characteristics () (T A =0to70 Cor 40to85 C;V CC = 5V ± 5% or 5V ± 0%; V PP =V CC ) Symbol Alt Parameter Test Condition t AVQV t ACC Address Valid to Output Valid t BHQV t ST BYT High to Output Valid t LQV t C Chip nable Low to Output Valid t GLQV t O Output nable Low to Output Valid t BLQZ (2) t STD BYT Low to Output Hi-Z t HQZ (2) t DF Chip nable High to Output Hi-Z t GHQZ (2) t DF Output nable High to OutputHi-Z t AXQX t OH Address Transition to Output Transition t BLQX t OH BYT Low to Output Transition -50 (3) -70 (3) Min Max Min Max Note:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Sampled only, not 00% tested. 3. Speed obtained with High Speed AC measurement conditions. Unit =V IL,G=V IL ns =V IL,G=V IL ns G =V IL ns =V IL ns =V IL,G=V IL ns G =V IL ns =V IL ns =V IL,G=V IL 5 5 ns =V IL,G=V IL 5 5 ns

7 Table 9. Read Mode AC Characteristics () (T A =0to70 Cor 40to85 C;V CC = 5V ± 5% or 5V ± 0%; V PP =V CC ) Symbol Alt Parameter Test Condition /-50 Min Max Min Max Min Max Unit t AVQV t ACC Address Valid to Output Valid t BHQV t ST BYT High to Output Valid t LQV t C Chip nable Low to Output Valid t GLQV t O Output nable Low to Output Valid t BLQZ (2) t STD BYT Low to Output Hi-Z t HQZ (2) t DF Chip nable High to Output Hi-Z t GHQZ (2) t DF Output nable High to OutputHi-Z t AXQX t OH Address Transition to Output Transition t BLQX t OH BYT Low to Output Transition =V IL,G=V IL ns =V IL,G=V IL ns G =V IL ns =V IL ns =V IL,G=V IL ns G =V IL ns =V IL ns =V IL,G=V IL ns =V IL,G=V IL ns Note:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Sampled only, not 00% tested. 3. Speed obtained with High Speed AC measurement conditions. Figure 7. Word-Wide Read Mode AC Waveforms A0-A9 VALID VALID tavqv taxqx tglqv thqz G Q0-Q5 tlqv tghqz Hi-Z AI0074B Note: BYTV PP =V IH.

8 Figure 8. Byte-Wide Read Mode AC Waveforms A,A0-A9 VALID VALID tavqv taxqx tglqv thqz G Q0-Q7 tlqv tghqz Hi-Z AI00742B Note: BYTV PP =V IL. Figure 9. BYT Transition AC Waveforms A0-A9 VALID A VALID tavqv taxqx BYTV PP tbhqv Q0-Q7 DATA OUT Q8-Q5 tblqx Hi-Z DATA OUT tblqz AI00743C Note: Chip nable () and Output nable (G) =V IL.

9 Table 0. Programming Mode DC Characteristics () (T A =25 C;V CC = 6.25V ± 0.25V; V PP = 2.5V ± 0.25V) Note:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0 V IN V CC ± µa I CC Supply Current 50 ma I PP Program Current =V IL 50 ma V IL Input Low Voltage V V IH Input High Voltage 2.4 V CC +0.5 V V OL Output Low Voltage I OL = 2.mA 0.4 V V OH Output High Voltage TTL I OH = 2.5mA 3.5 V V ID A9 Voltage V Table. Programming Mode AC Characteristics () (T A =25 C;V CC = 6.25V ± 0.25V; V PP = 2.5V ± 0.25V) Symbol Alt Parameter Test Condition Min Max Unit t AVL t AS Address Valid to Chip nable Low 2 µs t QVL t DS Input Valid to Chip nable Low 2 µs t VPHAV t VPS V PP High to Address Valid 2 µs t VCHAV t VCS V CC High to Address Valid 2 µs t LH t PW Chip nable Program Pulse Width µs t HQX t DH Chip nable High to Input Transition 2 µs t QXGL t OS Input Transition to Output nable Low 2 µs t GLQV t O Output nable Low to Output Valid 20 ns t GHQZ (2) t DFP Output nable High to Output Hi-Z 0 30 ns t GHAX t AH Output nable High to Address Transition 0 ns Note:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Sampled only, not 00% tested. Programming When delivered (and after each erasure for UV PROM), all bits of the are in the '' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both ''s and '0's can be present in the data word. The only way to change a '0' to a '' is by die exposure to ultraviolet light (UV PROM). The is in the programming mode when V PP input is at 2.5V, G is at V IH and is pulsed to V IL.Thedatatobeprogrammed is applied to 6 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. V CC is specified to be 6.25V ± 0.25V.

10 Figure 0. Programming and Verify Modes AC Waveforms A0-A9 VALID tavl Q0-Q5 DATA IN DATA OUT tqvl thqx BYTV PP tvphav tglqv tghqz V CC tvchav tghax tlh tqxgl G PROGRAM VRIFY AI00744 Figure. Programming Flowchart NO YS ++n = 25 FAIL V CC = 6.25V, V PP = 2.5V NO n = 0 = 50µs Pulse VRIFY Last Addr YS YS NO CHCK ALL WORDS BYTV PP =V IH st: V CC = 6V 2nd: V CC = 4.2V ++ Addr AI0044B PRSTO III Programming Algorithm The PRSTO III Programming Algorithm allows the whole array to be programed with a guaranteed margin in a typical time of 52.5 seconds. Programming with PRSTO III consists of applying a sequence of 50µs program pulses to each word until a correct verify occurs (see Figure ). During programing and verify operation a MARGIN MOD circuit is automatically activated to guarantee that each cell is programed with enough margin. No overprogram pulse is applied since the verify in MARGIN MOD provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple s in parallel with different data is also easily accomplished. xcept for, all like inputs including G of the parallel may be common. A TTL low level pulse applied to a 's input and V PP at 2.5V, will program that. A high level input inhibits the other s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with at V IH and G at V IL,V PP at 2.5V and V CC at 6.25V.

11 lectronic Signature The lectronic Signature (S) mode allows the reading out of a binary code from an PROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The S mode is functional in the 25 C ± 5 C ambient temperature range that is required when programming the. To activate the S mode, the programming equipment must force.5v to 2.5V on address line A9 of the, with V PP =V CC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V IL to V IH.All other address lines must be held at V IL during lectronic Signature mode. Byte 0 (A0 = V IL ) represents the manufacturer code and byte (A0 = V IH ) the device identifier code. For the ST- Microelectronics, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. RASUR OPRATION (applies to UV PROM) The erasure characteristics of the is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical in about 3 years, while it would take approximately week to cause erasure when exposed to direct sunlight. If the is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the window to prevent unintentional erasure. The recommended erasure procedure for is exposure to short wave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm 2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 2000 µw/cm 2 power rating. The should be placed within 2.5cm ( inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.

12 Table 2. Ordering Information Scheme xample: -70 X M TR Device Type M27 Supply Voltage C=5V Device Function 60 = 6 Mbit (2mb x 8 or Mb x 6) Speed -50 () =50ns -70 () =70ns -90 = 90 ns -00 = 00 ns -20 = 20 ns -50 = 50 ns V CC Tolerance blank = ± 0% X=±5% Package F = FDIP42W B = PDIP42 S = SDIP42 K = PLCC44 M = SO44 Temperature Range = 0 to 70 C 6 = 40 to 85 C Options TR = Tape & Reel Packing Note:. High Speed, see AC Characteristics section for further information. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

13 Table 3. Revision History Date Version Revision Details January First Issue 20-Sep AN620 Reference removed 9-Jul-0-03 SDIP42 package added 7-Jan ns speed class added, SO44 package mechanical data and drawing clarified

14 Table 4. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data Symbol mm inches Typ Min Max Typ Min Max A A A A B B C D D e ea eb L S K K α 4 4 N Figure 2. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline A2 A3 A A B B e D2 L α ea eb C D S N K K FDIPW-b Drawing is not to scale.

15 Table 5. PDIP42-42 pin Plastic Dual In Line, 600 mils width, Package Mechanical Data Symbol mm inches Typ Min Max Typ Min Max A A A B B C D D e ea eb L S α N Figure 3. PDIP42-42 pin Plastic Dual In Line, 600 mils width, Package Outline A2 A A B B e D2 L α ea eb C S D N PDIP Drawing is not to scale.

16 Table 6. SDIP42-42 pin Shrink Plastic DIP, 600 mils width, Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A A A b b c D e ea eb L S N Figure 4. SDIP42-42 pin Shrink Plastic DIP, 600 mils width, Package Outline A2 A b2 b e D2 A L ea eb c S D N SDIP Drawing is not to scale.

17 Table 7. PLCC44-44 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol mm inches Typ Min Max Typ Min Max A A A B B D D D e F R N CP Figure 5. PLCC44-44 lead Plastic Leaded Chip Carrier, Package Outline D D A2 A N B Ne F 0.5 (.020) D2/2 B e.4 (.045) Nd A PLCC R CP Drawing is not to scale.

18 Table 8. SO44-44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A A A b C CP D e H L N α 8 8 Figure 6. SO44-44 lead Plastic Small Outline, 525 mils body width, Package Outline A2 A C b e CP D N H A α L SO-d Drawing is not to scale.

E M27C Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM

E M27C Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM 6 Mbit (2Mb x 8 or Mb x 6) UV PROM and OTP PROM 5V ± 0% SUPPLY VOLTAG in RAD OPRATION ACCSS TIM: 70ns BYT-WID or WORD-WID CONFIGURABL 6 Mbit MASK ROM RPLACMNT LOW POWR CONSUMPTION Active Current 70mA at