APPLYING A SEAMLESS DESIGN FLOW TO. Aachen University of Technology. Germany. Abstract - Short product cycles and the necessity toachieve a short

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1 APPLYING A SEAMLESS DESIGN FLOW TO FAST DEVELOPMENT OF A CARRIER SYNCHRONIZER FOR MPSK M. Vaupel and H. Meyr Chair for Integrated Systems of Signal Processing Aachen University of Technology Aachen Germany vaupel@ert.rwth-aachen.de Abstract - Short product cycles and the necessity toachieve a short time to market call for sophisticated design methodologies. In this paper a seamless design ow is described enabling the design of engineering a chip for carrier synchronization of 8PSK, QPSK and BPSK modulated signals in three months. The circuit was fabricated in a 1mCMOS process using standard cells and is currently in commercial use in a modem for digital TV transmission. INTRODUCTION The demand for short product cycles in the eld of VLSI-design is continuously increasing. Time to market or rapid prototyping are hot topics. These demands call not only for skilled designers but require also design methodologies which support the development of digital integrated circuits. The design ow ranges from system level specication and simulation down to post layout simulation or even post production testing. An integral part of this ow are the verication steps. Phase shift keying (PSK) is a commonly used modulation technique for the transmission of digital data. Due to local oscillator inaccuracies of the receiver{transmitter pair, the complex valued signal suers from a frequency oset and a phase drift. In order to overcome these eects a correction device is needed which should be able to cope with dierent modulation schemes (8PSK, QPSK and BPSK) to be applicable in various environments. Additionally the functional parameters should be programmable to ensure the required exibility. THE CIRCUIT Figure 1 shows the receiver branch of the whole modem for digital TV transmission. After analog down conversion the signal is sampled. In phase and quadrature components are input to a matched lter, that is part of

2 the timing synchronization loop. The output signal is fed into the carrier synchronizer. The corrected signal values are input to a channel decoder (eg a Viterbi decoder). As an alternative, the matched lter could also be used inside the synchronization loop (see Figure 1). Timing Synchronization M.F. Viterbi I/Q ADC M.F. * * * * Phase and Frequency Synchronization Figure 1: Receiver chain of the modem * * * * The internal structure of the synchronizer is basically a digital PLL [1,2] and is depicted in Figure 2. It consists of phase rotator, phase error detector, loop lter, and NCO mainly. Additionally a sweep generator is implemented that allows an automated search of the frequency oset to be performed within a wide range during acquisition. This search is controlled by a lock detection unit that detects whether the received data is located within a certain range around a reference point in the complex plane or not. This in{ range information is processed within the count{and{compare unit which puts out a loop{in{lock bit. Furthermore a microprocessor interface ensures the necessary exibility of congurations and allows observation of internal states and signals. Additionally, a frequency measurement unit is implemented to support the coarse adjustment of the oscillator. Phase Rotator Phase Error and Lock Detection Frequency Measurement NCO Loop Filter phase error Sweep Generator lock bit Count & Compare up- Interface Figure 2: Structure of the Synchronizer The maximum specied sample rate was 35 MHz. The correctable frequency error should be up to +/{ 12.5% (8PSK) of the sample rate. The normalized loop bandwidth B L can be programmed to be in the range of 10 ;4 to 10 ;2 of the sampling rate the damping ratio can be chosen between 0.7 and 1.5.

3 DESIGN FLOW The integration of telecommunication systems on silicon is a process that requires modeling on dierent abstraction levels[3]. For each level suitable simulation paradigms have to be applied in order to evaluate the performance with the help of criteria that are adequate on this particular level. (See Figure 3). Of course designing an integrated circuit is not a pure top{down process. Each renement step gives a feedback to upper levels. For instance, the cost in silicon area has an impact on the decision on quantization parameters. The delay that is introduced into the synchronizer loop due to pipelining the building blocks has an inuence on the system performance. This stresses the importance of a smooth transition between system and architectural level. In addition each shift from an upper abstraction level to a lower one requires a verication between the two dierent representations of the same block. Implementation Selection and Development of Algorithms Function Verification COSSAP System performance spec met? Development of Architectures for each block Logic Synthesis Place & Route Fabrication Algorithm Architecture (VHDL) Architecture (Gate Level) Physical Layout Co-Simulation Algorithmic model and structural description match? VHDL-Sim. Timing requirements met? STL/Verilog-Sim. Timing requirements met? Production Test Die function is according to test vectors? Hardware in the Simulation loop Chip function correct? ASIC Figure 3: Overview of Design Flow System level On the uppermost abstraction level all system performance related issues (eg BER or remaining phase inaccuracies) have to be investigated. For this reason the system environment (eg channel, source decoder) has to be modeled and simulated. The simulation eciency is a crucial point especially

4 for complex systems since long simulations are necessary in order to achieve accurate results. All information which is not relevant on this level has to be hidden in order to speed up simulations. Therefore a data ow driven simulation engine is the appropriate choice[4]. In our case the system level simulation tool was COSSAP[5]. In order to decide on quantization of internal signals and pave the way down to implementation, a bittrue specication of all blocks of the circuit had to be created. Structural levels For each building block, a corresponding VLSI{architecture was developed and described in VHDL. That comprises of eg directly implementing the arithmetic units (eg the within loop lter) with some improvements that increase implementation eciency or of building architectures that are structurally dierent but show identical behavior at the borders of the entity compared with the functional description of the block. 1) 3) 2) phase difference in_lock area Figure 4: Mapping of address values The phase rotator is realized as a CORDIC{processor[6,7,8]. The loop lter is a rst order lter, that is pipelined in order to reach the specied data rate. Phase error detector and lock detection unit are implemented once for each modulation scheme. The phase detection algorithm used for 8PSK modulated signals was described in [9]. Its implementation was done via a synthesized table, because of the increased eciency compared to using arithmetic units or ROMs. In order to reduce the required silicon real estate, the implicit symmetry of the phase error detection was advantageously taken into account: in a rst step all quadrants are mapped onto the rst one 1) (see Figure 4), then the second octand is mapped onto the rst 2), and nally the upper remaining triangle is mapped onto the free address space in the lower half of the rst quadrant 3). Each mirroring operation in the

5 address space is compensated for by aninversion of the output phase value. Following this approach, the address space of the table could be decreased by a factor of eight at the expense of implementing a preprocessing unit that performes the mapping and a post processing unit for conditionally inverting the phase values. The values of the synthesized table were obtained using the functional simulation model of the Viterbi{and{Viterbi [9] algorithm and the postprocessing facilities of the simulation environment. Another possible structure of the receiver is to use the matched lter with subsequent decimation within the frequency synchronizer loop (see gure 1). The input data of the phase error estimator is then read from outside the chip rather than from the CORDIC{processor. Due to the dierent data rates (CORDIC{processor and NCO are processing the oversampled data, the other parts of the loop are working with the decimated values), decoupling of the CORDIC{processor and the rest of the loop is necessary which was implemented using enable signals. Verication VHDL Verication. An crucial step in the design ow is the verication of the VHDL descriptions against their counterparts, the functional system level specications. For this reason a simulator coupling between COSSAP and the SYNOPSYS VSS VHDL simulator was developed at our site [10,11]. For each VHDL entity an interface block is generated automatically that can replace the respective simulation model in a COSSAP netlist. Via this block the simulation data of the system level simulation run is fed into the VHDL simulation that is running simultaneously. The output data is compared on the functional level enabling the use of graphical postprocessing facilities. This approach avoids developing VHDL testbenches for each building block, producing input stimuli within the test bench or writing input stimuli of the functional model to les and reading these into the VHDL simulation, and comparing the produced output les which would be a very tedious, error{ prone and time consuming process. Therefore, debugging is greatly simplied using the cosimulation approach. The granularity of the modeled blocks has to be ne enough to ensure controllability and observability with a limited number of input datasets and to ease the debugging process, and coarse enough to obtain a high verication eciency. After design and verication of all building blocks the overall system has to be veried using the same approach described above. Post Layout Simulation. The verication step that follows placement and routing is aided by generating input stimuli and expected output data for post layout simulation using the system level simulation setup again. It is very easy to use the available source models to produce large sets of complex data patterns in order to drive the internal states to all possible values. The generation of Production Test vectors is done using the same approach.

6 phase error frequency stored in loop NCO output Figure 5: Measured internal data Functional Chip Verication. The manufactured chip was functionally tested using a hardware{in{the{simulation{loop environment[12]. Via a software interface module the input data which is produced by the simulator under simulated environmental conditions (eg a specic type of channel) is fed into the real hardware. The on{chip processed results are then read back and can be compared with the simulation model and visualized using the graphical output facilities of the simulation tool. In the case of the synchronizer chip the micro{processor interface that is needed for conguring the chip allows additionally an observation of internal states and signals. For instance, estimated phase error, output of NCO, and the frequency stored in the loop lter can be read out without increasing the pin count. Figure 5 summarizes some measured results that are read out during acquisition. The uppermost curve shows the detected phase error, the middle the frequency that is stored in the loop lter, and the lower displays the NCO output. During the rst 2000 clock cycles, a positive sweep value is added into the loop. After reaching the programmed limit, the output of the sweep generator is inverted in order search into negative direction. When a loop{in{lock is detected (a certain amount of received signal points are near the reference points in the

7 complex plane) the output of the sweep generator is disabled. The circuit is now in tracking mode and follows slowly varying frequencies. Problems The remaining bottleneck of the design ow was in our case the loose coupling between synthesis and placement and routing. The large number of simple logic gates and the non{local connections inside the synthesized table caused a large amount of wiring in this region (see Figure 6). Due to the fact that wireload models used in SYNOPSYS are not accurate enough with respect to the actual wiring capacitances, the pre{ and post{layout timing estimates diered by up to 33% resulting in serious timing violations that had to be removed by numerous try{and{error iterations. Figure 6: Final Layout

8 RESULTS The chip was manufactured in a 1m CMOS process and consists of 5964 standard cells. The chip area is 27 mm 2. Itispackaged into a 68 pin ceramic pin grid array package. The maximum sample rate under worst case conditions is 35 MHz. No self test is implemented, the fault coverage using the generated 32k test vectors is 89%. Figure 6 shows the nal layoutofthe chip. SUMMARY An integrated design ow that ranges from system level specication and simulation down to post layout simulation or even post production testing avoids implementation failures that result from verication gaps between different levels of abstraction and ensures short design times. It guarantees a close interaction between system level and hardware design providing a well dened interface. This enables concurrent engineering on dierent levels and of dierent structural blocks as well. With the help of the design environment described above it was possible to produce the nal physical layout within three months. The chip is fully functional and was a rst silicon success. A natural extension of the methodology is to enable reusing the developed pairs of functional and architectural parameterizable modules in order to improve the design process even further. Currently a tool set[13,14] is under development at our site which provides an automated VHDL generation from the functional specications. References [1] H. Meyr and G. Ascheid, Synchronization in Digital Communications, vol. 1. John Wiley & Sons, [2] E. A. Lee and D. G. Messerschmitt, Digital Communications. Kluwer Academic Publishers, [3] K. ten Hagen, Abstrakte Modellierung digitaler Schaltungen (VHDL vom funktionalen Modell bis zur Gatterebene). Heidelberg New York: Springer, August In Vorbereitung. [4] G. Jennings, \A case against event driven simulation of digital system design," in The 24th Annual Simulation Symposium (A. H. Rutan, ed.), (Los Alamitos, California), pp. 170{176, IEEE Computer Society Press, April [5] Synopsys, Inc., 700 E. Middleeld Rd., Mountain View, CA 94043, USA, COSSAP User's Manual. [6] J. E. Volder, \The CORDIC trigonometric computing technique," IRE Trans. Electronic Computing, vol. EC{8, pp. 330{34, September 1959.

9 [7] J. S. Walther, \A unied algorithm for elementary functions," in AFIPS Spring Joint Computer Conference, vol. 38, pp. 379{85, [8] H. Dawid and H. Meyr, \The Dierential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without correcting Iterations." accepted for IEEE Transactions on Computers, May, [9] A. J. Viterbi and A. M. Viterbi, \Nonlinear estimation of psk-modulated carrier phase with application to burst digtal transmission," IEEE Transactions on Information Theory, vol. IT-29, pp. 543{551, July [10] P. Zepter, \Simulator Coupling: COSSAP - Synopsys VSS," Internal Memo 715/16, ISS, RWTH Aachen, September [11] P. Zepter, \Kopplung eines VHDL Simulators an einen Simulator fur Signalverarbeitungsalgorithmen," in GME Fachberichte 11 Mikroelektronik (D. Seitzer, ed.), pp. 127{132, VDE Verlag, March in german. [12] O. J. Joeressen and H. Meyr, \Hardware \in the loop" simulation with COSSAP: Closing the verication gap," in International Conference on DSP Applications and Technology, (Dallas, TX), pp. 779{784, DSP Associates, October [13] H. Meyr, H. Dawid, O. Joeressen, and P. Zepter, \Design of High Speed Communication Systems," in Proceedings of the IEEE International Symposium on Circuits and Systems, (London), p , IEEE, May [14] P. Zepter, T. Grotker, O. Joeressen, and H. Meyr, \A design system for high throughput digital signal processing," in GME Fachberichte 13 Mikroelektronik (E. Barke, ed.), VDE Verlag, March 1995.