Spread-Spectrum Technique in Sigma-Delta Modulators

Transcription

1 Spread-Spectrum Technique in Sigma-Delta Modulators by Eric C. Moule Submitted in Partial Fulillment o the Requirements or the Degree Doctor o Philosophy Supervised by Proessor Zeljko Ignjatovic Department o Electrical and Computer Engineering The College School o Engineering and Applied Sciences University o Rochester Rochester, New York 008

2 ii Curriculum Vitae The author was born in Medina, NY on August 6 th, 980. He came to the University o Rochester in the all o 998 to begin his undergraduate studies and has since graduated with the Bachelor o Science degree with high distinction in 00. He continued his education with graduate studies at the University o Rochester upon completion o his undergraduate studies. He pursued his research interests in analog integrated circuit design and signal processing under the direction o Proessor Zeljko Ignjatovic and received the Master o Science degree rom the University o Rochester in 003. His particular research interests lie in the areas o sigma-delta modulation analog-to-digital conversion and signal processing implementations.

3 iii Acknowledgments Several people deserve special acknowledgment and recognition or their part in making this work possible. First and oremost, I would like to thank my advisor, Zeljko Ignjatovic, or selecting me as his irst oicial graduate student here at the University o Rochester. Your knowledge and guidance seem endless, and I cannot thank you enough or investing your time and eort into my education. In addition, I would like to thank my ormer graduate advisor, Mark Bocko, or his advice and guidance as I decided on my course o research. In addition, I must also give my thanks and appreciation to the Oice o Naval Research. The inancial support granted by your oice (under contract N ) provided the means to continue researching this exciting topic. I would also like to thank all o my colleagues in Proessor Ignjatovic s TESLA research group. The discussions and assistance you have all provided will not be orgotten. In particular, I wish to thank Yu Song or his assistance in coding and debugging, PCB layout, and measurement results that directly led to portions o the work presented in this thesis. Last, but certainly not least, I would like to thank all o my amily and riends whose encouragement throughout my studies has been a necessary driving orce. To my amily, your encouragement and support as I pursued my educational goals may have gone without suicient gratitude on my part; however, I can assure you it has

4 iv never been under-appreciated. To all o my riends, I would be remiss i I did not thank you all or helping me receive a steady dose o un and entertainment outside o my educational experiences. To everyone else who has supported me in my educational pursuits, thank you or your assistance and thoughtulness. Although you have gone nameless here, your contributions along the way will always be with me.

5 v Abstract The application o spread-spectrum techniques to sigma-delta (Σ ) modulators as a method to reduce the eects o integrated circuit nonidealities is investigated in this work. The research primarily ocuses on reducing the eects o DC oset, licker noise, nonlinear ampliier DC gain, DAC and power supply noise, and substrate noise. The proposed design may prove beneicial in Power-over- Ethernet (IEEE 80.3) or other AC powered applications and vibration powerscavenging applications where the power supply and substrate noise may still exhibit strong spectral tones aecting the modulator s perormance. In addition, the insensitivity o the proposed design to process variations and circuit nonidealities such as low requency noise and DC oset makes it suitable or high-resolution ADC applications in more advanced CMOS technologies. A step-by-step design methodology or transorming a conventional Σ modulator into a spread-spectrum Σ modulator is described. To illustrate this process, the design o a third-order -bit spread-spectrum Σ modulator is shown in detail. Additionally, the requirements or a particular spread-spectrum sequence are described with respect to the expected noise perormance o the Σ modulator. An experimental prototype third-order -bit ully-dierential spreadspectrum Σ modulator is implemented using the TSMC -poly/4-metal 0.35µm CMOS process. The spread-spectrum sequence utilized or the measurements is a

6 vi second-order blue noise sequence that was synthesized on an Altera FPGA. The prototype is clocked at 00kHz and digitizes a 500Hz bandwidth signal with 94dB o dynamic range. Additionally, the prototype achieves SNR and SNDR measurements o 85.dB and 8.7dB, respectively. The spread-spectrum technique in Σ modulation also is explored or bandpass Σ modulators. Speciically, a two-path bandpass Σ modulator utilizing a spread-spectrum capacitor randomization scheme within the resonator structure and a bandpass Σ modulator employing modulation with a band-stop spread-spectrum sequence are described. Both methods are shown to be eective at spreading in-band spectral intererers to make them appear as wideband noise. We also apply spread-spectrum techniques to Nyquist rate analog-to-digital converters. A time-interleaved Nyquist-rate analog-to-digital converter employing spread-spectrum channel ADC selection is shown to eectively randomize the individual channel ADC mismatches such as gain, oset, and licker noise, thereby improving the ADC s perormance.

7 vii Table o Contents Curriculum Vitae... ii Acknowledgments... iii Abstract... v Table o Contents... vii List o Tables... xi List o Figures... xiii Chapter Introduction. Thesis Organization... 4 Chapter Analog-to-Digital Conversion 6. Nyquist Rate Analog-to-Digital Conversion Sampling Quantization Oversampling Analog-to-Digital Conversion Sigma-Delta Analog-to-Digital Conversion Lowpass Sigma-Delta Analog-to-Digital Conversion... 6

8 viii.3. Bandpass Sigma-Delta Analog-to-Digital Conversion... 3 Chapter 3 Spread-Spectrum in Communications Systems 7 3. Spread-Spectrum Technique in Communications Systems Frequency-Hopping Spread-Spectrum Direct Sequence Spread-Spectrum... 9 Chapter 4 Spread-Spectrum Σ Modulator Design Methodology 3 4. Sigma-Delta Modulator Design Procedure High-Level Third-Order Σ Modulator Design High-Level to Signal Flow-Graph Σ Modulator Design Spread-Spectrum Σ Modulator DAC Reerence Voltage Noise Substrate Noise Nonlinear Ampliier Gain Spread-Spectrum Σ Modulator Design Chapter 5 Spread-Spectrum Sequence Considerations and Simulation Results Spreading Sequence Considerations Eect o Spread-Spectrum Modulation on Flicker Noise Eect o Spread-Spectrum Modulation on Spectral Intererer Eect o Spread-Spectrum Modulation on DC Oset Determining the Required Spread-Spectrum Sequence Blue Noise Generation Blue Noise Generator Implementation Third-Order Spread-Spectrum Σ Modulator Simulation Results... 89

9 ix Chapter 6 Experimental Results Implementation Operational Transconductance Ampliier Comparator Switches and Switch Noise Prototype Layout Experimental Test Setup Measured Perormance SNR and SNDR Substrate Noise Feedback DAC Noise Perormance Summary... Chapter 7 Bandpass Σ ADC Designs Utilizing Spread- Spectrum Techniques 7. Bandpass Σ Modulator Utilizing 3-Path Resonator Structures Mirror Image Generation Mechanism and Theory Modulator Operation Modulator Design Simulation Results Bandpass Σ Modulator Utilizing Spread-Spectrum Path Selection Capacitor Path Spread-Spectrum Randomization Modulator Operation Simulation Results Band-Stop Noise Modulated Bandpass Σ Modulator Resonator Topologies Band-Stop Noise Sequence Generation Simulation Results... 46

10 x Chapter 8 Extending Spread-Spectrum Techniques to Nyquist Rate ADCs Spread-Spectrum Randomized Time-Interleaved ADC Channel Mismatch and / Noise Eects Spread-Spectrum Channel Randomization Method Time-Interleaved ADC with Spread-Spectrum Modulators Simulation Results Chapter 9 Conclusion Summary Topics or Continued Research Substrate Noise Reduction Experimental Veriication Multi-Bit Spread-Spectrum Σ Modulator Spread-Spectrum Cascaded Σ Modulator Reerences... 65

11 xi List o Tables Table 4-: Table 4-: Maximum out-o-band gain results when using various Wn cuto requency values in the Matlab unction butter... 4 Coeicient values or use in the Σ modulator shown in Figure Table 4-3: Maximum integrator output values... 4 Table 4-4: Table 4-5: Table 4-6: Table 4-7: Dynamic range scaled coeicients or the Σ modulator shown in Figure Rounded, dynamic range scaled coeicients or the Σ modulator loop topology shown in Figure Pole and zero locations or the Σ modulator using the rounded, dynamic range scaled coeicients Simulation parameters used or the Matlab/Simulink veriication O the Σ modulator Table 4-8: Relationship between the capacitors and coeicient values... 5 Table 4-9: Coeicient values corresponding to Eq. (4-6) Table 5-: Coeicient values or all-digital N th -order Σ modulator Table 6-: Folded-cascode OTA perormance measured results Table 6-: Transmission gate transistor sizings Table 6-3: Capacitor values or the third-order -bit spread-spectrum Σ modulator... 0

12 xii Table 6-4: Table 7-: Table 7-: Spread-spectrum Σ modulator prototype chip perormance summary... Simulation parameters or the pseudo-two-path ourth-order bandpass Σ modulator example Comparison o SFDR and SNDR or various two-path bandpass Σ modulator designs in the presence o an intererer at in /

13 xiii List o Figures Figure -: Sampling process model... 8 Figure -: Frequency domain depiction o sampling... 8 Figure -3: Quantizer model... 9 Figure -4: Quantization error probability density unction distribution... 0 Figure -5: Quantized signal spectrum... Figure -6: Frequency domain depiction o oversampling... 3 Figure -7: Power spectral density o quantization noise or Nyquist and oversampling... 4 Figure -8: Oversampling ADC model... 5 Figure -9: First-order Σ ADC... 7 Figure -0: NTFs o the PCM oversampled system and the st -order Σ modulator... 8 Figure -: Second-order Σ modulator... 9 Figure -: NTFs o the PCM oversampled system, st -order Σ modulator, and nd -order Σ modulator... 0 Figure -3: L th -order Σ modulator... Figure -4: RF communications receiver employing a bandpass (BP) Σ modulator... 4 Figure -5: Pole-zero diagram or the lowpass (a) and bandpass (b) Σ modulators used in the lowpass-to-bandpass transormation example... 5

14 xiv Figure -6: Magnitude response or the lowpass (a) and bandpass (b) Σ modulators used in the lowpass-to-bandpass transormation example... 6 Figure 3-: Frequency-Hopping Spread-Spectrum communication system... 9 Figure 3-: Direct Sequence Spread-Spectrum communication system Figure 4-: Chain o integrators with weighted eedback summation loop topology Figure 4-: Chain o integrators with weighted eedorward summation loop topology Figure 4-3: Chain o integrators with weighted eedback and eedorward summation loop topology Figure 4-4: Chain o integrators with eedorward summation and local resonator eedbacks loop topology Figure 4-5: Chain o integrators with distributed eedback, distributed eedorward, and local resonator eedbacks loop topology Figure 4-6: Chain o integrators with weighted eedback loop topology chosen or the Σ modulator design Figure 4-7: Pole-zero plot displaying pole and zero locations or the Σ modulator using the rounded, dynamic range scaled coeicients Figure 4-8: Frequency response o the NTF and STF across the entire bandwidth Figure 4-9: Frequency response o the NTF and STF across the assumed input signal bandwidth Figure 4-0: Simulation result o the designed Σ modulator across the entire bandwidth Figure 4-: Simulation result o the designed Σ modulator across the assumed signal bandwidth Figure 4-: High-level Σ modulator block diagram Figure 4-3: Circuit schematic and signal low-graph o the delay-ree integrator Figure 4-4: Circuit schematic and signal low-graph o the sample-delayed integrator Figure 4-5: Block diagram o the Σ modulator ater the delay element has been relocated... 5 Figure 4-6: Block diagram o the Σ modulator ater the eedback path is represented by voltage nodes... 5

15 xv Figure 4-7: Signal low-graph representation o the Σ modulator... 5 Figure 4-8: Capacitive coupling mechanisms or substrate noise Figure 4-9: Ampliier DC gain as a unction o ampliier output voltage Figure 4-0: Integrator block diagram used in Simulink to implement the nonlinearities Figure 4-: Insertion o spread-spectrum multiplier pairs into the third-order Σ modulator... 6 Figure 4-: Initial step toward producing the spread-spectrum Σ modulator. The spread-spectrum multiplier pairs are moved according to the dashed arrows... 6 Figure 4-3: Intermediate step toward producing the spread-spectrum Σ modulator. The spread-spectrum multiplier pairs continue to be rearranged according to the dashed arrows... 6 Figure 4-4: Third-order -bit spread-spectrum Σ modulator. The delayree and sample-delayed spread-spectrum modulated (SSM) integrator structures are introduced Figure 4-5: Delay-ree mirrored integrator structure employed or implementing the delay-ree SSM integrator Figure 4-6: Sample-delayed mirrored integrator structure employed or implementing the sample-delayed SSM integrator Figure 4-7: Example clocking sequence or the delay-ree and sample-delayed SSM integrators Figure 4-8: Delay-ree SSM integrator model Figure 4-9: Sample-delayed SSM integrator model Figure 4-30: Third-order -bit spread-spectrum Σ modulator signal lowgraph Figure 4-3: Third-order -bit spread-spectrum Σ modulator circuit schematic Figure 5-: Figure 5-: Figure 5-3: Model used to calculate the eect o spread-spectrum modulation on licker noise... 7 PSDs or the white noise and irst- through third-order blue noise spread-spectrum sequences modulated with licker noise White noise and irst- through third-order blue noise modulated with licker noise plotted against the third-order Σ modulator output spectrum... 76

16 xvi Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: PSDs or the white noise and irst- through third-order blue noise spread-spectrum sequences modulating a 60Hz spectral intererer Spectral intererer modulated with white noise and irst- through third-order blue noise plotted against the third-order Σ modulator output PSDs or the white noise and irst- through third-order blue noise spread-spectrum sequences modulating DC oset... 8 DC oset modulated with white noise and irst- through third-order blue noise plotted against the third-order Σ modulator output Figure 5-8: Spread-spectrum sequence selection low graph Figure 5-9: N th -order -bit all-digital Σ modulator loop topology implemented Figure 5-0: Blue noise spectrum obtained rom the second-order all-digital Σ modulator implemented on Altera FPGA Figure 5-: Output spectrum o third-order Σ modulator where low-requency noise as well as the second and third harmonics o the input are visible... 9 Figure 5-: Output spectrum o third-order spread-spectrum Σ modulator where only the third harmonic o the input is visible... 9 Figure 5-3: Output spectrum o the third-order Σ modulator in the presence o DAC noise... 9 Figure 5-4: Output spectrum o the third-order spread-spectrum Σ modulator in the presence o DAC noise Figure 6-: Folded-cascode OTA schematic Figure 6-: Switched-capacitor common-mode eedback circuit Figure 6-3: Regenerative latched comparator schematic Figure 6-4: Figure 6-5: Figure 6-6: Simulated on-resistance o the CMOS switch as a unction o input voltage (a) Simpliied input sampling network, and (b) the circuit model For calculating the switch noise Chip photograph o the prototype spread-spectrum Σ modulator Figure 6-7: 50F unit capacitor layout Figure 6-8: Experimental test setup... 05

17 xvii Figure 6-9: Spread-spectrum Σ modulator prototype output spectrum with 00Hz 00mV peak-to-peak sinusoidal input signal Figure 6-0: Measured SNR and SNDR versus input signal amplitude Figure 6-: Output spectra o the conventional Σ modulator (top) and spreadspectrum modulator (bottom) with 60Hz DAC noise present... 0 Figure 7-: Figure 7-: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: (a) Input signal spectrum. (b) Two-path output spectrum. (c) Three-path output spectrum... 6 Proposed double-sampling pseudo-three-path bandpass ilter along with the operational clock sequence... 7 Double-sampling pseudo-three-path bandpass ilter during Clk clock phase... 9 Double-sampling pseudo-three-path bandpass ilter during Clk clock phase... 0 Double-sampling pseudo-three-path bandpass ilter during Clk3 clock phase... Typical output spectrum o three-path ourth-order bandpass Σ modulator with input requency in =.54MHz ( s = 0.MHz)... 6 Output spectrum detail o the two-path ourth-order Σ modulator with in =.54MHz... 6 Output spectrum detail o the three-path ourth-order Σ modulator with in =.54MHz... 7 Output spectrum o the two-path ourth-order Σ modulator with in =.54MHz and in /3 intererer... 7 Figure 7-0: Output spectrum detail o the two-path ourth-order Σ modulator with in =.54MHz and in /3 intererer... 8 Figure 7-: Output spectrum o the three-path ourth-order Σ modulator with in =.54MHz and in /3 intererer... 8 Figure 7-: Output spectrum detail o the three-path ourth-order Σ modulator with in =.54MHz and in /3 intererer... 9 Figure 7-3: Proposed double-sampling pseudo-two-path bandpass ilter utilizing spread-spectrum path selection... 3 Figure 7-4: Example clock sequence... 3 Figure 7-5: Output spectrum o pseudo-two-path ourth-order bandpass Σ modulator utilizing spread-spectrum path selection with in =.54MHz ( s = 0.MHz)... 36

18 xviii Figure 7-6: Detail o output spectrum o the traditional pseudo-two-path ourth-order Σ modulator with in =.54MHz Figure 7-7: Detail o output spectrum o the pseudo-two-path ourth-order Σ modulator utilizing spread-spectrum path selection with in =.54MHz Figure 7-8: Output spectrum o the pseudo-two-path ourth-order Σ modulator utilizing spread-spectrum randomized capacitor path selection with in =.54MHz and in /3 intererer Figure 7-9: Output spectrum detail o the pseudo-two-path ourth-order Σ modulator utilizing spread-spectrum randomized capacitor path selection with in =.54MHz and in /3 intererer Figure 7-0: Forward-Euler resonator... 4 Figure 7-: Band-stop noise Forward Euler resonator... 4 Figure 7-: Forward-Euler Non-Delayed resonator... 4 Figure 7-3: Band-stop noise Forward-Euler Non-Delayed resonator... 4 Figure 7-4: Lossless-Discrete Integrator... 4 Figure 7-5: Band-stop noise Lossless-Discrete Integrator Figure 7-6: Band-stop noise modulated bandpass Σ modulator Figure 7-7: Double-Delay resonator Figure 7-8: Single opamp ully dierential switched-capacitor band-stop noise modulated Double-Delay resonator and corresponding clock sequences Figure 7-9: Spectrum o the band-stop noise sequence Figure 7-30: Output spectrum o the proposed modulator design with an input signal requency o 0.7MHz, OSR o 07, and bandwidth o 00kHz Figure 7-3: Output spectrum detail o the traditional bandpass Σ modulator with Fs/4 intererer Figure 7-3: Output spectrum detail o the proposed band-stop noise modulated bandpass Σ modulator in the presence o a Fs/4 intererer Figure 8-: Figure 8-: Time-interleaved ADC utilizing spread-spectrum chopper multipliers Output spectrum o 4-path TI ADC utilizing periodic path selection... 57

19 xix Figure 8-3: Figure 8-4: Output spectrum o 4-path TI ADC utilizing spread-spectrum path selection Output spectrum o 4-path TI ADC utilizing spread-spectrum path selection and spread-spectrum chopper multipliers... 58

20 Chapter Introduction Increasing demand or small size, high perormance, low power, and low cost electronics products has ueled advancements in modern electronics design and manuacturing. These demands require an increasing level o electronic circuit integration. In recent years as the eature size o the abrication processes have reached submicron levels, the integration o several circuits and systems on a single chip has become commonplace. This integration is evident, or example, in the multi-mode receivers being implemented or various communications systems. The receivers are integrating low-noise ampliiers (LNAs), downconversion mixers, requency synthesizers, analog ilters, and analog-to-digital converters (ADCs) together on a single chip. However, continued circuit integration regularly places noise-sensitive analog blocks and noisy digital signal processing blocks together on a common substrate. The result o the large-scale integration is an increase in substrate noise and power supply noise alicting the analog circuitry. It should come as no surprise that ADCs, which require both analog and digital circuitry, are experiencing increased adverse eects rom substrate noise and power supply noise.

21 It is well known that sigma-delta (Σ ) ADCs are suitable or high resolution and low-to-moderate bandwidth applications. However, in current CMOS processes, where circuit nonidealities such as substrate noise and power supply noise are being introduced into the Σ modulator, dynamic range is sacriiced. As a result, new techniques or minimizing or eliminating these nonidealities are required in order or the Σ ADCs to operate at their highest resolution potential. Although this may be a new and growing problem among mixed-signal circuit designs, similar issues have existed or several decades in the communications industry and have been successully addressed. Speciically, methods or reducing the eects o channel intererence and multipath distortions, whose eects on the signal integrity are similar to substrate and power supply noise eects in mixed signal circuits, have existed since the 940s. The solution is generally classiied in communications systems as the spread-spectrum technique. The spread-spectrum technique in communications systems perorms a wideband spreading o the input signal beore it is transmitted over the noisy channel. The wideband spreading is perormed by modulating the input with a pseudo-random sequence that is independent o the signal and has much larger bandwidth. The wideband version o the signal is then transmitted over the channel to the receiver. The signal is despread at the receiver by correlating the received signal with the identical pseudo-random sequence used to spread the signal. As a result, the original input signal is recovered and the noises introduced into the wideband signal by the channel are spread as wideband noise that is readily iltered out by the receiver. This research applies the principles o the spread-spectrum technique to the Σ modulator. The input to the Σ modulator is spread by a pseudo-random spreading sequence beore being applied to the Σ modulator. The wideband version o the input signal is then processed by the Σ modulator, which introduces intererers such as substrate noise and power supply noise onto the wideband signal. The signal is then despread at the Σ modulator output by a synchronized version o

22 3 the pseudo-random spreading sequence. While the input signal to the Σ modulator is recovered, the intererers introduced by the nonideal Σ modulator circuitry become spread as wideband noise. The result is a reduced eect o nonidealities and spectral intererers on the Σ modulator. In addition to spreading substrate noise and power supply noise eects, spread-spectrum modulation also reduces the eects o ampliier and DAC non-idealities, including / noise, DC oset, nonlinear ampliier gain, and even-order nonlinearities. In this work, we introduce the design methodology or transorming a traditional Σ modulator into a spread-spectrum Σ modulator. In this approach, the redesign o several critical elements required or the switched-capacitor implementation o the spread-spectrum Σ modulator is described. In addition, a speciic example describing the design process or implementing a -bit third-order spread-spectrum Σ modulator is presented. We also discuss several options or the required spread-spectrum sequence, and the eects o spread-spectrum modulation on various circuit nonidealities are presented. An experimental prototype implementing a third-order -bit ully-dierential spread-spectrum Σ modulator has been implemented using a 0.35µm -poly/4-metal CMOS process. The spreadspectrum sequence utilized or the measurements is a second-order blue noise sequence that was synthesized on an external FPGA. The prototype is clocked at 00kHz and it is able to convert a 500Hz bandwidth signal with 94dB o dynamic range. In addition, the modulator dissipates 3.5mW o power rom a 5V supply. The spread-spectrum technique in Σ analog-to-digital conversion is not limited to the lowpass Σ modulator described above. We also present several bandpass Σ modulator designs in which the spread-spectrum technique has been employed. The bandpass modulator utilizing a spread-spectrum capacitor path randomization scheme within the individual resonator structure is shown to be eective at spreading the mirror image signal as well as out-o-band spectral intererers as a wideband noise. Additionally, a spread-spectrum bandpass Σ modulator employing modulation with a sequence with band-stop spectral properties

23 4 is described. The band-stop noise spread-spectrum modulation is implemented to reduce the eects o substrate noise on the bandpass Σ modulator. The methodology or designing the resonators and the overall band-stop noise modulated bandpass Σ modulator is presented and several resonator structures are described in detail. The inal topic discussed in this thesis is the extension o the spread-spectrum technique in analog-to-digital conversion systems to Nyquist rate ADCs. Nyquist rate time-interleaved (TI) ADCs utilize multiple path structures to achieve eicient conversion. However, mismatch between the individual paths introduce spectral intererence into the ADC output spectrum. As a means to reduce the eect o the spectral intererers, a time-interleaved Nyquist-rate ADC that utilizes a spreadspectrum sequence to select the channel ADC used or a particular conversion is described. The spread-spectrum TI ADC provides an eective randomization o the ADC selection sequence, which eliminates some o the non-ideal eects o the traditional TI ADC where the channel ADCs are selected in a periodic manner.. Thesis Organization This work proposes a union between the independently mature ields o mixed-signal circuit design and spread-spectrum techniques in telecommunication systems. In particular, a Σ modulator or analog-to-digital conversion employing spread-spectrum techniques is described. This thesis is divided into nine chapters, including the introduction chapter. Chapter presents the two common techniques or analog-to-digital conversion: Nyquist rate conversion and sigma-delta modulation analog-to-digital conversion. Chapter 3 describes the spread-spectrum technique as it applies to communications systems. Chapter 4 begins with a general

24 5 description o the Σ modulator design procedure and continues with the high-level transormation o a -bit Σ modulator design into a -bit spread-spectrum Σ modulator. Chapter 5 discusses the choices o various spreading sequences or use with the spread-spectrum Σ modulator. Furthermore, the choice o an ideal requency-shaped spreading sequence or use with the particular lowpass spreadspectrum Σ modulator is presented, along with simulation results o the spreadspectrum Σ modulator. Chapter 6 provides the details o the third-order -bit spread-spectrum Σ modulator prototype that was designed and implemented in a 0.35µm CMOS process. Additionally, the experimental results rom the prototype are presented. Chapter 7 applies the spread-spectrum technique to bandpass Σ modulator architectures. Chapter 8 extends the spread-spectrum technique in analogto-digital conversion beyond Σ modulation to Nyquist rate analog-to-digital converters. In particular, a time-interleaved Nyquist rate analog-to-digital converter employing spread-spectrum techniques is described. Finally, Chapter 9 provides a summary o this work and directions or uture work.

25 6 Chapter Analog-to-Digital Conversion The advancements o digital computing and signal processing in an inherently analog world continue to drive the need or devices capable o converting signals both to and rom the analog and digital domains. This role has allen upon analog-to-digital and digital-to-analog converters. This chapter begins by introducing the dierent techniques commonly used to convert an analog signal into its digital representation. These techniques include Nyquist rate, oversampling, and Σ analogto-digital conversion. Nyquist rate analog-to-digital conversion is described through its two underlying concepts: sampling and quantization. Although these topics are discussed in the context o Nyquist rate analog-to-digital conversion, the sampling and quantization processes are required or any orm o analog-to-digital conversion. The genre o oversampling analog-to-digital converters is then investigated with a ocus on the advantages o sampling the input signal at a rate much higher than the Nyquist rate. The concept o oversampling analog-to-digital conversion is then extended to oversampled analog-to-digital conversion employing quantization noise shaping. The class o oversampled converters employing noise shaping is commonly reerred to as

26 7 Σ analog-to-digital converters. The properties o Σ analog-to-digital converters are described as well as come common implementations.. Nyquist Rate Analog-to-Digital Conversion.. Sampling Analog to digital conversion is the process by which a continuous analog signal is sampled in time and quantized in amplitude producing a digital representation. Sampling in time produces a discrete-time version o the continuoustime signal by taking samples o the continuous-time signal at uniorm time instances nt s, where T s represents the sampling period. In other words, i x(t) represents the continuous-time signal, the samples o x(t), deined as x[n], may be represented as x[n] = x(nt s ). As a result, the requency domain content o the input signal is periodically replicated at integer multiples o the sampling requency s, where s = /T s. The sampling process is modeled in Figure -. In this igure, x(t) represents the continuous-time input signal and x s [n] represents the discrete time signal produced by the sampling process. The requency domain representation o the sampling process is described in Eq. (-). In the equation, X(j) represents the spectrum o the continuous-time input signal and X s (j) represents the spectrum o the sampled signal. X s ( j ) = X ( j( k s )) (-) T s k =

27 8 Figure -: Sampling process model. The requency domain result o the sampling process is shown graphically in Figure -. The highest input signal requency, B, determines the minimum sampling requency, s, required to preserve inormation contained in the input signal, according to Nyquist criterion. In this example s = B. According to Nyquist criterion, in order to prevent aliasing the input signal should be sampled with the sampling requency s such that s B. The sampling process is an invertible operation provided that the input continuous-time signal is sampled at a suiciently high rate so as to prevent aliasing. This may be achieved by applying an anti-alias ilter to the continuous-time input signal to band-limit the signal beore sampling []. X(j) s = B X (j) s B s B s B B Figure -: Frequency domain depiction o sampling.

28 9.. Quantization Amplitude quantization is a mapping procedure whereby the ininite set o input signal amplitude values is encoded into a inite set o output amplitude values. The amplitude quantization process is perormed by an element known as a quantizer. An N-bit quantizer is one which maps its input range to N output levels. The non-linear mapping procedure produces an error signal known as quantization error. Quantization error, e Q [n], is deined in Eq. (-) as the dierence between the quantizer output and sampled input signal. The model describing the amplitude quantization process is depicted in Figure -3. e [ n] = y[ n] x [ n] (-) Q s Quantizer x [n] s y[n] x [n] s + y[n] e[n] Figure -3: Quantizer model. According to [], over time the quantization error statistics approach those o a uniormly distributed white noise process that is uncorrelated with the input signal. Thereore, in order to simpliy the analysis o the quantization error, it is common to use the white noise approximation. This approximation allows the quantization error to be modeled by a uniormly distributed white noise process provided e Q [n] is decorrelated rom the input signal, and the input signal does not exceed the input range o the quantizer []. Under the white noise approximation, the quantization error probability density unction has the distribution shown in Figure -4. In the

29 0 igure and the orthcoming analysis, represents the separation between the output levels o the quantizer. ρ(e ) Q 0 e Figure -4: Quantization error probability density unction distribution. (-3). The quantization error power, σ e, may now be determined according to Eq. σ e Q = e ρ( e ) de Q Q (-3) Substituting in the quantization probability density unction depicted in Figure -4 or ρ(e Q ), the quantization error can be calculated as the result in Eq. (-4). σ e = (-4) According to the white noise approximation and Eq. (-), the quantized output signal, y[n], is a linear combination o the input signal, x s [n], and the quantization error, e Q [n]. Similarly, the spectrum o the quantized output signal is the linear combination o the input signal spectrum and the quantization error spectrum. The resulting spectrum o y[n] is depicted in Figure -5. The quantization error

30 spectrum is lat, thus resembling a white noise process. The power spectral density o the quantization error, N Q (j), when the sampling rate is s is given by Eq. (-5). N Q s e σ ( j ) = = (-5) s Y(j) X (j) s N (j) Q - s - 0 B B s Figure -5: Quantized signal spectrum. Consider an N-bit quantizer with a maximum ull-scale output range, V, deined by the maximum and minimum quantizer output values V and -V. The separation between output levels,, or an N-bit quantizer is deined according to Eq. (-6). = V N (-6) The Signal-to-Noise Ratio (SNR) o the quantized signal, y[n], is given by Eq. (-7) assuming the input signal is considered to be a zero-mean random process with a power o σ x []. σ x 0log0 = 0log 0 σ x 0log0 σ e σ e SNR = [db] (-7)

31 By substituting Eqs. (-4) and (-6) into Eq. (-7), the SNR calculation can be simpliied. The result is shown in Eq. (-8). σ x SNR = 0log V 6.0N [db] (-8) Equation (-8) reveals that or each additional bit o quantizer resolution, N, the improvement in SNR is approximately 6dB. Another important quantizer metric is the dynamic range (DR). Dynamic range is deined as the range o input signal values or which the quantizer produces a positive SNR []. The dynamic range calculation is typically perormed using sinusoidal input signals, in which case the dynamic range is the ratio o a ull-scale sinusoid to a sinusoid whose power is equal to the noise power []. The signal power or a ull-scale sinusoid is equal to V /. Thereore, the dynamic range can be expressed as in Eq. (-9). DR = V (-9) The dynamic range expression in Eq. (-9) may be reduced to a more useul orm by solving or V in Eq. (-6) and substituting into Eq. (-9). The result is given in Eq. (-0). DR = 6.0N +.76 [db] (-0) Similar to SNR, the DR o a quantizer increases by 6dB or each -bit increase in quantizer resolution. The white noise approximation is very useul or quantizer system analysis; however, the approximation is not always accurate. In some cases the quantization error may be correlated to the input signal, thus making the approximation invalid. When this happens, analysis o the quantizer system would be diicult i not

32 3 impossible. Fortunately, in most instances the white noise approximation is valid and allows or tractable analysis [].. Oversampling Analog-to-Digital Conversion The class o analog-to-digital converters (ADCs) known as oversampling ADCs outperorm Nyquist rate ADCs by sampling and quantizing the input signal at a sampling rate greater than twice the input signal bandwidth. As this section will show, the oversampling ADCs reduce the in-band quantization noise power by spreading it across the entire sampling bandwidth. Oversampling ADCs are typically divided into two conversion methods: oversampling pulse-code modulation (PCM) conversion and Σ modulation analog-to-digital conversion. Oversampling ADCs oer an improvement in resolution over Nyquist rate ADCs due to the act that the samples o the input signal are acquired at a rate higher than the Nyquist rate. To demonstrate the oversampling principle, the input signal spectrum and its oversampled spectrum are depicted in Figure -6. X(j) X (j) s - 0 B 0 B - - B s B s Figure -6: Frequency domain depiction o oversampling.

33 4 An N-bit quantizer, whose perormance was analyzed in Section.., subsequently quantizes the oversampled input signal. The noise power, σ e, injected into the sampled input signal, x s [n], by the quantizer was given in Eq. (-4). The total noise power is equal or both Nyquist rate ADCs and oversampling ADCs, but the requency distribution o the noise power is dierent since the oversampling ADCs are operating at a higher sampling rate. Since the quantizer is being modeled according to the white noise approximation, the noise power is uniormly distributed across the entire sampling bandwidth, - s / to s /. Figure -7 shows the power spectral density, N Q (j), o the quantization noise or sampling at Nyquist rate, s, and oversampling rate, s. N (j) Q Nyquist Oversampling - s - s - s - s s s s s Figure -7: Power spectral density o quantization noise or Nyquist and oversampling. The noise bandwidth o concern is that which lies in the signal bandwidth, B = [- s /, s /]. As Figure -7 shows, the quantization noise power lies entirely within the signal bandwidth or the Nyquist sampling case; however, only a raction o the quantization noise power lies within the signal bandwidth in the oversampling case. In order to take advantage o the noise spreading, the quantizer output must be lowpass iltered, which eectively removes the noise power outside the signal bandwidth. Following the low-pass ilter, the signal may be downsampled to the

34 5 Nyquist rate without aecting the SNR. The low-pass iltering and downsampling elements are collectively reerred to as a decimation unit. A block-diagram o the overall oversampled PCM system is provided in Figure -8. Analog e [n] Q t = nt s x'(t) Anti- Alias Filter x(t) x s[n] + = M s B N-bit Quantizer y[n] Digital M Digital Output (Resolution > N) Figure -8: Oversampling ADC model. Reducing the quantization noise power within the signal bandwidth reduces the noise power contribution rom the quantizer in the oversampling ADCs, resulting in an SNR improvement. According to the white noise approximation, the power spectral density o the quantization error is N Q (j) = σ e / s. I the oversampling PCM ADC has an ideal low-pass ilter with cuto requency B (corresponding to the signal bandwidth) ollowing the quantizer, the in-band noise power σ e is determined according to Eq. (-). σ e' = B B N ( j ) d Q (-) Substituting the power spectral density, N Q (j), into Eq. (-) results in the inal expression or the in-band quantization noise power or the oversampling PCM ADC. This result is given in Eq. (-). B σ = e' σ e (-) s

35 6 The SNR o the oversampling PCM ADC when the input signal power is given by σ x is deined in Eq. (-3) []. σ x 0log0 = 0log0 σ x 0log0 e + 0log 0 σ e' SNR = σ s B [db] (-3) The term s / B is commonly reerred to as the oversampling ratio (OSR). From Eq. (-3), it can be seen that or a given input signal with ixed bandwidth B, or every doubling o the sampling requency, s, the SNR o the oversampling ADC increases by 3dB. This result clearly demonstrates the perormance improvements made available through the oversampling process..3 Sigma-Delta Analog-to-Digital Conversion.3. Lowpass Sigma-Delta Analog-to-Digital Conversion Sigma-delta analog-to-digital converters are an extension o oversampling ADCs that not only spread the ixed amount o quantization noise, σ e, but also perorm shaping o the quantization noise away rom the signal band. By attenuating the amount o quantization noise within the signal band and ampliying the quantization noise outside the signal band, more o the quantization noise may be iltered out. Since more quantization noise is removed rom the signal band the resulting output ater low-pass iltering has a higher SNR. In addition to the noise shaping beneit, Σ analog-to-digital converters oer high linearity, reduced antialias ilter complexity, and high tolerance to analog circuit imperections [3].

36 7 The examination o Σ analog-to-digital conversion will begin by examining the irst-order Σ modulator. The irst-order Σ analog-to-digital conversion system, shown in Figure -9, is composed o two main components: the Σ modulator and the digital decimation ilter. The Σ modulator is the component o interest within this text. The quantizer in Figure -9 is assumed to be an additive white noise source according to the white noise approximation. This assumption is made in order to provide a tractable analysis o the Σ modulator operation. Analog e [n] Q z - s + x [n] + - -z - N-bit Quantizer y[n] M Digital Output (Resolution > N) Digital N-bit DAC First-Order Sigma-Delta Modulator Digital Decimator Figure -9: First-order Σ ADC. The Σ modulator shown in Figure -9 operates as ollows. The sampledelayed integrator integrates (Σ) the dierence ( ) between the sampled input signal, x s [n], and the analog value rom the N-bit digital-to-analog converter (DAC), which represents the quantizer output, y[n]. The integrator output value is then quantized by the N-bit quantizer producing the N-bit digital output signal, y[n]. The output signal is then ed back through the N-bit DAC where its analog value is determined. Assuming an ideal DAC, Eq. (-4) presents the z-domain equation describing the operation o the irst-order Σ modulator in Figure -9. ( z ) E ( z) Y ( z) = z X ( z) + (-4) Q

37 8 The Σ modulator output is the linear combination o a delayed version o the input signal and quantization noise that has been shaped according to a irst-order dierentiation ilter. The eect o the dierentiation on the quantization noise is a high-pass iltering; thereore, the quantization noise o the Σ modulator is shaped away rom low requency toward high requency. The transer unction by which the quantization noise is iltered is commonly reerred to as the noise transer unction, or NTF. To compare the noise shaping beneits o Σ modulation over pure PCM modulation, the NTF magnitude spectra or both are plotted. The result is shown in Figure -0. I the signal bandwidth is assumed to be s /0 (denoted in Figure -0 with the vertical bar) the reduction o in-band noise awarded by Σ modulation is clearly evident. Figure -0: NTFs o the PCM oversampled system and st -order Σ modulator.

38 9 A result o the reduced amount o in-band quantization noise is an increase in SNR over the PCM oversampling ADC. According to [], the SNR or a irstorder Σ modulator is given by Eq. (-5). SNR = π s 0log0 σ x 0log0 σ e 0log0 + 30log0 3 B [db] (-5) According to Eq. (-5), when the sampling requency is doubled, the SNR increases by 9dB. This result demonstrates a 6dB improvement over the PCM oversampling case. The analysis o Σ modulator perormance continues with a look at secondorder Σ modulators. The structure o a second-order Σ modulator is shown in Figure -. The irst-order Σ modulator structure remains; however, it is joined with a delay-ree integrator between the input and the sample-delayed integrator. The z-domain transer unction describing the operation o the second-order Σ modulator is shown in Eq. (-6), assuming an ideal DAC once again. ( z ) E ( z) Y ( z) = z X ( z) + (-6) Q e [n] Q z - s + x [n] + - -z z - N-bit Quantizer y[n] N-bit DAC Figure -: Second-order Σ modulator. Equation (-6) indicates that the output is a linear combination o a delayed version o the input signal and the high-pass iltered quantization noise, similar to the

39 0 irst-order structure. Compared with the irst-order Σ modulator, the quantization noise o the second-order Σ modulator undergoes a second-order high-pass iltering. Thereore, the second-order NTF shapes more o the in-band quantization noise away rom low requencies toward higher requencies. The result is a reduction o in-band noise and an increase in noise located at higher requencies. This is depicted in Figure -, which displays the magnitude spectra o the irst- and second-order NTFs as well as the PCM oversampling quantization noise. Figure -: NTFs o the PCM oversampled system, st -order Σ modulator, and nd -order Σ modulator. Figure - clearly indicates that the second-order Σ modulator provides an in-band noise reduction over the irst-order Σ modulator. As a result, the secondorder Σ modulator has a higher SNR than the irst-order Σ modulator. According to [], the SNR or the second-order Σ modulator is given by Eq. (-7).

40 SNR = π 4 s 0log0 σ x 0log0 σ e 0log0 + 50log0 5 B [db] (-7) When the sampling requency, s, doubles, the SNR or the second-order Σ modulator improves by 5dB. This represents a 6dB SNR improvement over the irst-order Σ modulator and a db SNR improvement over the PCM oversampling system. The general block diagram o an L th -order Σ modulator is shown in Figure -3. In general, as the order, L, o a Σ modulator continues to increase, the SNR will continue to increase. According to [], the ideal in-band SNR obtained using an L th -order Σ modulator is given by Eq. (-8). e [n] Q z - s x [n] - -z - - -z z - Stage Stage L- Stage L N-bit Quantizer y[n] N-bit DAC Figure -3: L th -order Σ modulator. SNR = π L s 0log0 σ x 0log0 σ e 0log0 + (0L + 0) log0 [db] (-8) L + B The ideal result in Eq. (-8) predicts that or every doubling o the sampling requency, the L th -order Σ modulator provides an additional (6L + 3) db o SNR. This also indicates that or every increase in order, L, o the Σ modulator, a SNR increase o 6dB is awarded over the (L-) th -order Σ modulator. The L th -order pure dierentiation technique described previously or Σ modulators provides a nice cornerstone or Σ modulator analysis; however, it is

41 rarely used in practice. As depicted in Figure -, each time the order o the Σ modulator is increased, the out-o-band gain o the NTF increases according to L. It has been shown in [4] that a Σ modulator may become unstable i the NTF out-oband gain is too large. As such, other topologies are used that restrict the out-o-band gain o the NTF to values that produce stable modulators [5]. Although this text will only discuss Σ modulators utilizing single-bit quantizers, a growing number o modulator designs are employing multi-bit quantizers [6] [8]. The simplicity o single-bit quantizers and the improved perormance o multi-bit quantizers exhibit a tradeo. The multi-bit Σ modulator achieves a particular SNR target at a lower oversampling ratio than the same order single-bit Σ modulator; however, the strict linearity requirements o the multi-bit DAC may make the circuit design much more diicult. Since the DAC output is directly combined with the modulator input, the DAC linearity needs to be at least N- bits or an N-bit ADC. While this is not easily achieved using standard DAC structures, techniques or improving DAC linearity have been proposed [9] []. In addition to the single- and multi-bit Σ modulators previously described, higher-order NTFs may be generated by cascading independent lower-order Σ modulator stages together [], [3]. This technique is commonly reerred to as multi-stage noise shaping, or MASH [4]. The advantage o the MASH technique is that the modulator is stable provided the independent Σ modulators comprising it are stable. The downside to cascaded Σ modulator systems is that they require an error cancellation network at the output to cancel out the quantization noise rom the stages preceding the inal stage. Thereore, in an ideal cascaded Σ modulator only the quantization noise rom the inal stage appears at the modulator output. However, in practical cascaded Σ modulator implementations, mismatch issues may reduce the extent o quantization noise canceling which negatively impacts the overall modulator perormance.

42 3.3. Bandpass Sigma-Delta Analog-to-Digital Conversion The lowpass Σ modulators described in the previous section are eective at converting low-requency signals into high-resolution digital representations. This is accomplished by designing the NTF such that nulls exist near DC so that the amount o quantization noise present in the signal bandwidth is minimized. Bandpass Σ modulators operate in a similar manner, except that the NTF nulls are relocated to requencies other than DC, thus shaping the quantization noise toward both DC and the Nyquist requency [3], [5], [6]. As a result, bandpass Σ modulators convert high-requency low-bandwidth signals to high-resolution digital representations in much the same manner that lowpass Σ modulators convert low-requency lowbandwidth signals. As is the case with lowpass Σ modulators, the oversampling ratio o bandpass Σ modulators is deined as one-hal the sampling requency divided by the width o the signal band o interest. A distinct advantage o bandpass Σ modulators is that they retain many o the beneits awarded by lowpass Σ modulators while processing higher-requency signals. Bandpass Σ modulators have ound numerous applications including, but not limited to, radio-requency (RF) communications systems, radar systems, and spectrum analyzers. In the context o RF communications systems, bandpass Σ modulators allow earlier digitization o the signals, enabling bandwidth-eicient digital modulation schemes as well as multi-mode (multi-standard) receivers. Bandpass Σ modulators thrive in communications systems since they eliminate the need or intermediate requency (IF) mixing stages. A simpliied RF receiver employing bandpass Σ modulation is shown in Figure -4. The bandpass Σ modulator immediately digitizes the RF input signal, which is then mixed down to baseband by the digital quadrature mixer. Finally, the signal is decimated, removing the quantization noise, and passed to the DSP or demodulation.

43 4 RF In Analog BP Σ Modulator Digital Quadrature Mixer cos(ω n) sin(ω n) 0 0 I Q Decimation Filter To DSP Figure -4: RF communications receiver employing a bandpass (BP) Σ modulator. A lowpass-to-bandpass transormation may be perormed to a lowpass Σ modulator to design a bandpass Σ modulator [6]. The lowpass Σ modulator that is subject to the transormation must satisy the desired perormance requirements, such as SNR, with the oversampling ratio requirement o the bandpass Σ modulator. The transormation z -z is commonly utilized since the transormation preserves the oversampling ratio o the lowpass Σ modulator and the NTF notch is placed exactly at s /4. Out o necessity, the transormation increases the order o the N th -order lowpass Σ modulator to a N th -order bandpass Σ modulator. To better describe the transormation process, a speciic example transorming a second-order lowpass Σ modulator into a ourth-order bandpass Σ modulator is examined. The NTF o the second-order Σ modulator is given by Eq. (-9). z + z NTF ( z) = (-9).3z + 0.5z Ater applying the z -z transormation, the ourth-order bandpass Σ modulator NTF is obtained and shown in Eq. (-0). 4 + z + z NTF ( z) = (-0) 4 +.3z + 0.5z

44 5 In order to illustrate the transormation, the pole-zero diagrams and the NTF magnitude responses are plotted in Figures -5 and -6, respectively. As shown in Figure -6, the ourth-order bandpass Σ modulator NTF has the same gain and requency characteristic o the second-order lowpass Σ modulator; however, the notch bandwidth has been compressed by two and replicated at ± s /4. As described in [5], the bandpass Σ modulator is equivalent to two interleaved copies o the original lowpass Σ modulator operating on subsampled data with alternating signs. Figure -5: Pole-zero diagrams or the lowpass (a) and bandpass (b) Σ modulators used in the lowpass-to-bandpass transormation example.

45 6 Figure -6: Magnitude response or the lowpass (a) and bandpass (b) Σ modulators used in the lowpass-to-bandpass transormation example.

46 7 Chapter 3 Spread-Spectrum in Communications Systems This thesis proposes to merge the concept o Σ analog-to-digital conversion with the technique known as spread-spectrum modulation. This chapter investigates the spread-spectrum concept as it applies to communications systems. The spreadspectrum technique has existed in military communications applications since the 950 s due, in part, to its resistance to narrowband intererence and its low probability o detection and interception. The spread-spectrum technique has shown many beneits in communications systems that indicate its potential eectiveness in Σ analog-to-digital conversion systems.

47 8 3. Spread-Spectrum Technique in Communications Systems Spread-spectrum techniques are commonly utilized in communications systems due to their ability to suppress various noise sources, particularly spectral intererers, as well as multipath distortions [7], [8]. The spread-spectrum technique was initially developed in the 940 s and 950 s or military and intelligence requirements due to its inherent property o hiding the signal below the channel noise loor, its resistance to narrowband intererence, and its low probability o detection and interception [9], [0]. In recent decades, the spread-spectrum technique has ound success in commercial applications as well, most notably in cellular telephones. A signal is said to be spread-spectrum modulated i it satisies three properties: the signal occupies a bandwidth much larger than is needed or the inormation signal, the modulation is perormed using a spreading code that is independent o the signal, and despreading at the receiver is done by correlating the received signal with a synchronized copy o the spreading code [7], [9] []. The two most common orms o spread-spectrum communications are Frequency- Hopping Spread-Spectrum (FHSS) and Direct Sequence Spread-Spectrum (DSSS). 3.. Frequency-Hopping Spread-Spectrum Frequency-Hopping Spread-Spectrum operates by broadcasting the message over a random series o carrier requencies, hopping rom requency to requency at ixed time intervals [7], [8], []. A typical FHSS system is depicted in Figure 3-. The input signal, b(t), is passed through an encoder, which implements the desired encoding algorithm, producing the signal b (t) that is centered around some base

48 9 requency. The encoded signal is then modulated with the random carrier signal whose requency is determined by the Pseudo-Noise (PN) Code Generator, producing the transmit signal, m(t). The received signal, r(t), consists o the transmit signal, m(t), as well as a spectral intererence signal, i(t), that was introduced by the channel. The spread-spectrum signal, r(t), is demodulated using the same randomly selected carrier requencies that the transmitter used to modulate the signal and decoded to produce the output signal, y(t). The spectral intererers introduced by the channel will only disrupt a very small portion o the FHSS message as compared to a message that was transmit at a single carrier requency near the intererer. Channel b(t) Encoder b'(t) X m(t) + r(t) X y'(t) Decoder y(t) Frequency Synthesizer i(t) Frequency Synthesizer PN Code Generator PN Code Generator Figure 3-: Frequency-Hopping Spread-Spectrum communication system. 3.. Direct Sequence Spread-Spectrum Direct Sequence Spread-Spectrum is achieved by modulating the input signal with a pseudo-random spreading code consisting o s and - s, which has a requency much greater than that o the input signal [8]. The basic DSSS system is depicted in Figure 3-. The transmitter input signal is modulated with the pseudorandom spreading code, s(t), which produces a wideband representation o the input signal. The newly created wideband signal, m(t), is then transmit over the channel to

49 30 the receiver. The received signal, r(t), which consists o the wideband spread input signal combined with spectral intererers, is then demodulated. In order or demodulation to unction properly, the pseudo-random spreading sequences at the transmitter and receiver must be synchronized. Ater demodulation, the input signal is returned to baseband and the spectral intererers introduced by the channel are spread as wideband noise. Since the receiver output is typically iltered around the input signal bandwidth, the wideband noise produced by the spectral intererers that lies outside the signal bandwidth is removed. As a result, only a small portion o the noise introduced by the spectral intererers remains in the signal band. This process results in an increased SNR. Carrier Channel Carrier b(t) X m(t) Modulator m'(t) + r'(t) Demodulator r(t) X y(t) s(t) Pseudo- Random Code i(t) s(t) Pseudo- Random Code Figure 3-: Direct Sequence Spread-Spectrum communication system. The spread-spectrum techniques utilized in our work most closely resemble the DSSS techniques in communications. The underlying idea proposed herein is to perorm a wideband spreading o the analog-to-digital conversion system input signal, pass the wideband version o the input through the noisy system, and recover the digital representation o the original input by demodulating the output with the spreading sequence. The goal o this research is to suppress more noise at the output o the ADC utilizing the spread-spectrum technique than the ADC system that does not utilize spectral spreading. This technique requires redesigning several o the components required by the ADC system to handle the wideband version o the

50 3 input, since traditional ADC systems only process the narrowband input directly. These new components are described throughout the text as they are introduced.

51 3 Chapter 4 Spread-Spectrum Σ Modulator Design Methodology This chapter presents the methodology or designing Σ modulators employing spread-spectrum chopper modulation. The procedure or designing the - bit spread-spectrum Σ modulator does not digress in any major way rom the design o a traditional -bit Σ modulator. Section 4. begins with a general discussion on the Σ modulator design procedure. This includes the basic design decisions required to ensure the Σ modulator will be stable and suit the desired application. Section 4. also describes the high-level design procedure using Matlab/Simulink sotware tools. The material in Section 4. utilizes the inormation rom Section 4. as the high-level design o a speciic third-order -bit Σ modulator in Matlab is presented. This example is signiicant to the text since the Σ modulator designed in this section will be used as the model or the third-order -bit spread-spectrum Σ modulator prototype. Section 4.3 describes the procedure or converting the highlevel Σ modulator design rom Section 4. into the signal low-graph representation.

52 33 Finally, Section 4.4 details the spread-spectrum Σ modulator. The spreadspectrum Σ modulator is shown to be eective at reducing the eects o DAC noise, substrate noise, and ampliier gain nonlinearity, licker noise, and DC oset. These noise sources and their eects on the Σ modulator are described in Section 4.4. Additionally, the method or transorming a traditional Σ modulator into a spread-spectrum Σ modulator is described in this section. In particular, the design procedure or a third-order -bit spread-spectrum Σ modulator is presented in detail. 4. Sigma-Delta Modulator Design Procedure The irst step in designing a Σ modulator is to determine the modulator type, order, and number o quantization levels that will suit the required design speciications. In terms o the modulator type, the designer must choose whether a lowpass or bandpass modulator is to be implemented. Once this is decided the modulator order and number o quantization levels are chosen according to the design space around a speciic SNR target. Example design spaces that illustrate the tradeo between SNR and OSR are provided in [4] and [3]. Once the decision or the modulator order and number o quantization levels has been made, the noise transer unction (NTF) ilter type to be implemented must be decided. Common NTF ilter choices or lowpass Σ modulators include highpass Butterworth, Inverse Chebyshev type, and maximally-lat all-pole ilters. These are popular choices since the high requency portion o the NTF is maximally lat outside the signal band. Additionally, the signal transer unction (STF) resulting rom these NTF design options is maximally lat and unity across the signal band,

53 34 which implies that the choice o NTF does not aect the input signal. In addition, the maximum out-o-band gain o the highpass ilters listed may be controlled by the ilter cuto requency. This is important since research in the ield o Σ modulators has shown that stable Σ modulator design may be achieved when the maximum out-o-band gain is restricted to a speciic value. This will be investigated in more detail later in the text. The next step in the Σ modulator design procedure is to determine the loop topology to implement the chosen modulator. The loop topology is responsible or implementing both the NTF and STF. Thereore, the proper decision o loop topology is an important design step. There are several loop topologies that are commonly used in the design o Σ modulators. The choice o NTF ilter type aects the loop topology to be used in a particular design. The reason or this is that some loop topologies only allow or zero placement at DC, while some topologies allow or zero placement at requencies other than DC. The ormer loop topologies are thus useul or Butterworth and maximally-lat all-pole NTF ilter designs while the latter topologies are utilized to implement Inverse Chebyshev type ilters. The three most common loop topologies or implementing Butterworth and maximallylat all-pole highpass ilters are the chain o integrators with weighted eedback summation, the chain o integrators with weighted eedorward summation, and the chain o integrators with weighted eedback and eedorward summation. These topologies are illustrated in Figures 4-, 4-, and 4-3, respectively. Similarly, the two most common loop topologies or implementing the Inverse Chebyshev type highpass ilters are the chain o integrators with eedorward summation and local resonator eedbacks and the chain o integrators with distributed eedback, distributed eedorward, and local resonator eedbacks. These loop topologies are shown in Figures 4-4 and 4-5, respectively. Once the loop topology has been decided the transer unction or the overall Σ modulator may be determined in terms o the individual eedorward, eedback, and local resonator eedback coeicient variables. These coeicient variables will be assigned values in the subsequent design steps.

54 35 X z - a z z - -z - z - -z - Y b b b 3 Figure 4-: Chain o integrators with weighted eedback summation loop topology. X + z - z - z - -z - -z - -z - a a a 3 + Y Figure 4-: Chain o integrators with weighted eedorward summation loop topology. X a a a 3 z - z z - -z - z - -z - Y b b b 3 Figure 4-3: Chain o integrators with weighted eedback and eedorward summation loop topology.

55 36 γ X z - z z - -z - -z - z - a a a 3 + Y Figure 4-4: Chain o integrators with eedorward summation and local resonator eedbacks loop topology. X a a a 3 γ + z z - -z - z - -z - Y b b b 3 Figure 4-5: Chain o integrators with distributed eedback, distributed eedorward, and local resonator eedbacks loop topology. Now that the NTF ilter type has been chosen and the order o the Σ modulator is known, ilter design sotware is used to obtain a stable ilter design or the NTF. Speciically, Matlab may be used to design the Butterworth, maximally-lat all-pole, and inverse Chebyshev type ilters using the unctions butter, maxlat, and cheby, respectively. The typical inputs to these unctions include the order, cuto requency, and ilter type (lowpass, highpass, bandpass, or bandstop). Additionally, the outputs are the a and b vectors containing the

56 37 coeicient values o the transer unction represented in Eq. (4-) [4]. Since this portion o the text will describe the design o a lowpass Σ modulator we will only consider the design criteria required or this type o modulator. B( z) b() + b() z NTF( z) = = A( z) + a() z b( n + ) z a( n + ) z n n (4-) In order to obtain a stable Σ modulator, the maximum out-o-band gain o the NTF must be restricted to a speciic value. This is achieved by adjusting the ilter cuto requency or the NTF. Decreasing the cuto requency or a ilter o a given order reduces the amount o out-o-band gain. Thereore, the cuto requency is adjusted until the desired maximum out-o-band gain is obtained. At this point, the Matlab butter, maxlat, or cheby unction has returned the values o the NTF a and b coeicient vectors. In order or the transer unction to be a realizable system, the a() and b() coeicients must be scaled to equal. This is done by dividing all o the a coeicient values by a() and the b coeicient values by the b() coeicient. The resulting scaled a and b coeicients yield a ilter whose initial impulse response value is equal to (h(0) = ). Now that the a and b coeicients are known or the NTF, the individual eedorward, eedback, and local resonator eedback coeicient values may be determined. This is done by equating the variables o the hand-calculated NTF with the corresponding a and b values returned by the ilter design sotware. Once the individual eedorward, eedback, and local resonator eedback coeicient values are calculated, high-level simulations o the Σ modulator may be perormed to veriy unctionality and stability. Once a stable Σ modulator has been designed, dynamic range scaling o the integrators is perormed in order to ensure each integrator swings to its maximum and minimum values, thus ensuring maximum dynamic range. Ater dynamic range scaling, it is important to once again veriy the stability and unctionality o the Σ modulator.

57 38 4. High-Level Third-Order Σ Modulator Design Now that the general Σ modulator design procedure has been presented, the Σ modulator speciic to this text will be examined. Conversion rom a standard Σ modulator to the spread-spectrum Σ modulator may be perormed once the initial high-level modulator design is complete. Thereore, the design presented in this section details the standard Σ modulator that will be converted later into the spreadspectrum Σ modulator o interest to this text. The design process will include the step-by-step decisions required to arrive at the implemented design. Since the targeted applications or the Σ modulator designed in this text are low requency in nature, a lowpass modulator topology was chosen or implementation. Additionally, since the main goal o this text is proo o concept, a third-order -bit modulator design was deemed suitable. The next decision to be made in the design low was to choose the highpass ilter type to be used or the NTF. The spread-spectrum Σ modulator was implemented as a third-order switched-capacitor Σ modulator utilizing a NTF whose pole locations were determined according to a Butterworth highpass response. This was due to the straightorward loop topologies used to implement the Butterworth highpass transer unction. Since we chose to implement a Butterworth highpass ilter as the NTF, the loop topology must be either the chain o integrators with weighted eedback summation, the chain o integrators with weighted eedorward summation, or the chain o integrators with weighted eedback and eedorward summation. The speciic loop topology chosen to implement the Σ modulator in this text was the chain o integrators with weighted eedback summation. When this loop topology is utilized with a NTF that has a Butterworth highpass response, then the STF will have a Butterworth lowpass response. The result o this is that the STF will be nearly lat across the input bandwidth, which

58 39 yields an improvement over the other loop topologies. In addition, since the STF is lowpass in nature, it will help to keep the modulator stable when transient signals with large out-o-band energy are applied to the Σ modulator input [5]. The drawback to this topology and NTF ilter choice is a reduction in SNR over ilters that are equiripple in the stopband such as the inverse Chebyshev type ilter. The inverse Chebyshev type ilter provides improved quantization noise attenuation over the entire signal bandwidth. The speciic loop topology implemented in this text is shown in Figure 4-6. Analysis o the modulator loop, shown in Figure 4-6, yields the dierence equation in Eq. (4-). b b b 3 z - -z X Y -z - -z - a a a 3 E Figure 4-6: Chain o integrators with weighted eedback loop topology chosen or the Σ modulator design. ( ) ( ) ( ) = + 3] [ ] [ 3 ] [ 3 ] [ n y b n y b a b n y b a a b a b n y 3] [ ] [ 3 ] [ 3 ] [ ] [ n e n e n e n e n x a a a (4-) The resulting NTF is given by Eq. (4-3). ( ) ( ) ( ) ( ) ( ) = z b z b a b z b a a b a b z z NTF (4-3) Additionally, the STF may be determined according to Eq. (4-4). ( ) ( ) ( ) ( ) = z b z b a b z b a a b a b z a a a z STF (4-4)

59 40 Since the ilter design sotware returns values or both the numerator and denominator z -i, i = 0,,, 3, coeicients, some initial assumptions must be made in order to calculate values or the individual loop coeicients. The irst assumption is to let a = b. This assumption causes the input signal and eedback to have approximately equal power levels. Secondly, we assume that a = a 3 =. We make this approximation since these coeicients are used or dynamic range scaling o the integrator outputs. The values or the a and a 3 coeicients will be determined once the initial design procedure has been completed. Ater these assumptions are made, the NTF and STF are simpliied to the results expressed in Eqs. (4-5) and (4-6). ( ) ( z ) z = NTF (4-5) 3 ( 3 b b b ) z + ( 3 b b ) z ( b ) z STF ( z) = 3 ( 3 b b b ) z + ( 3 b b ) z ( b ) z 3 b z 3 3 (4-6) The next step in the process o designing the Σ modulator is to use Matlab to obtain a stable NTF ilter design. Since the NTF ilter type was chosen to be a highpass Butterworth ilter, the Matlab unction butter will be utilized. According to Lee s criterion or stable Σ modulator design, the maximum out-o-band gain o the NTF ilter should remain below [5]. Although this criteria has been shown in [6] to be neither necessary nor suicient, it is still widely accepted as a general rule-o-thumb or stable Σ modulator design provided extensive simulations are done to veriy stability. More recent conservative criteria have suggested to design the maximum out-o-band NTF gain to be no larger than.5 [4], [7]. This text utilizes the more conservative design constraints. Thereore, the cuto requency o the highpass ilter to be designed should be adjusted until the maximum out-o-band gain o the ilter is below.5. In order to allow or eventual process variations and capacitor ratio variances, the maximum out-o-band gain or this design was limited to.4. Ater several iterations o cuto requency values in the butter unction,

60 4 shown in Table 4-, the maximum cuto requency value or the out-o-band gain design constraint was ound to be 0.05 ( s /). Ater scaling the a() and b() coeicients to equal, the realizable NTF was returned by Matlab and is shown in Eq. (4-7). Iteration Wn Maximum Out-o-Band Gain Table 4-: Maximum out-o-band gain results when using various Wn cuto requency values in the Matlab unction butter. ( ) ( z ) z = 3 NTF (4-7) 3.343z z 0.554z Equating the respective numerator and denominator z -i, i = 0,,, 3, NTF coeicients rom Eqs. (4-5) and (4-7) produces the individual loop coeicient values. These values are listed in Table 4-. a i b i a a a 3 b b b Table 4-: Coeicient values or use in the Σ modulator shown in Figure 4-6. Using the coeicient values rom Table 4-, the Σ modulator was then simulated at the system level in the Matlab/Simulink environment. This was done to veriy the unctionality o the design as a lowpass Σ modulator with a third-order NTF. Ater the veriication step, dynamic range scaling o the integrators was

61 4 perormed. The maximum comparator input value was obtained when a 0.7 V (relative to V) amplitude sine wave was applied to the modulator. This represents the maximum normalized input amplitude that ensures stability o the Σ modulator and will be used or integrator dynamic range scaling. The maximum output values or each integrator are detailed in Table 4-3. Integrator Maximum Output Table 4-3: Maximum integrator output values. The maximum output values listed in Table 4-3 provide the dynamic range scaling actors required to achieve similar integrator output swings in each o the integrators in the Σ modulator. To increase the integrator output value by a actor k, the input branches to the integrator should be multiplied by k while the output branches should be divided by k. In this case, k is equal to the inverse o the maximum integrator output value or the respective branch (i.e., k = /0.6, k = /0.5, and k 3 = /0.9897). As a result o the dynamic range scaling, the a i and b i coeicient values are altered. The new dynamic-range scaled a i and b i coeicient values are given in Table 4-4 as a i and b i, respectively. a i b i a a a 3 b b b 3 k a k a /k k 3 a 3 /k k b k b k 3 b Table 4-4: Dynamic range scaled coeicients or the Σ modulator shown in Figure 4-6.

62 43 The circuit-level implementation o the coeicients given in Table 4-4 is accomplished as a ratio o capacitors. Due to this implementation, the coeicient values in Table 4-4 should be rounded to values easily realized by ratios o integer capacitor values. Once the rounded, scaled values have been determined, it is necessary to veriy that the NTF ilter remains stable with a maximum out-o-band gain below.5. Thereore, the irst step in this process is to appropriately round the scaled coeicient values rom Table 4-4. The new rounded, scaled loop coeicient values are provided in Table 4-5. a i b i a a a 3 b b b Table 4-5: Rounded, dynamic range scaled coeicients or the Σ modulator loop topology shown in Figure 4-6. The rounded, scaled coeicients listed in Table 4-5 may now be used in conjunction with Eqs. (4-3) and (4-4) to determine the new NTF and STF. The results are shown in Eqs. (4-8) and (4-9), respectively. ( ) ( z ) z = 3 NTF (4-8) 3.35z +.875z 0.5z 0.05z STF ( z) = (4-9) 3.35z +.875z 0.5z The Matlab unction tzp is then used to enter the NTF into Matlab and convert it into pole-zero representation according to the a and b coeicient vectors, which can be extracted rom the NTF equation given by Eq. (4-8). Once the NTF is entered into Matlab, the poles and zeros are plotted on the unit circle to ensure NTF stability. The resulting pole-zero plot is shown in Figure 4-7. According to the igure, all o the poles are located within the unit circle and all o the zeros are

63 44 located at DC. This is veriied by Table 4-6, which lists the pole and zero locations. The zero locations are as expected since the NTF is implemented by a high-pass Butterworth ilter. Also, since the poles are all located within the unit circle, the NTF is implemented by a stable ilter design. Zeros Poles 0.644, ± 0.05j Table 4-6: Pole and zero locations or the Σ modulator using the rounded, dynamic range scaled coeicients. Figure 4-7: Pole-zero plot displaying pole and zero locations or the Σ modulator using the rounded, dynamic range scaled coeicients.

64 45 Once the stability o the NTF ilter has been veriied, the maximum out-oband gain o the NTF should be determined. The Matlab unction reqz calculates the requency response o a digital ilter speciied by the a and b ilter coeicient vectors. Ater Matlab has calculated the requency response, the maximum out-oband gain value can be determined. The maximum out-o-band gain or the NTF implemented with rounded, scaled coeicients was ound to be.3974, which is below the design target o.4. Thereore, according to Lee s criterion, the modulator implemented with the NTF described herein should result in a stable design. The requency response o both the NTF and STF are shown in Figures 4-8 and 4-9. Figure 4-8 depicts the requency response across all requencies rom 0 to Nyquist ( S /), while Figure 4-9 depicts the requency response within the input signal bandwidth (rom 0 to 500Hz). Figure 4-8: Frequency response o the NTF and STF across the entire bandwidth.

65 46 Figure 4-9: Frequency response o the NTF and STF across the assumed input signal bandwidth. The inal step in the initial design o the Σ modulator is to veriy the unctionality o the modulator using high-level simulation tools. For the Σ modulator proposed herein we chose to implement the design in Simulink while the data processing was done using Matlab. The loop topology depicted in Figure 4-6 was inserted into Simulink utilizing the coeicients listed in Table 4-5. The simulation parameters are provided in Table 4-7. Simulation Parameter Value Sampling Frequency 00kHz Bandwidth 500Hz OSR 00 Input Signal Frequency 00Hz Input Signal Amplitude 0.7 V (relative to V ull-scale) Table 4-7: Simulation parameters used or Matlab/Simulink veriication o the Σ modulator.

66 47 The high-level simulation results are shown in Figures 4-0 and 4-. Figure 4-0 depicts the Σ modulator output spectrum across the range o requencies rom 0 to Nyquist rate. Additionally, Figure 4- shows the Σ modulator output spectrum across the input signal bandwidth. The results depicted in Figures 4-0 and 4- indicate that the Σ modulator designed in this section unctions appropriately. Figure 4-0: Simulation result o the designed Σ modulator across the entire bandwidth.

67 48 Figure 4-: Simulation result o the designed Σ modulator across the assumed signal bandwidth.

68 High-Level to Signal Flow-Graph Σ Modulator Design Now that the high-level design o the third-order Σ modulator is complete, the irst step required to produce the switched-capacitor circuit-level implementation is taken. This step is to transorm the high-level block diagram shown in Figure 4- into a signal low-graph representation. The signal low-graph representation is then translated directly into the circuit schematic. The block diagram shown in Figure 4- depicts the Σ modulator designed in the previous section. As seen in the igure, both delay-ree and sample-delayed integrators are required or implementation. The circuit schematic and the equivalent signal low-graph representation or the delay-ree and sample-delayed integrators are provided in Figures 4-3 and 4-4, respectively. These igures represent the single-ended version o the respective integrators or simplicity; however, the ullydierential versions o the integrators may be determined rom the igures shown. The summation node o the signal low-graph represents the input node o the operational ampliier in the integrator schematic. This node is included in the signal low-graph representation since additional switched-capacitor branches may be included at the input side o the integrator. Speciically, this summation node is used or the additive eedback required or the Σ modulator implemented in this text. E X z - -z - z - -z - Y Figure 4-: High-level Σ modulator block diagram.

69 50 C I v in φ φ C S φ φ - + v out v in -C S + C I -z - v out Figure 4-3: Circuit schematic and signal low-graph o the delay-ree integrator. C I v in C S φ φ - C v z - S in + φ φ + v out C I -z - v out Figure 4-4: Circuit schematic and signal low-graph o the sample-delayed integrator. The transer unctions or the circuits shown in Figures 4-3 and 4-4 are provided in Eqs. (4-0) and (4-), respectively. These transer unction equations veriy that Figure 4-3 represents the delay-ree integrator and Figure 4-4 represents the sample-delayed integrator. H H C z S ( z) = C C S ( z) = C I I z z (4-0) (4-) There are three steps needed to transorm the high-level block diagram o the thirdorder Σ modulator shown in Figure 4- into its equivalent signal low-graph representation. The irst step is to relocate the delay element o the third integrator to the respective input paths. The result o this is shown in Figure 4-5. The next step is to disconnect the eedback path and represent each eedback path with its own input node, which is connected to the eedback reerence voltage, V DAC. Figure 4-6

70 5 depicts the result o this step. The inal step, shown in Figure 4-7, is to replace the integrators rom the high-level block diagram with their signal low-graph equivalents. The result o this inal step indicates that sign manipulation o the coeicients and V DAC eedback reerence voltages is required. Additionally, the coeicients are represented as capacitor ratios that correspond to Figures 4-3 and 4-4. E X z z - -z - -z - Y z - Figure 4-5: Block diagram o the Σ modulator ater the delay element has been relocated. E X z z - -z - -z - Y z - DAC V DAC V DAC V DAC V DAC Figure 4-6: Block diagram o the Σ modulator ater the eedback path is represented by voltage nodes. X C S - = -0. C I C S C S3 - = -0.5 z C - = 0.5z I C - I z - -z - -z - E Y C S - = -0. C I V DAC C S - = -0.5 C I - - V DAC C S3 z - = 0.5z C - I3 V DAC V DAC DAC Figure 4-7: Signal low-graph representation o the Σ modulator.

71 5 In order to veriy that the sign manipulation was perormed correctly, the minus sign that multiplies the input coeicient may be pushed through the summation node to multiply the irst eedback path and the -0.5 orward path coeicient. Ater this manipulation, Figure 4-7 becomes identical to Figure 4-5. Thereore, the signal low-graph represented in Figure 4-7 is the correct representation o the high-level block diagram shown in Figure 4-. Additionally, Figure 4-7 identiies the relationship between the sampling capacitor, integrating capacitor, and the coeicient values or each stage. These relationships are detailed in Table 4-8. Integrator Stage Capacitor Ratio Coeicient Value S I S I 3 S3 I3 C C 0. C C 0.5 C C 0.5 Table 4-8: Relationship between the capacitors and the coeicient values. Since the ultimate goal o this work is to design a spread-spectrum Σ modulator, the circuit level implementation o the signal low-graph depicted in Figure 4-7 will not be examined at this time. However, in the upcoming section that describes the design procedure o the spread-spectrum Σ modulator rom the standard Σ modulator designed in Sections 4. and 4.3, the signal low-graph o the spread-spectrum Σ modulator will be converted into a circuit-level schematic diagram.

72 Spread-Spectrum Σ Modulator CMOS IC design has always maintained the objective to incorporate as much circuitry possible on a single chip in an eort to keep cost down. However, in more recent years as the eature size o the abrication processes has reached submicron levels, the ability to integrate several systems on a single chip has become commonplace. As a result, noise-sensitive analog blocks and noisy digital signal processing blocks are regularly being placed on a common substrate. The result is an increased eect o substrate noise and power supply noise on the analog circuitry. It should come as no surprise that analog-to-digital converters, which require both analog and digital circuitry, are experiencing increased adverse eects rom substrate noise and power supply noise. According to [8], the SNDR o a Σ modulator may decrease by over 0dB in the presence o noisy digital circuitry such as toggling inverters. In addition to substrate noise and power supply noise, it has recently been shown that nonlinear ampliier gain also adversely aects the perormance o Σ modulators [9], [30]. In the past, only the eect o inite ampliier gain on the perormance o Σ modulators has been studied. However, nonlinear ampliier gain has been shown to introduce harmonic distortions into the modulator output spectrum and also increase the noise loor level [9]. As a result, the expected perormance o the Σ modulator is sacriiced. It is well known that Σ ADCs are suitable or high resolution and low-tomoderate bandwidth applications. However, when circuit nonidealities such as substrate noise, power supply noise, and nonlinear ampliier gain are introduced into the Σ modulator, dynamic range is sacriiced. To remedy this, the spread-spectrum Σ modulator architecture presented herein may be utilized. The spread-spectrum Σ modulator utilizes spread-spectrum modulation, whereby a signal with speciic spectral characteristics, used as a chopper modulation signal, eliminates the substrate

73 54 noise, power supply noise, and nonlinear ampliier gain spectral peaks by spreading them as noise across the entire modulator spectrum. This noise, along with the resulting quantization noise, is then shaped away rom the baseband input signal to high requency where it is iltered out by the decimation ilter. The proposed method eliminates the strong distortion component near DC created by harmonics o the digital sampling clock, the in-band spectral intererers rom power supply noise, and the even-order harmonics produced by the nonlinear ampliier gain. These results along with the spread-spectrum Σ modulator design procedure are presented in the orthcoming sections. In addition to spreading substrate noise, power supply noise, and nonlinear ampliier gain spectral peaks, spread-spectrum modulation also negates the eects o integrator opamp and DAC non-idealities (/ noise, DC oset, and even-order nonlinearities). The spread-spectrum Σ modulator shapes the input signal about the Nyquist requency beore it sees the non-idealities rom the integrator opamps and DAC and shapes the quantization noise toward low requency. Traditional Σ modulators shape the quantization noise toward high requency while leaving the low requency input signal unchanged. The undesirable circuit noise contributions will remain at low requency where the quantization noise is shaped by the spreadspectrum Σ modulator. When the quantizer output undergoes one inal spreadspectrum multiplication, the input signal is returned to baseband, while the quantization noise along with the low requency circuit nonidealities are shaped toward high requency. This procedure is much like that described in [3] or the mirrored-integrator Σ ADC DAC Reerence Voltage Noise Historically, considerable attention has been given to ensure the reerence voltages provided to the eedback DAC are immune to noise since they are directly

74 55 added to the input signal, aecting the overall modulator perormance. Traditional Σ modulators commonly require low-noise on-chip bandgap reerence circuits, external reerence voltage sources, or large o-chip decoupling capacitors to ilter out the noise on the DAC reerence voltage [3]. As a result, a penalty is paid in terms o on-chip or o-chip area and/or increased power consumption. One distinct advantage o the proposed design is that the eedback switched-capacitor DAC is enclosed within the spread-spectrum randomized structure. This means that the DAC eedback signal experiences one ewer spread-spectrum modulation than the input signal indicating that the low-requency DAC noises will be removed rom the signal bandwidth and spread as a wideband noise. Thereore, the switched-capacitor DAC reerence voltages do not require the stringent conditioning that other designs require since its low-requency noise does not have as great an impact on the dynamic range o the Σ modulator Substrate Noise Substrate noise is a growing problem in CMOS mixed-signal and system-ona-chip integrated circuit (IC) designs as circuit integration increases with decreasing eature sizes [33]. The substrate o an IC ideally has zero impedance. However, in reality this is not the case. The substrate possesses some inite impedance; thereore, any current injected into the substrate produces voltage luctuations in the V SS supply voltage typically connected to the substrate. These voltage luctuations on the substrate are more commonly reerred to as substrate noise. It has been shown in [34] [37] that there are three main mechanisms or generating substrate noise in mixed signal circuits: capacitive coupling, digital power supply transients, and impact ionization. The overall substrate noise seen by the analog circuitry on chip is the sum o the noise generated by each individual source.

75 56 Capacitive coupling, in the context o substrate noise, reers to the coupling that exists between the source and drain regions o a MOSFET with the substrate through the junction capacitances. In addition, coupling also exists between the gate capacitances and the substrate in MOSFETs [37]. These coupling mechanisms are illustrated in Figure 4-8. The substrate noise waveorms generated by capacitive coupling are correlated to the digital waveorms on the MOSFET terminals. This is due to the act that a capacitor tends to maintain a constant voltage across itsel. Thereore, when there is a change in voltage on one side o the capacitor it will result in a similar change on the other side [35]. As a result, when there is a low-to-high signal transition at one o the MOSFET terminals, a low-to-high signal will be created on the substrate. S G D n n p-substrate Figure 4-8: Capacitive coupling mechanisms or substrate noise. Digital power supply noise is a product o the inductance and resistance rom the bond wires connecting the power supplies to the chip as well as di/dt noise. Ringing o the power supply voltages is created by the inductive connections to the chip and the on-chip capacitance between the power supply and ground. A more common name or this ringing is ground bounce. Due to the nonideal substrate, a small resistance exists between the digital V SS (or ground) power supply and the substrate. As a result, any ground bounce or other noise present on the digital V SS power supply line will also be present in the substrate. This indicates that digital power supply noise is commonly the largest source o substrate noise [34].

76 57 The inal source o substrate noise considered in this text is impact ionization. When a MOSFET is biased in the saturation region, the saturation current lowing rom drain to source generates an electric ield near the drain. I the electric ield is large enough, the kinetic energy o some o the unbound charge located in the depletion region is increased causing the charges to accelerate. The accelerated charges are typically reerred to as hot carriers. As the hot carriers are accelerated, they may collide with electron-hole pairs within the silicon lattice structure and dislodge them. The dislodging o the electron-hole pairs is known as impact ionization [35]. The majority o the holes generated by impact ionization low back into the substrate, thus producing a drit current within the substrate [37]. The substrate current created by impact ionization contributes to the overall substrate noise. It has been shown, however, that the eects o impact ionization on the substrate noise are strongly dependent on the technology used [34] Nonlinear Ampliier Gain The eect o inite DC gain on Σ modulator perormance has been well documented in literature to produce integrator leakage in which only a raction o the previous output sample is added to the current input sample []. This aects the extent to which the Σ modulator shapes low-requency quantization noise []. However, the eects o nonlinear DC gain on Σ modulator perormance have been largely overlooked until recently [9], [30]. According to [9], nonlinear DC gain introduces harmonic distortions into the modulator output spectrum and also increases the in-band noise loor. Finite integrator ampliier DC gain results in integrator leakage, whereby only a raction o the previous output sample is added to the current input sample. The transer unction representing a leaky integrator is given in Eq. (4-), where α = A - 0 is deined as the integrator leakage actor (A 0 is the ampliier DC gain).

77 58 H αz ( z) = (4-) However, the ampliier DC gain does not remain constant over the range o all ampliier output values due to the change in the output transistors output resistance [9]. In reality where large-signal swings are common at the ampliier output, the ampliier DC gain is a unction o the ampliier output voltage, v out. In particular, an ampliier with an NMOS common-source output stage will have higher DC gain or lower ampliier output voltages, and the DC gain will decrease as the ampliier output voltage increases. This was veriied through simulation o a two-stage ampliier utilizing an NMOS common-source output stage with a PMOS active load. The resulting DC gain as a unction o the output voltage or the two-stage ampliier is shown in Figure 4-9. The ampliier nonlinear DC gain characteristic causes the overall integrator gain and corresponding pole to constantly change as a unction o the output voltage value [9]. Since the integrator gain is a unction o the output value and the output value depends on the previous input signal samples (i.e., integrator's gain depends on the input signal), the integrator exhibits non-linear behavior and harmonic distortions are introduced into the modulator output. In order to simulate the eects o the nonlinear ampliier gain on the Σ modulator, an integrator model must be obtained that includes the nonlinear ampliier gain. Since the ampliier gain is nonlinear, it is assumed to take on the orm o that shown in Eq. (4-3). 3 ( v ) = A + A v + A v A v A + o 0 o o 3 o (4-3)

78 59 Figure 4-9: Ampliier DC gain as a unction o ampliier output voltage. Using the Matlab unction polyit, the A i, i = 0,,, 3, coeicients that best it the nonlinear gain measurements represented by the polynomial presented in Figure 4-9 may be determined in a least squares sense [4]. These coeicients are presented in Table 4-9. Coeicient Value A A -9.6 A 0.86 A Table 4-9: Coeicient values corresponding to Eq. (4-3) Equation (4-4) presents the integrator model chosen or implementation to simulate the nonlinear eect o the ampliier gain. In the equation, A(v o ) corresponds

79 60 to the nonlinear gain expressed in Eq. (4-3). Figure 4-0 shows the overall integrator block diagram that was implemented in the Matlab/Simulink environment or simulation o the Σ modulator. The operator shown in Figure 4-0 represents squaring o the input to the block, which in this case is v o. In order to simpliy the model, only the nonlinearities o second-order and lower were considered. Analysis o the ideal integrator case may be used to validate the integrator model presented in Eq. (4-4). The ideal integrator is obtained when the ampliier gain is constant and ininitely large. I A(v o ) is assumed to be constant and A(v o ), then Eq. (4-4) simpliies to the expression in Eq. (4-5). The result in Eq. (4-5) is the expected integrator equation assuming an ideal ampliier. = v 0 vi v o vo z A( vo ) A( vo ) (4-4) v0 = vi z (4-5) A(v o) * + + A(v o) v i X -z - v o Figure 4-0: Integrator block diagram used in Simulink to implement the nonlinearities Spread-Spectrum Σ Modulator Design This section describes the methodology to transorm a traditional Σ modulator into a spread-spectrum Σ modulator. The transormation will begin with

80 6 the high-level third-order -bit Σ modulator designed in Section 4.3 and will end with the circuit-level schematic o the third-order -bit spread-spectrum Σ modulator. The irst step in obtaining the high-level spread-spectrum Σ modulator design is to place pairs o spread-spectrum multipliers beore and ater each delayree integrator in the traditional Σ modulator, which is shown in Figure 4-6. In the case o a sample-delayed integrator, the integrator is irst separated into a delay-ree integrator ollowed by the delay element. The spread-spectrum multiplier pairs are then inserted beore and directly ater the delay-ree integrator. This irst step is illustrated in Figure 4-. The spread-spectrum multiplying sequence is represented in the igure as e[n]. The spread-spectrum sequence utilized is a binary sequence o s and - s. The particular spread-spectrum sequence employed and a method or generating the sequence will be described in Chapter 5. X a + a + + -z - a 3 z - -z - -z - Y b b b 3 Figure 4-: Insertion o spread-spectrum multiplier pairs into the third-order Σ modulator. The spread-spectrum multipliers inserted into the traditional Σ modulator structure receive identical spread-spectrum sequences, e[n]. Additionally, since the spread-spectrum multipliers are introduced as pairs and each multiplier in the pair is provided the same sequence o s and s they eectively perorm multiplication by. Thereore, the introduction o the spread-spectrum multipliers leaves the overall modulator unction unchanged.

81 6 Once the spread-spectrum multipliers are inserted into the traditional Σ modulator structure, one multiplier rom each pair is moved through the modulator. The intermediate stages in rearranging the spread-spectrum multipliers are shown in Figures 4- and 4-3. As some o the spread-spectrum multipliers are moved through the modulator, they may encounter other spread-spectrum multipliers. I this is the case, they reorm a spread-spectrum multiplier pair resulting in multiplication by. Thereore, the overall number o spread-spectrum multipliers may be reduced as the multipliers are moved through the Σ modulator. Upon completion o spreadspectrum multiplier rearrangement, the spread-spectrum Σ modulator is generated. The resulting third-order -bit spread-spectrum Σ modulator structure is shown in Figure 4-4. X a + a + a 3 + -z - -z - -z - z - Y b b b 3 Figure 4-: Initial step toward producing the spread-spectrum Σ modulator. The spreadspectrum multiplier pairs are moved according to the dashed arrows. X a + a + a 3 + -z - -z - -z - z - Y b b b 3 Figure 4-3: Intermediate step toward producing the spread-spectrum Σ modulator. The spread-spectrum multiplier pairs continue to be rearranged according to the dashed arrows.

82 63 X a + a + a 3 + -z - -z - -z - z - Y b b b 3 Figure 4-4: Third-order -bit spread-spectrum Σ modulator. The delay-ree and sampledelayed spread-spectrum modulated (SSM) integrator structures are introduced. The dashed arrows in Figures 4- and 4-3 depict the direction in which a particular spread-spectrum multiplier is moved. When the sample-delayed spreadspectrum sequence, e[n-], is pushed through the quantizer, there is no change to the multiplier. The spread-spectrum multiplication simply perorms a sign alternation, so the result is the same whether the operation is perormed in the analog domain beore the quantizer or in the digital domain ater quantization. The structural transormation to produce the spread-spectrum Σ modulator described here may be applied to any traditional Σ modulator to create a spread-spectrum Σ modulator. The spread-spectrum Σ modulator architecture presented in Figure 4-4 incorporates the delay-ree spread-spectrum modulated (SSM) integrator and the sample-delayed SSM integrator structures. These structures take on the same architecture as the mirrored integrator structures proposed in [38]. The circuit schematics or the SSM integrator structures are shown in Figures 4-5 and 4-6 or the delay-ree and the sample-delayed SSM integrators, respectively. The SSM integrators are controlled by the clock sequence shown in Figure 4-7. The clocking sequence consists o two non-overlapping clock phases, φ and φ ; the delayed turn-o phases, φ d and φ d ; and the spread-spectrum chopping signals, φ C and φ C. The delayed turn-o clock signals are used to prevent signal-dependent charge injection onto the sampling capacitors, C s, and integration capacitors, C I [39], [40]. The φ C and φ C signals are also non-overlapping and correspond to the e[n] spread-spectrum sequence and its complement (i.e., when φ C is a logic high, then

83 64 φ C is a logic low and when φ C is a logic low, then φ C is a logic high). Similar to the mirrored-integrator Σ modulator in [3], a distinct advantage o the proposed spread-spectrum Σ modulator is that it is not a major design digression rom mature Σ modulator technology. C I φ d φ d φ φ + C S φ C v in - φ C + φ C φ C + v out - C S φ C + - φ C - φ d φ φ d φ C I Figure 4-5: Delay-ree mirrored integrator structure employed or implementing the delayree SSM integrator. C I φ d φ d φ φ + C S φ C v in - φ C + φ C φ C + v out - C S φ C + - φ C - φ d φ φ d φ C I Figure 4-6: Sample-delayed mirrored integrator structure employed or implementing the sample-delayed SSM integrator.

84 65 φ φ d φ φ d φ C φ C Figure 4-7: Example clocking sequence or the delay-ree and sample-delayed SSM integrators. As it turns out, the models or the delay-ree and sample-delayed SSM integrators shown in Figures 4-5 and 4-6 when driven by the spread-spectrum sequence, e[n], are directly applicable to the high-level spread-spectrum Σ modulator shown in Figure 4-4. These models are depicted in Figures 4-8 and 4-9 or the delay-ree SSM integrator and the sample-delayed SSM integrator, respectively. The models correspond exactly with the SSM integrator structures established by the spread-spectrum multiplier rearrangement described previously. The signal low-graph diagram o the third-order -bit spread-spectrum Σ modulator can be produced using the SSM integrator models rom Figures 4-8 and 4-9. The signal-low-graph or the spread-spectrum Σ modulator will correspond almost identically with the signal low-graph produced in Section 4.3 or the traditional Σ modulator with the addition o several spread-spectrum multipliers. The spread-spectrum Σ modulator signal low-graph is shown in Figure X -z - Y Figure 4-8: Delay-ree SSM integrator model.

85 66 X -z - z - Y Figure 4-9: Sample-delayed SSM integrator model. X C S - = -0. C I C S - = -0.5 z C - = 0.5z I C - I z - -z - C S3 -z - Y C S - = -0. C I C S - = -0.5 C I C S3 z - = 0.5z C - I3 -V DAC V DAC -V DAC V DAC DAC Figure 4-30: Third-order -bit spread-spectrum Σ modulator signal low-graph. The circuit schematic or the third-order -bit spread-spectrum Σ modulator may now be generated rom the signal low-graph. The e[n]e[n-] multiplication with the quantizer output is perormed using two two-input exclusive-or (XOR) unctions. The output rom the two XORs multiplying the quantizer output, e[n], and e[n-] is then used to control the DAC switches, which are active high. Thereore, when the XOR output is logic high, +V REF is connected to +V DAC and -V REF is connected to -V DAC. Alternatively, i the XOR output is logic low, then +V REF is connected to -V DAC and -V REF is connected to +V DAC. Prior to the modulator output there is one last spread-spectrum multiplication, which is perormed by the inal XOR unction in the schematic. The overall circuit schematic or the third-order -bit spread-spectrum Σ modulator is shown in Figure 4-3.

86 Figure 4-3: Third-order -bit spread-spectrum Σ modulator circuit schematic. 67

87 68

88 69 Chapter 5 Spread-Spectrum Sequence Considerations and Simulation Results The material presented in this chapter provides the background inormation regarding the spreading sequence options or the spread-spectrum Σ modulator. Section 5. examines the eect o modulating licker noise, spectral intererers, and DC oset, which occur within the Σ modulator, with dierent spread-spectrum sequences. This analysis provides a methodology or determining the optimum spread-spectrum sequence or a particular Σ modulator. The spreading sequences considered have white noise and blue noise spectral properties. In Section 5., we present a method to eiciently generate dierent order blue noise sequences in the event the modulator requires a blue noise spread-spectrum sequence. Finally, Section 5.3 provides simulation results comparing the third-order spread-spectrum Σ modulator to the traditional Σ modulator. The simulations consider the eects o substrate noise, nonlinear ampliier DC gain, and DAC noise, which were discussed in Chapter 4.

89 70 5. Spreading Sequence Considerations This section provides a method or determining which spreading sequence has the ideal properties or use in the spread-spectrum Σ modulator. We consider spreading sequences with both white noise and blue noise spectral properties. Blue noise is a highpass noise whose spectrum consists o only high requency components. Speciically, the spectrum o a blue noise sequence consists o low requency deiciencies and uncorrelated high-requency luctuations that are classiied as high-requency white noise [4], [4]. The order o the blue noise sequence is deined by the slope o its spectrum roll-o in the transition band (i.e., a band between the pass and stop band). A irst-order blue noise sequence exhibits +0dB/dec roll o in the transition band and each additional order increases the roll o rate by 0 db/dec. Sections investigate the eects o modulating licker (/) noise, a spectral intererer, and DC oset with the various spread-spectrum sequences. Each section includes calculations as well as graphical results to illustrate the indings. Section 5..4 utilizes the results rom Sections to propose a methodology or determining the spread-spectrum sequence required by a speciic Σ modulator. 5.. Eect o Spread-Spectrum Modulation on Flicker Noise This section will discuss the eect o modulation with various spreadspectrum sequences on licker noise. In particular, spread-spectrum sequences with white noise and blue noise spectral properties are considered. The model used to calculate the result o modulating licker noise with the spread-spectrum signal is shown in Figure 5-.

90 7 Figure 5-: Model used to calculate the eect o spread-spectrum modulation on licker noise. The modulation analysis begins by considering the autocorrelation unction or the licker noise process. Flicker noise is a non-stationary process whose autocorrelation unction cannot be derived by the classical Wiener-Khintchine relation [43]. However, as described in [43], by utilizing the method o orderreducing and integrating, an explicit orm o the licker noise autocorrelation unction may be derived. The result is provided in Eq. (5-) or the continuous-time licker noise process, where h - and h correspond to the licker noise power at Hz and the highest requency, respectively. R X ( t, t h ) = h [ 3 + ln π t] 3 + ln t h π t t h t t t = t t (5-) Since the modulation between the licker noise and the spread-spectrum sequence occurs within a switched-capacitor Σ modulator, we need to consider the discrete-time autocorrelation unction or the licker noise. Thereore, t and t rom Eq. (5-) are replaced with nt s and mt s, and h is replaced with the Nyquist requency, s /. The resulting discrete-time autocorrelation unction or the licker noise process is shown in Eq. (5-). R X h ( n, m) = h [ 3 + lnπn] 3 + ln πnm m n n = m n m (5-)

91 7 The autocorrelation or the modulation product o the spread-spectrum process and the licker noise process is shown in Eq. (5-3), assuming the spreadspectrum process, Y, is a discrete-time process. [ Z( nt ) Z( mt )] E[ X ( nt ) Y ( nt ) X ( mt ) Y ( mt )] R Z ( n, m) = E s s = s s s s (5-3) Since the spread-spectrum process and the licker noise process are statistically independent, the autocorrelation unction o the modulation product Z is equal to the product o the individual autocorrelation unctions, as shown in Eq. (5-4), where k = m-n. The analysis contained in this section assumes n >>. Since tenso thousands o samples are typically acquired or Σ modulator measurements, this assumption should be valid. R ( n, m) = R ( n, m) R ( n, m) = R ( n, n + k) R ( n, n k) (5-4) Z X Y X Y + We irst consider using the spread-spectrum sequence with white noise spectral properties. The white noise spread-spectrum sequence is a wide-sensestationary (WSS) process. Thereore, its autocorrelation unction R Y (n,n+k) is independent on time instant n and it is equal to δ[k]. The product o autocorrelation unctions or the white noise spread-spectrum process and the licker noise process is provided in Eq. (5-5). The power spectral density (PSD) calculated rom R Z (n,n+k) is shown in Eq. (5-6). The result indicates that modulating licker noise with a white noise sequence results in a spectrum with white noise spectral properties. R Z [ 3 + lnπn] δ[ ] ( n, n + k) = h k (5-5) S Z WN h [ 3 + lnπn] s s ( j ) =, s (5-6) First-order blue noise is the next spread-spectrum sequence considered. The irst-order dierentiation highpass ilter, (-z - ), is used to produce the irst-order

92 73 blue noise sequence or the calculations. The autocorrelation unction o the irstorder blue noise process is provided in Eq. (5-7). R Y ( k) = δ [ k] δ[ k + ] δ[ k ] (5-7) The autocorrelation unction resulting rom modulating licker noise and irst-order blue noise sequence is shown in Eq. (5-8). In addition, the PSD calculated rom this autocorrelation unction is given in Eq. (5-9). Equation (5-9) indicates that modulating licker noise with a irst-order blue noise sequence results in a spectrum that combines irst-order blue noise component and white noise component. 3 n, n + k) = h + lnπn δ[ k] δ[ k ] δ[ k ] +.64h δ[ k] + (5-8) R Z ( h 3 + lnπn.64h S Z BN ( j ) π = cos + s s s (5-9) The analysis continues by examining the result o modulating licker noise with a second-order blue noise spread-spectrum sequence. Similar to the irst-order blue noise, the second order-blue noise used or the calculations was assumed to be generated by the second-order dierentiation highpass ilter, (-z - ). The autocorrelation unction o the second-order blue noise sequence, R Y (k), is shown in Eq. (5-0). R Y ( k) = δ [ k] δ[ k + ] δ[ k ] + δ[ k + ] + δ[ k ] (5-0) The product o the second-order blue noise autocorrelation and the licker noise autocorrelation is calculated as Eq. (5-) and the resulting PSD is given by Eq. (5- ). The resulting spectrum o licker noise and second-order blue noise modulation

93 74 contains a white noise component as well as irst- and second-order blue noise components. R Z ( n, n + k) = h 3 π n + ln δ [ k] δ[ k + ] δ[ k ] + δ[ k + ] + δ[ k ] + 0.9h δ [ k] δ[ k + ] δ[ k ] +.4h δ [ k] (5-) 3 πn h + ln ( ) π S = cos 3 Z BN j s s π. 4h cos + s s s. h (5-) The inal spread-spectrum signal considered or analyzing licker noise and spread-spectrum modulation is a third-order blue noise. The blue noise was generated by the third-order dierentiation highpass ilter with the transer unction (-z - ) 3. The autocorrelation unction or the third-order blue noise is given in Eq. (5-3). R Y ( k) = δ [ k] δ[ k + ] δ[ k ] + δ[ k + ] δ [ k ] δ[ k + 3] δ[ k 3] (5-3) The PSD or the modulation product o the spread-spectrum process with third-order blue noise spectral properties and the licker noise is shown in Eq. (5-4). The result in Eq. (5-4) indicates that modulating a licker noise process with a thirdorder blue noise process produces white noise, irst-order blue noise, second-order blue noise, and third-order blue noise components.

94 75 h 3 πn + ln 3 3 ( ) π S = cos 3 5 Z BN j s s s h π 0.67h π. 4h cos cos + + s s s s (5-4) To illustrate the results obtained in this section, the PSDs or each o the modulation results are plotted in Figure 5-. This example assumes n = 00,000, h - = -05dB, and s = 00kHz. This igure indicates that or these assumptions, the bestcase thermal noise loor o the spread-spectrum Σ modulator will be between - 44dB and -54dB, depending on the choice o spread-spectrum sequence. Thereore, i the expected thermal noise loor o the Σ modulator deined by the ampliier thermal noise and switch noise power is above -44dB in the baseband, then there should be no perormance degradation caused by modulating the licker noise with any o the spread-spectrum sequences considered. Figure 5-: PSDs or the white noise and irst- through third-order blue noise spread-spectrum sequences modulated with licker noise.

95 76 However, i the expected thermal noise loor o the Σ modulator is below - 44dB in the baseband, then the white noise modulation sequence may not be eicient in spreading the licker noise and a higher order blue noise sequence may be required. A speciic third-order Σ modulator with a thermal noise loor o 49dB is shown in Figure 5-3 along with the results illustrating the PSDs or the various spread-spectrum signals modulating licker noise. Since the thermal noise loor o the Σ modulator example is at 49dB, the white noise modulated licker noise, whose noise loor resides at 44dB, would cause the noise loor o the Σ modulator to increase by 5dB. However, i the spread-spectrum sequence utilized is one o the blue noise signals, whose noise loors are located near -54dB, the Σ modulator output spectrum will remain unchanged. As a result, the spread-spectrum signal with blue noise properties oers a potential beneit over the white noise spread-spectrum signal when considering licker noise. Figure 5-3: White noise and irst- through third-order blue noise modulated with licker noise plotted against the third-order Σ modulator output spectrum.

96 Eect o Spread-Spectrum Modulation on a Spectral Intererer The eect o spread-spectrum modulation on a sinusoidal spectral intererer is examined in this section. The model shown in Figure 5- that is used to calculate the eect o spread-spectrum modulation on licker noise is used again in this section; however, the licker noise process is replaced with a sinusoidal intererence signal with random phase. The random process describing the sinusoidal intererence signal with random phase is show in Eq. (5-5), where the random variable, Θ, is uniormly distributed over the interval [-π, π] and n is the intererence signal requency. X ( t) = Acos(π t + Θ) (5-5) The PSD o the sinusoidal intererence signal with random phase is provided in Eq. (5-6). n A π S X ( j ) = [ δ ( n ) + δ ( + n )] (5-6) s The modulation operation represents multiplication in the time domain or convolution in the requency domain. The analysis provided in this section was done in the requency domain; thereore, the results rom modulating a sinusoidal intererer with the dierent spread-spectrum sequences were ound by convolving the PSDs or the spread-spectrum signals with the PSD o the sinusoidal intererence signal. The PSDs o the white noise and irst- through third-order blue noise spreadspectrum sequences may be inerred rom Section 5... These PSDs are shown in Eqs. (5-7) - (5-0) or the white noise and irst- through third-order blue noise sequences.

97 78, ) ( s s s Y j S WN = (5-7), cos ) ( s s s s Y j S BN = π (5-8), cos 3 ) ( s s s s Y j S BN = π (5-9), cos 5 ) ( 3 s s s s Y j S BN = π 3 (5-0) The PSDs resulting rom modulating the intererence signal with the dierent spread-spectrum sequences are ound by convolving Eq. (5-6) with Eqs. (5-7) - (5-0). Equations (5-) - (5-4) display the results o these convolutions, where P int represents the power o the intererence signal (i.e., P int = A /). s Z P j S WN int ) ( = (5-) = s n s Z P j S BN π π cos cos ) ( int (5-) + = s s n s n s Z P j S BN π π π π cos cos cos cos 3 ) ( int + s s n π π sin sin (5-3)

98 79 + = s s n s n s Z P j S BN π π π π cos 3cos cos 3cos 5 ) ( int 3 + s s n s n π π π π cos cos sin 3sin 3 3 s s n s s n π π π π sin sin cos 3cos (5-4) The PSD results in Eqs. (5-) - (5-4) are plotted in Figure 5-4 to display the modulation result. For this example, we assumed a spectral intererer at n = 60Hz with an amplitude o 4.mV. Based on these assumptions, the results in Figure 5-4 indicate that modulating a spectral intererer with white noise may signiicantly increase the thermal noise loor o the spread-spectrum Σ modulator that is a consequence o the ampliier thermal noise and switch noise power. However, i the expected thermal noise loor o the spread-spectrum Σ modulator is above -50dB, then any o the blue noise sequences appear to be a suitable choice or the spreadspectrum sequence. Figure 5-4: PSDs or the white noise and irst- through third-order blue noise spread-spectrum sequences modulating a 60Hz spectral intererer.

99 80 It is important to consider the actual spread-spectrum Σ modulator that is to be implemented, however. Figure 5-5 presents the output rom the example spreadspectrum Σ modulator considered in Section 5.. plotted with the spectral intererer modulation PSDs rom Figure 5-4. This igure indicates that, although the thermal noise loor or the example modulator and the irst-order blue noise are both approximately -50dB, the corner requency o the modulation result is lower than the cuto requency o the spread-spectrum Σ modulator NTF. As a result, there will be an increase in noise near the NTF cuto requency, which typically corresponds to the edge o the signal bandwidth, creating a decrease in SNR. Thereore, the spread-spectrum Σ modulator in this example should utilize a blue noise spread-spectrum sequence o second-order or higher. In general, though, the spread-spectrum sequences with blue noise spectral properties oer substantial improvement over the white noise sequence when a spectral intererer is alicting the Σ modulator. Figure 5-5: Spectral intererer modulated with white noise and irst- through third-order blue noise plotted against the third-order Σ modulator output.

100 Eect o Spread-Spectrum Modulation on DC Oset This section examines the eect o modulating DC oset with several spread-spectrum sequences. DC oset maniests itsel as a strong spectral intererence signal located within the signal bandwidth at zero requency. The DC oset PSD is provided in Eq. (5-5), where P DC is total power o the oset. S X ( j ) = P δ ( ) (5-5) The modulation operation represents convolution in the requency domain. Thereore, the DC oset PSD in Eq. (5-5) is convolved with the spread-spectrum sequence PSDs provided in Eqs. (5-7) - (5-0) to obtain the PSDs or spreadspectrum modulation with DC oset. The resulting PSDs rom modulating the DC oset process with the dierent spread-spectrum sequences are shown in Eqs. (5-6) - (5-9) or the white noise and irst- through third-order blue noise sequences, respectively. DC S Z WN P DC ( j ) = (5-6) s S Z BN P DC π ( j ) = cos (5-7) s s S Z BN P DC π ( j ) = cos 3 s s (5-8) S Z BN P DC π ( j ) = cos 3 5 s s 3 (5-9) The results rom Eqs. (5-6) - (5-9) indicate that the DC oset signal takes on the spectral shape o the spread-spectrum modulation sequence used to modulate the oset. This result is illustrated in Figure 5-6, which plots the PSDs rom Eqs. (5-

101 8 6) - (5-9), assuming a DC oset o -40dB. The white noise spreading sequence evenly spreads the power contained in the DC signal across all requencies, while the blue noise spreading sequences all shape the DC oset power toward high requency. This result indicates that the blue noise spreading sequences will guarantee less noise power within the signal bandwidth coming rom DC oset as compared to the white noise spreading sequence. Figure 5-6: PSDs or the white noise and irst- through third-order blue noise spread-spectrum sequences modulating DC oset. The Σ modulator example rom Sections 5.. and 5.. will be considered in terms o the DC oset. The NTF o the example spread-spectrum Σ modulator is plotted in Figure 5-7 along with the PSDs rom the DC oset modulation that are shown in Figure 5-6. Figure 5-7 indicates that the white noise and the irst-order blue noise spreading sequences modulated with the DC oset will increase the in-band noise o the Σ modulator. However, the second- and third-order blue noise sequences will attenuate the DC oset to levels that will not alict the Σ modulator

102 83 perormance. As a result, a blue noise sequence o second-order or higher will be required to achieve the desired perormance when considering the eects o DC oset. Overall, since the DC oset is shaped in requency by the spreading sequence, the spread-spectrum sequence that guarantees the DC oset will remain below the noise loor o the particular Σ modulator should be utilized. Figure 5-7: DC oset modulated with white noise and irst- through third-order blue noise plotted against the third-order Σ modulator output Determining the Required Spread-Spectrum Sequence The irst step required or determining the spread-spectrum sequence necessary or the Σ modulator being designed is to simulate the modulator without any spread-spectrum sequence applied. From this simulation the h - licker noise parameter, the spectral intererer power, and the DC oset power are determined.

103 84 Additionally, the thermal noise loor should be estimated so that the proposed algorithm can decide whether or not the choice o spread-spectrum sequence is suicient or suppressing the eect o the nonideal parameter being considered. The next step is to calculate the spectra resulting rom modulating the spread-spectrum sequences with the expected licker noise, spectral intererer, and DC oset. These calculations should begin with the white noise spreading sequence and move to the irst- and increasing order blue noise sequences. The irst sequence that reduces the eects o the nonideality enough so that its power remains below the thermal noise loor represents the minimum-order spreading sequence required or the particular nonideality. Once the minimum spreading-sequence order or each nonideality is obtained, the required spreading sequence is determined by selecting the highest order o the three spreading sequences. Selecting the highest order sequence required by the individual modulation results guarantees that the eects rom each o the nonidealities will be reduced below the thermal noise loor o the Σ modulator. Figure 5-8 displays a low graph that illustrates the decision process. Sections depict the eects o licker noise, a 60Hz spectral intererer, and DC oset ater modulation with the dierent spread-spectrum sequences. These results were obtained using the simulation results o the third-order spread-spectrum Σ modulator designed in Chapter 4. The thermal noise loor assumed or the simulations was very optimistic; however, this value assures us that the spread-spectrum sequence required to suppress the nonidealities below this thermal noise loor will also suppress them below the actual thermal noise loor. Based on the calculations and igures shown in Sections , the spreadspectrum sequence required or the third-order spread-spectrum Σ modulator is the second-order blue noise sequence.

104 85 Simulate Σ Modulator Thermal Noise Flicker Noise Spectral Intererer DC Oset a a a b b a < b a < b No No No a < b b Yes Yes Yes Max Order Required Spreading Sequence Figure 5-8: Spread-spectrum sequence selection low graph. 5. Blue Noise Generation According to Section 5., blue noise is characterized as a random signal whose spectrum contains a deiciency o low requencies and consists o high requency white noise. The quantization noise shaping characteristic o a lowpass Σ modulator may be used to produce a sequence with a blue noise spectrum. The order o the blue noise sequence corresponds to the order o the lowpass Σ modulator.

105 86 The digital Σ modulator architecture is well suited or generating the blue noise sequence due to its simple implementation. Since the blue noise sequence used or the spread-spectrum Σ modulator is a binary sequence o s and - s, the digital Σ modulator should utilize a -bit quantizer. We propose an adaptable N th -order -bit all-digital Σ modulator architecture in this section that is used to generate the N th -order blue noise sequence. Replacing the integrators rom a traditional Σ modulator with accumulators and the DAC with a digital code converter creates the all-digital Σ modulator. The N th -order digital Σ modulator architecture implemented in this text is shown in Figure 5-9. The -bit digital Σ modulator is adequate or this application since the spread-spectrum Σ modulator requires a binary blue noise sequence. Similar algorithms that produce blue noise sequences have been proposed or ractional-n PLL applications [44] and or DAC dynamic-element matching in multi-bit Σ ADC applications [45]. However, the structures commonly used in ractional-n PLL applications are cascaded Σ modulators, which produce a multi-bit output [46]. Due to this, a unique design was required so that higher-order single-bit digital Σ modulators may be implemented. Dither + a N- a Y b N z - z - b b z - z - Digital Code Converter Figure 5-9: N th -order -bit all-digital Σ modulator loop topology implemented. The digital Σ modulator depicted in Figure 5-9 is a single-loop N th -order structure, which indicates that considerations must be made to ensure modulator stability when N is greater than two. Thereore, appropriate choices or the a i and b i

106 87 coeicients should be made. The coeicients were selected to be / k, k =,,, N. This coeicient selection allows multiplication with the coeicients to be easily implemented as a shit right N-times unction. Table 5- lists the coeicient values corresponding to Figure 5-9. Coeicient Value a = b / a = b /4... a N- = b N- / N- b N... / N Table 5-: Coeicient values or all-digital N th -order Σ modulator. The greatest advantage o the proposed digital Σ modulator architecture is its order adaptability. Lower- and higher-order digital Σ modulators are easily constructed rom the proposed architecture. Beginning with the irst-order digital Σ modulator, the N th -order digital Σ modulator is constructed by adding N- stages to the let-hand side o the irst-order modulator. The coeicients o the added stages continue to decrease by a actor o two as additional stages are added. Also, a lowerorder digital Σ modulator is constructed by removing stages rom the let-hand side until the desired order Σ modulator is obtained. 5.. Blue Noise Generator Implementation The irst step to implementing the -bit second-order all-digital Σ modulator is high-level unctional description o the modulator in Matlab. Once the high-level description is complete and the modulator unctionality is veriied, the

107 88 design is coded or implementation on an FPGA using VHDL. The FPGA used to implement a hardware realization o the digital Σ modulator is the Altera Cyclone II EPC35F that resides on the DE evaluation board. An external clock was preerred over the on-board clock in order to allow or easy implementation o a variety o sampling (i.e., clock) requencies. The VHDL implementation o the digital blocks is described in the ollowing text. The addition and subtraction nodes in Figure 5-9 are implemented as signed 4- bit adders and subtractors. Additionally, the z - delay elements are designed to be 4- bit D-Flip-Flops. The Digital Code Converter output values with the appropriate bitwidth or each eedback path were speciied in the VHDL code and selected based on the previous modulator output value. Finally, the dither signal is generated using 6-bit linear eedback shit registers (LFSRs). Each LFSR is identical except or the initial seed provided. Thereore, each one produces a dierent pseudo-random sequence that repeats every clock cycles. The dither signal is constructed as the parallel result rom the LFSRs on each clock cycle. High-level Matlab simulations were used to determine that an -bit dither signal prevents adder and subtractor overlow rom occurring, which could corrupt the output sequence. Also, the use o a dither signal eliminates any idle tones - also known as limit cycles - that may be present in the output spectrum. The spectrum o the -bit second-order alldigital Σ modulator implemented on the Altera FPGA evaluation board utilizing a sampling requency o 00kHz is shown in Figure 5-0. Although the -bit second-order all-digital Σ modulator was not implemented on-chip, the required area and power overhead can be approximated rom similar designs utilized in requency synthesizer applications [47], [48]. In particular, the design in [47] utilizes a third-order digital Σ modulator implemented in a 0.35µm CMOS process. The modulator is clocked at 3MHz and occupies an area o 0.8mm and consumes 0.7mW o power rom a.5v supply. This translates to a power consumption o 0.04mW rom a 5V power supply with the modulator utilizing a clock rate o 00kHz, as required by the spread-spectrum Σ modulator.

108 89 Figure 5-0: Blue noise spectrum obtained rom the second-order all-digital Σ modulator implemented on Altera FPGA. 5.3 Third-Order Spread-Spectrum Σ Modulator Simulation Results The behavioral simulation results presented here were obtained rom Matlab/Simulink models o the third-order -bit spread-spectrum Σ modulator designed in Chapter 4. The simulation parameters correspond to those used in Section 4. or the traditional Σ modulator. The input signal utilized in the simulations is a 0.7V amplitude sinusoidal signal with requency in = 00Hz lying

109 90 within a 500Hz bandwidth. The OSR was selected to be 00, resulting in a sampling requency o s = 00kHz. The substrate coupling noise is simulated by injecting attenuated square waves containing the sampling clock requency as well as higher harmonics and sub-harmonics into the irst integrator in the Σ modulator. Additionally, the nonlinear ampliier DC gain results presented in Section are included in the model or the irst integrator. In order to provide realistic simulations, non-ideal ampliier models were used or the integrators. The simulations were perormed assuming room temperature, a inite ampliier gain (63dB), inite gainbandwidth (50MHz), slew rate (0V/µs), and saturation. In addition to the ampliier non-idealities, clock jitter was also taken into account. The output spectrum o the traditional third-order -bit Σ modulator assuming the nonidealities previously described is shown in Figure 5-. The modulator s vulnerability to low-requency noise as well as even- and odd-order harmonics rom the nonlinear ampliier gain are evident in the output spectrum. These nonidealities limit the SNDR to 7.8dB in simulation. The output spectrum o the third-order -bit spread-spectrum Σ modulator, shown in Figure 5-, indicates that this architecture suppresses the low-requency distortions near DC rom the substrate noise as well as the even-order harmonics created by the nonlinear ampliier gain. The low-requency noise and the input signal second harmonic are spread as a wideband noise across the entire requency range [- s /, s /]. The result o this is an increase in the noise loor o the spread-spectrum Σ modulator. Despite the noise loor increase, the resulting SNDR or the spread-spectrum Σ architecture using the same parameters as the traditional Σ modulator is 8dB. The proposed architecture demonstrates a 0.dB improvement in SNDR rom the traditional Σ modulator design, which translates to an increase in eective resolution o.4 bits. Simulations were also perormed to demonstrate the eects o DAC noise on the Σ modulator. In order to simulate DAC noise, a 60Hz sinusoidal signal was injected onto the positive DAC reerence voltage. The simulations were conducted with no input signal in order to distinguish the eects o the DAC noise. The output

110 9 spectrum o the traditional third-order -bit Σ modulator in the presence o DAC noise is shown in Figure 5-3. The noise on the positive DAC voltage maniests itsel as a spectral intererence signal at 60Hz as well as harmonics o 60Hz. However, as shown in Figure 5-4, the output spectrum o the third-order spreadspectrum Σ modulator does not contain these spectral intererers. These results indicate that the spread-spectrum Σ modulator is not aected by noise on the DAC reerence voltage. Figure 5-: Output spectrum o third-order Σ modulator where low requency noise as well as the second and third harmonics o the input are visible.

111 9 Figure 5-: Output spectrum o third-order spread-spectrum Σ modulator where only the third harmonic o the input is visible. Figure 5-3: Output spectrum o the third-order Σ modulator in the presence o DAC noise.

112 93 Figure 5-4: Output spectrum o the third-order spread-spectrum Σ modulator in the presence o DAC noise.

113 94 Chapter 6 Experimental Results An experimental prototype o the third-order -bit spread-spectrum Σ modulator has been abricated according to the design described in the preceding chapters. The modulator layout was completed in Cadence design tools using the TSMC 0.35µm -poly/4-metal CMOS process and was abricated through the MOSIS service. This CMOS process enables thick oxide transistors, allowing or power supply voltages up to 5V. Using a 5V power supply, the prototype modulator dissipates 3.5mW o power; however, this igure does not include the control logic, which was not integrated on chip or this prototype design. The experimental results or the prototype modulator are presented in this chapter.

114 95 6. Implementation This section describes the core circuitry utilized in the design o the -bit third-order spread-spectrum Σ modulator prototype. The opamp and accompanying common-mode eedback (CMFB) circuit are described and measurement results are provided. In addition, the comparator implemented in the prototype modulator is described. This section concludes with a description o the CMOS switches implemented and an analysis o the noise they contribute to the sampling capacitors. 6.. Operational Transconductance Ampliier The prototype modulator designed in this thesis was or proo-o-concept purposes and was not targeted or cutting-edge perormance in terms o speed, power consumption, and noise perormance. Thereore, in order to achieve this goal, we decided to use an operational transconductance ampliier (OTA) design that we previously developed and tested in the 0.35µm technology or switched-capacitor accelerometer readout applications. The implemented OTA was chosen to be the ully-dierential olded-cascode OTA topology. The implemented OTA is shown in Figure 6-, and the measured perormance parameters rom the abricated oldedcascode OTA are provided in Table 6-. The perormance speciications o concern or the OTA are the DC gain, unity-gain requency, and settling time. The DC gain o the implemented OTA is greater than 60dB, which is shown to be a minimum required gain or highresolution designs [4]. The overall settling characteristics are dependent on the unitygain requency and the settling time o the OTA. Typical OTA settling deines 0.% settling accuracy to require approximately 7τ settling time, where τ is the circuit time constant.

115 96 V ctrl V b V b V in + + V out V in V b3 V b4 Figure 6-: Folded-cascode OTA schematic. Perormance Parameter DC Gain Unity Gain Frequency Dominant Pole Frequency Slew Rate Transconductance (g m ) DC Oset Thermal noise Flicker Noise Value 6dB 6.6MHz 5.5kHz 5V/µs ma/v.6mv dbv /Hz Hz -05 dbv 0Hz -5 dbv 00Hz -5 dbv Table 6-: Folded-cascode OTA perormance measured results. Since the integrator to be implemented with this OTA operates during every hal o the sampling period, then 7τ settling time is required to be less than hal the sampling clock period. According to calculations, the minimum unity-gain requency

116 97 o the OTA should be at least.7 times the sampling requency o the Σ modulator prototype [7]. Consequently, when a sampling requency o 00kHz is used or the modulator, the OTA should have a unity-gain requency o at least 540kHz. Thereore, the unity-gain requency o the implemented OTA, which is measured to be 6.6MHz, is more than suicient to ensure good settling accuracy. The switched-capacitor CMFB circuit shown in Figure 6- was implemented or the ully-dierential olded-cascode OTA. This circuit is necessary because it establishes the common-mode output voltage o the OTA since this value is not well deined by the eedback circuitry typically applied to the OTA (i.e., the eedback only speciies the dierential signal voltages). The CMFB circuit in Figure 6- acts like a simple switched-capacitor lowpass ilter with a DC input signal [7]. V b4 V ctrl V ctrl C C C C V out V out + V re Figure 6-: Switched-capacitor common-mode eedback circuit.

117 Comparator The comparator utilized in the Σ modulator prototype is the regenerative latched comparator design proposed in [49]. This comparator design consists o a dierential preampliication stage at the input, a regenerative latch circuit, and an SR latch at the output. The preampliier senses the voltage dierence between the input signals, which is ampliied to levels near the power supply rails by the regenerative latch. The SR latch then drives these signals to ull complementary output levels. The schematic or the implemented comparator is shown in Figure 6-3. Simulation results indicate that the comparator operates at sampling requencies over 40MHz, which is more than suicient or the prototype modulator. c c S R c c R Out I bias V in + V in S Out Figure 6-3: Regenerative latched comparator schematic.

118 Switches and Switch Noise The switches employed throughout the switched-capacitor spread-spectrum Σ modulator prototype were all implemented as transmission gate CMOS switches with the aspect ratios provided in Table 6-. The CMOS switches were implemented with relatively large transistors to ensure the on-resistance o the switch was small and as near constant as possible across the entire voltage range. This guaranteed that the switches would not limit the overall operating speed o the prototype modulator. The on-resistance as a unction o the input voltage applied to the switch is shown in Figure 6-4. Aspect Ratio PMOS NMOS 8µm/0.5µm 6µm/0.5µm Table 6-: Transmission gate transistor sizings. Figure 6-4: Simulated on-resistance o the CMOS switch as a unction o input voltage.

119 00 The other important perormance parameter o the CMOS switches is the sampling noise that is associated with the switched capacitor structure. A simpliied representation o the input sampling network to the switched-capacitor Σ modulator prototype is depicted in Figure 6-5a during the sampling phase. Modeling the MOS switch as a resistor produces the circuit shown in Figure 6-5b, where R on is the equivalent on- resistance o the switch and V N () is a noise voltage equal to the thermal noise voltage o a resistor with the power spectral density speciied in Eq. (6-). s V out R on V out. C s V n( ) C s (a) (b) Figure 6-5: (a) Simpliied input sampling network, and (b) the circuit model or calculating the switch noise. v n ( ) = 4kTR on (6-) The RC network ormed in Figure 6-5b creates a lowpass ilter, with magnitude-squared value o the requency response given in Eq. (6-), that eectively ilters the resistor thermal noise, V N (). The total noise power at the output ater lowpass iltering is provided in Eq. (6-3) as H ( jω) v out. = + ( ω R C ) (6-) on s kt v out = C s (6-3)

120 0 The resulting sampling noise power is spread as a white noise across the entire spectrum (rom - s / to s /). However, since the Σ modulator prototype operates as an oversampling device, the total noise power appearing within the signal bandwidth will be reduced by a actor equal to the oversampling ratio, M. Additionally, since the modulator is implemented as a ully-dierential structure where two sampling capacitors are employed, the total noise power will be doubled since each capacitor contributes an equal amount o noise. Finally, since the charge sampling and transer occur during two separate clock phases, the sampling noise is contributed equally during both phases. Since the sampling noise voltages introduced during the separate sampling and transer phases are uncorrelated, their noise powers add. Thereore, the noise power is multiplied by an additional actor o two. The overall sampling noise power or the prototype spread-spectrum Σ modulator is provided in Eq. (6-4). v out 4kT = (6-4) MC s The result rom Eq. (6-4) is useul during the design procedure since the result allows the minimum size sampling capacitors required to achieve a speciic thermal noise target to be calculated. The total in-band sampling noise power or the modulator prototype was chosen to be no larger than -00dB at an oversampling ratio o 00. Using this value, the minimum sampling capacitor size was determined to be 0.88pF. In order to provide a margin o error and reduce charge injection rom the relatively large switches implemented, the minimum capacitor size or the input sampling capacitors was chosen to be pf. Smaller capacitor values may be used or the sampling capacitors o the second and third integrator stages since the total baseband noise contributed rom these stages is considerably less than the contribution rom the irst stage []. The capacitor values corresponding to the thirdorder -bit spread-spectrum Σ modulator schematic rom Figure 4-3 are listed in Table 6-3. These capacitor values implement the necessary coeicients according to

121 0 Table 4-8 when the capacitor ratios given in the signal low-graph diagram o Figure 4-30 are used. Stage Stage Stage 3 C S = C F = pf C S = C F = pf C S3 = C F3 = pf C I = 0pF C I = 4pF C I3 = pf Table 6-3: Capacitor values or the third-order -bit spread-spectrum Σ modulator. 6. Prototype Layout A chip photograph o the abricated prototype is shown in Figure 6-6. In an attempt to simpliy and expedite the design, the same ampliier design was used or all three modulator stages. The only adverse impact this has on the prototype s perormance is an increase in power consumption over the design utilizing more optimized, less power hungry second and third stage ampliiers. Since the prototype design is ully-dierential, common-mode disturbances are expected to be rejected; however, special attention was given to assure symmetry in the layout, which also helps to reject common-mode disturbances. The experimental prototype utilizes a single 5V power supply or both the analog and digital circuitry. In addition, the analog and digital circuits share a common ground. Typically, the analog ground is separated rom the digital ground in order to reduce the amount o switching activity that is coupled into the substrate [50], [36]. However, it was a goal o this work to demonstrate the ability o the spread-spectrum Σ modulator to reduce the eects o substrate coupling noise and power supply noise on the analog circuitry.

122 03 Figure 6-6: Chip photograph o the prototype spread-spectrum Σ modulator. The TSMC 0.35µm CMOS process used to abricate the spread-spectrum Σ modulator prototype is a -poly/4-metal technology, which enables the use o polypoly capacitors. The required capacitor sizes determined during the design phase were ormed using unit size capacitors. This technique is eective at ensuring accurate capacitor ratios [5]. In addition, 90 corners were avoided in the unit capacitor layout to avoid pattern errors when etching the poly- [5]. The unit capacitor used has a nominal capacitance o 50F and is shown in Figure 6-7. Interconnecting 0, 40, 80, and 00 unit capacitors, we assembled the required pf, pf, 4pF, and 0pF capacitors, respectively. Since the capacitance per unit area or the poly-poly capacitor was on the order o 0.9F/µm, the 50F unit capacitor occupies an area o approximately 56µm [53].

123 04 8µm Poly Poly 8µm Figure 6-7: 50F unit capacitor layout. 6.3 Experimental Test Setup An evaluation board was constructed or testing the spread-spectrum Σ modulator prototype. The spread-spectrum Σ modulator is packaged in a 64-pin LQFP package that is directly soldered onto the evaluation board. The diagram o the entire experimental test setup is shown in Figure 6-8. The equipment required or testing the prototype modulator is also listed in the igure. The voltage regulator generates the power supply or the experimental prototype rom an external 9V battery. The voltage reerence is also powered by the voltage regulator and supplies the.5v common-mode voltage or the prototype. Each supply and reerence voltage line entering the prototype is bypassed with a 0.µF capacitor as close to the package as possible. The input signals to the prototype were generated using an ultra-low distortion unction generator with dierential output capability.

124 05 Evaluation Board D Voltage Regulator Voltage Reerence E +5V Gnd +.5V Voltage Source V+ V- Vdd Gnd Vcm Vrep C Signal Generator Vop Von Vip Vin DUT Out Out Vren Clk Clk N Clk ss Clk ss... Buers F A Signal Generation Out Logic Analyzer Out N FPGA B PC Export Data Acquisition In In A: Agilent 6903A Logic Analysis System B: Altera DE Evaluation Board (with Cyclone II FPGA) C: Stanord Research Systems DS360 Signal Generator D: Linear Technology LT086 CT-5 Voltage Regulator E: Analog Devices ADR44 Voltage Reerence F: Texas Instruments SN74HCT573N Transparent D-Type Latch Figure 6-8: Experimental test setup.

125 06 The periodic clocks required by the spread-spectrum Σ modulator prototype were generated using a logic analyzer, as shown in Figure 6-8. These signals correspond to the clock signals required by the circuit schematic in Figure 3-3. The FPGA is used to produce the blue noise sequence required or the spread-spectrum modulation. In order to ensure a proper synchronization o the blue noise sequence and the periodic clocks, the logic analyzer supplies the FPGA with a reerence clock signal. This reerence signal is used by the FPGA as its master clock triggering the FPGA to output data at the same rate as the logic analyzer. The FPGA output is a 3.3V signal, requiring it to be buered up to 5V prior to entering the prototype. This buer is provided on the evaluation board. The output rom the spread-spectrum Σ modulator prototype is a -bit data stream clocked at the sampling rate o the modulator. The data stream is collected by the logic analyzer and saved to a ile, which is then processed in the PC by Matlab. An example output spectrum that was acquired rom the prototype evaluation board is shown in Figure 6-9. The spread-spectrum Σ modulator prototype was sampled at 00kHz and the input signal applied was a 00Hz 00mV peak-to-peak sinusoidal waveorm.

126 07 Figure 6-9: Spread-spectrum Σ modulator prototype output spectrum with 00Hz 00mV peak-to-peak sinusoidal input signal. 6.4 Measured Perormance 6.4. SNR and SNDR The measured SNR and SNDR versus input signal amplitude are shown in Figure 6-0. As this igure indicates, the peak SNR and SNDR are 85.dB and 8.7dB, respectively. The measurements were taken by sweeping the amplitude o a

127 08 00Hz sinusoidal input signal while the modulator sampled at 00kHz. The DR was measured to be 94dB, which is also shown in Figure 6-0. Figure 6-0: Measured SNR and SNDR versus input signal amplitude Substrate Noise In order to demonstrate substrate coupling noise reduction capabilities o the spread-spectrum Σ modulator, the design plan was to introduce an external noise source into the substrate and observe its eects on the modulator s perormance. Unortunately, an oversight during the layout design procedure o the third-order - bit spread-spectrum Σ modulator was made rendering the measurement o the substrate noise eects impossible. A resistive p-type substrate contact was ormed surrounding the entire Σ modulator. In addition, the substrate contact was provided a pin on the chip where the external noise source was to be connected. However, the

128 09 substrate contact was in close proximity to several grounded guard rings around the on-chip capacitors. As a result, all o the injected noise current lowed through the least resistive path immediately to ground. Thereore, the injected substrate noise was undetectable even when the prototype implemented a conventional Σ modulator Feedback DAC Noise The ability o the spread-spectrum Σ modulator prototype to suppress noise present on the eedback signals rom the DAC has also been experimentally evaluated. As stated in Section 4.4., although the input signal and eedback DAC signal are linearly combined, the DAC signal experiences one ewer spread-spectrum modulation than the input signal. Thereore, the DAC noises and intererences are expected to be spread as a wideband noise, while the input signal is demodulated to baseband. In order to test the DAC noise suppression capability o the spread-spectrum Σ modulator prototype, we injected a 5mV amplitude, 60Hz sinusoidal signal into the positive DAC reerence voltage. This signal was used to emulate the eects o electromagnetic intererence and power line noise that may be coupled onto the DAC reerence voltage. In order to conclusively observe that the spread-spectrum Σ modulator removes the eedback DAC noise, a comparison was made by applying the identical DAC signal with injected sinusoidal noise to the conventional Σ modulator that does not employ spread-spectrum modulation. The response o the conventional Σ modulator or the comparison was obtained rom the spreadspectrum prototype modulator by holding the modulation sequence constant and equal to one. Figure 6- indicates that the spread-spectrum prototype modulator greatly attenuates noise on the eedback DAC reerence voltage in comparison to the conventional Σ modulator.

129 0 The result in Figure 6- also indicates several additional beneits o the spread-spectrum Σ modulator over the conventional Σ modulator. The DC oset present in the conventional Σ modulator is attenuated by approximately 50dB in the spread-spectrum Σ modulator. In addition, Figure 6- demonstrates that the spread-spectrum Σ modulator is eective at removing the licker noise component that dominates the modulator s low-requency response in conjunction with the DC oset. Additionally, unlike traditional chopper-stabilized Σ modulators, the spreadspectrum Σ modulator is not prone to intermodulation products between the periodic chopping clock and the modulator output [54]. Figure 6-: Output spectra o the conventional Σ modulator (top) and spread-spectrum Σ modulator (bottom) with 60Hz DAC noise present.

130 6.5 Perormance Summary This chapter has veriied the overall unctionality o the prototype spreadspectrum Σ modulator. In addition, the eectiveness o the spread-spectrum Σ modulator prototype at removing several undesirable noise and intererence sources rom the modulator output has been demonstrated. The perormance results or the prototype spread-spectrum Σ modulator are summarized in Table 6-4. The experimental results also veriy the DAC noise suppression, DC oset reduction, and licker noise removal capabilities o the spread-spectrum Σ modulator. Perormance Parameter Sampling Frequency Signal Bandwidth Value 00kHz 500Hz Oversampling Ratio 00 Peak SNR, SNDR Dynamic Range 85.dB, 8.7dB 00Hz) 94dB Chip Area.3mm Power Consumption Supply Voltage Process 3.5mW (w/o control logic) 5V TSMC -poly/4-metal 0.35µm CMOS Table 6-4: Spread-spectrum Σ modulator prototype chip perormance summary.

131 Chapter 7 Bandpass Σ ADC Designs Utilizing Spread-Spectrum Techniques The spread-spectrum technique in Σ analog-to-digital conversion is not limited to the lowpass Σ modulators described in the previous chapters. This chapter presents several bandpass Σ ADC designs in which the spread-spectrum technique has been employed. Section 7. presents a two-path bandpass Σ modulator that utilizes a three-path structure to eliminate the mirror image signal within the signal bandwidth. The mirror image is created by the inherent path mismatch in the abricated two-path modulator. The proposed design is shown to be eective at removing the mirror image signal rom the signal bandwidth by relocating the image outside the bandwidth. However, it is possible or out-o-band spectral intererers to be modulated into the signal bandwidth. As a result, the twopath bandpass Σ modulator described in Section 7. was developed. This modulator utilizes a capacitor path randomization scheme within the individual resonator structure that eectively spreads the mirror image signal as well as out-o-band

132 3 spectral intererers as a wideband noise. The capacitor path randomization scheme employed is one with spread-spectrum properties. Finally, Section 7.3 presents a technique employing a spread-spectrum sequence with band-stop spectral properties to reduce the eects o substrate noise on bandpass Σ modulators. The methodology or designing the resonators necessary or band-stop noise modulation is presented and several resonator structures are described in detail. Additionally, a method to design the overall bandstop noise modulated bandpass Σ modulator is presented. It is shown through behavioral simulations that the proposed design is eective at removing spectral intererers, including those created by substrate noise, rom the signal bandwidth. 7. Bandpass Σ Modulator Utilizing 3-Path Resonator Structures In recent years, much research has gone into early digitization o signals in communication systems. This has been caused, in part, by the amount o digital signal processing required by certain communication protocols and modulation schemes. Fortunately, modern advances in CMOS technologies have allowed analog circuit designers to begin looking toward signal processing at high requency bands popular to existing communication systems. In particular, bandpass Σ modulators allow or analog-to-digital conversion in IF and RF bands within these systems. Although several techniques exist or designing bandpass Σ modulators, a popular approach is through the use o a two-path structure. However, typical two-path bandpass Σ modulator architectures suer rom path mismatch due to CMOS component and process variations. The most common eect o path mismatch is an

133 4 attenuated mirror image o the input signal located symmetrically about s /4 in the output spectrum. Previous bandpass Σ modulator designs have made attempts at either suppressing the mirror image by accurately controlling path matching within the modulator structure [55], or adjusting the path sampling requency such that the mirror image signal produced is slightly out o the signal band o interest [56]. The approach proposed in [55] is innovative; however, the improvement was modest at best. Although the Σ modulator proposed in [56] removes the mirror image rom the signal band, the quantization noise shaping is reduced due to the displacement o the Noise-Transer-Function (NTF) notch requency. Thus, it requires twice as many op-amps as the structure where the notch o the NTF is at s /4. For this reason, we sought a design that would attenuate the mirror image signal down to the surrounding noise loor while maintaining a reduced number o required op-amps. A new two-path Σ modulator design is described in the ollowing sections with a speciic look at a pseudo-two-path bandpass Σ modulator. 7.. Mirror Image Generation Mechanism and Theory The well-known advantage o N-path bandpass Σ modulators is that the sampling rate o each path is reduced by N relative to the throughput rate o the entire structure. This allows or relaxed op-amp speciications such as settling time and bandwidth. These are particularly useul advantages since they allow placement o the Σ ADC closer to the antenna in current communications systems [57]. In these applications, a bandpass input signal is commonly sampled at the requency that is N times higher than the input signal center requency. However, the drawback o N-path bandpass Σ modulators is that path mismatch may create a mirror image signal located symmetrically about s /N rom the desired signal.

134 5 In order to explain the appearance o the mirror image, we model the N-path Σ ADC structure in a way such that the input signal samples are multiplied by a gain-error sequence. Each sample o the gain-error sequence is equal to the gain o the corresponding path in the N-path structure. Thus, the output o the modulator is eectively the input signal modulated by a gain-error signal o the orm shown by Eq. (7-). g[ nt s N = ] = k 0 G( k) e πkn j N (7-) The gain-error signal eectively places copies o the input signal spectrum at requency locations k s /N in the output spectrum, where k is speciied in Eq. (7-). For the particular case o a two-path bandpass Σ modulator where the input signal is sampled at the requency our times higher than its center requency, the output spectrum ater gain-error modulation is deined by Eq. (7-). Y ) = G(0) X ( ) + G() X ( ) (7-) s out ( This is illustrated in Figure 7-(b), where Figure 7-(a) corresponds to the input signal spectrum. It can be seen that the mirror image is modulated back to s /4, thus corrupting the input signal. It has been shown that, in general, a mirror image would old back into the signal band i the gain-error sequence, which is associated with the path-mismatch, has at least one requency component that is an integer multiple o the input signal center requency. We propose to introduce the third path while retaining the sampling requency that corresponds to the two-path structure. As a result, the input signal remains centered at s /4, which corresponds to the two-path structure, while the mirror image is pushed out o the signal band to locations at s / and 5 s /, as shown in Figure 7-(c). In this case, the gain-error sequence consists o DC, s /3, and

135 6 s /3 requencies, which modulate the mirror image out o the signal band. The resulting output spectrum is deined by Eq. (7-3) and displayed in Figure 7-(c). Y out s s ( ) = G(0) X ( ) + G() X ( ) + G() X ( ) (7-3) 3 3 The proposed approach helps to reduce the eects o the mirror image signal present in the output spectrum. We have shown that the mirror image locations or the three-path Σ modulator design are guaranteed to be outside the signal band o interest provided the OSR is greater than. The result o the proposed three-path structure is a much-improved SFDR over the typical two-path structure. X(jθ) (a) -s/ -s/4 s/4 s/ Yout(jθ) [-path] (b) -s/ -s/4 s/4 s/ Yout(jθ) [3-path] (c) s/ 5s/ -s/ -s/4 s/4 s/ Figure 7-: (a) Input signal spectrum. (b) Two-path output spectrum. (c) Three-path output spectrum.

136 7 7.. Modulator Operation We propose an improvement o the pseudo-two-path bandpass Σ modulator proposed in [58], such that a third path is introduced in the existing bandpass ilter (resonator). The improved three-path resonator is shown in Figure 7-. The design operates as a double-sampling, pseudo-two-path bandpass ilter based on [58], with an additional input path realized by adding a pair o sampling capacitors. This, in turn, simpliies the clocking sequence. The operation o the proposed doublesampling pseudo-three-path bandpass ilter is described in detail below. 3 Ca 3 3 Cs5 3 Cb 3 Cs3 3 3 Cc 3 Vin Cs Cs Vout 3 Cs4 Cs Cc Cb 3 Clk Clk Clk3 3 3 Ca 3 Figure 7-: Proposed double-sampling pseudo-three-path bandpass ilter along with the operational clock sequence.

137 8 The double-sampling structure operates such that during one clock phase, the input is being sampled, while the previous input signal value is being transerred to the charge storage capacitors o the resonator. In this design, the sampling capacitor pairs: Cs, Cs; Cs3, Cs4; and Cs5, Cs6 and the charge storage capacitor pairs: Ca, Ca; Cb, Cb; and Cc, Cc are controlled by clock signals Clk, Clk, and Clk3, which are also shown in Figure 7-. For simplicity, assume that the values o all capacitors are equal. To analyze the operation o the resonator, the circuit can be broken into three circuits associated with the dierent clock cycles. First, consider the circuit corresponding to Clk at time instance n, which is shown in Figure 7-3. V in (n) is sampled to Cs, Cs. Additionally, Cs3, Cs4 and Cb, Cb perorm charge transer to Cc, Cc, which are connected as eedback capacitors. This operation yields the expression or v out (n) shown by Eq. (7-4). vout ( n) = vin ( n ) vout ( n ) (7-4) During this clock cycle, Cb, Cb become completely discharged, preparing them or storage during the next clock cycle. Additionally, capacitors Ca, Ca store v out (n-).

138 9 Ca Cb Cs5 Cc Cs3 + - Vin Cs Cs - + Vout Cs4 Cs6 Cc Cb Clk Clk Clk3 Ca Figure 7-3: Double-sampling pseudo-three-path bandpass ilter during Clk clock phase. Next, consider the operation during Clk at time instance n+, depicted by Figure 7-4. V in (n+) is sampled to Cs5, Cs6, while v in (n) stored on Cs, Cs and v out (n-) stored on Ca, Ca, are transerred to the eedback capacitors Cb, Cb. Once this charge is transerred, Ca, Ca are discharged, preparing them or storage during the ensuing clock cycle. The resulting expression or v out (n+) is Eq. (7-5). vout ( n + ) = vin ( n) vout ( n ) (7-5)

139 0 Ca Cb Cs5 Cc Cs3 + - Vin Cs Cs - + Vout Cs4 Cs6 Cc Cb Clk Clk Clk3 Ca Figure 7-4: Double-sampling pseudo-three-path bandpass ilter during Clk clock phase. The inal clock stage o consideration, Clk3 at time instance n+, shown by Figure 7-5, ollows the analysis o the previous stages resulting in the expression or v out (n+) seen in Eq. (7-6). v out (n + ) = v (n + ) v (n) (7-6) in out

140 Ca Cb Cs5 Cc Cs3 + - Vin Cs Cs - + Vout Cs4 Cs6 Cc Cb Clk Clk Clk3 Ca Figure 7-5: Double-sampling pseudo-three-path bandpass ilter during Clk3 clock phase. A generalized equation or the resonator s output voltage can be generated rom this analysis. The result is Eq. (7-7), where k is an integer value. The resulting z-domain transer unction or the ilter described above is given by Eq. (7-8). vout ( n + k) = vin ( n + k ) vout ( n + k ) (7-7) z H ( z) = (7-8) + z

141 Similar to the design proposed in [58], each path is chosen once in three consecutive samples. The resulting noise components generated by the path mismatch will lie at s /3, s /3, and s. These noise peaks are ar rom the input signal band at s /4 when the OSR is greater than, which means that the proposed resonator design is insensitive to capacitor path mismatch. The preceding analysis clearly illustrates the double-sampling and pseudo-three-path operation o the resonator circuit. Also, as the circuit operation continues, it is clear how the operation cycles through all three paths o the resonator, thus eliminating the mirror image around s / Modulator Design As concluded earlier, in order to avoid mirror image creation in the two-path bandpass Σ modulator, the gain sequence should not have the spectral component at s / (i.e., the input signal that is located at s /4 should not see an even number o distinct physical paths). Thereore, the s / component o the gain-error sequence associated with the conventional two-path bandpass Σ modulator can be avoided by introducing the third path into the Σ modulator design. Also, we extend this reasoning to the pseudo-two-path Σ modulator such as the design proposed in [58]. We conclude that when the input signal is located at s /4 there should not be an even number o pseudo-paths. In Section 7.., we described a pseudo-three-path bandpass ilter, which, i used in the design proposed in [58], improves the mirror image suppression. However, there are sources other than the resonator that may cause the s / component o the gain-error sequence in two-path Σ modulators. The design proposed in [58] is using an even number (two) o quantizers and eedback DAC loops. According to the aorementioned analysis, this may cause the mirror image to old back into the signal band. The speed o the two-path Σ modulator design relies

142 3 heavily on the operating speed o the quantizer and DAC circuitry. I these circuits are capable o operating at the sampling requency that is our times the input signal center requency, then only a single quantizer and DAC are necessary or proper modulator operation. Having a single quantizer and eedback DAC loop, there can be no path mismatch that might produce the mirror image. However, i the quantizer and DAC circuits are not capable o operating at these speeds, it is necessary to introduce separate quantizers and DACs or each o the three paths in the modulator structure. The individual quantizer outputs would then be multiplexed to produce the inal modulator output. Thereore, we propose to introduce a third quantizer and DAC eedback loop to suppress the s / gain-error component, as opposed to the design in [58] that utilizes two-paths (i.e. two quantizers and eedback DACs). We generalize this approach and conclude that a two-path Σ modulator should be designed such that the input bandpass signal, which is centered at s /4, should not see an even number o distinct objects (e.g. quantizers, eedback DACs, sampling capacitor paths) Simulation Results The simulation parameters used in the pseudo-two-path bandpass Σ modulator example described in this section are sampling requency s = 0.MHz, OSR = 70, bandwidth = 30kHz, and an input signal at in =.54MHz, which is shited slightly rom s /4. Additionally, capacitor tolerances o ±8% were assumed to realize the gain mismatch error among the dierent paths. In order to provide realistic simulations, non-ideal op-amp models were used or the resonators. The simulations were perormed assuming room temperature, a inite op-amp gain (57dB), inite gain-bandwidth (50MHz), slew rate (80V/µs), and saturation. In addition to the op-amp non-idealities, clock jitter was also taken into account.

143 4 Maintaining the same average path gain, simulations were perormed or both the two-path and three-path designs. Figure 7-6 shows the typical modulator output or the proposed design with an input requency o.54mhz and bandwidth and OSR speciied previously. The detailed output spectrum o the two-path design used or the simulations, seen in Figure 7-7, shows the mirror image produced rom the two-path structure. Due to the mirror image signal, the SFDR o this design is 54dB. The three-path design improves upon this metric as seen in Figure 7-8, where a detailed section o the output spectrum around the input requency is displayed. The mirror image signal is completely removed rom the output spectrum resulting in the SFDR = 7dB. The simulations have shown that the three-path structure slightly increases the noise loor in the signal band. The detailed output spectrum igures rom both designs (Figure 7-7 and Figure 7-8) show that the noise loor in the signal band or the three-path design is, on average, db higher than that or the two-path design. This shows that, along with the relocation o the mirror image spike outside the signal band, the notch o the NTF accompanying the replica is also relocated, which brings an excess amount o quantization noise back into the signal band. However, since the mirror image signal is removed rom the signal band o the three-path modulator the resulting SNDR is higher than that or the two-path design. The calculated SNDRs or the two-path and three-path modulator designs are 5.6dB and 60.dB respectively. As a result, the proposed three-path bandpass Σ modulator demonstrates a 0dB SFDR improvement along with a 7.5dB SNDR improvement over the previous two-path modulator design. One drawback o both the two-path modulator described in [58] and the proposed three-path modulator described herein is their susceptibility to out-o-band intererers that may old back into the signal band during the interleaving procedure. In particular, i a strong spectral spike exists within the requency locations in /3 BW/ intererer in /3 + BW/ or 5 in /3 BW/ intererer 5 in /3 + BW/ then the

144 5 spectral spike will be modulated into the signal band creating an in-band intererer. As a result, the SFDR and SNDR o both modulators will be reduced. Simulations were perormed to conirm this using the same parameters speciied above or the previous set o simulations. In addition, an intererer signal located at in /3 was included with an amplitude equal to 0% o the input signal amplitude. Figure 7-9 depicts the output spectrum o the two-path modulator where the intererer is clearly visible at in /3. Figure 7-0 shows the in-band detailed spectrum o the two-path modulator when an intererer is applied at in /3. Figure 7-0 shows the mirror image o the input signal within the signal band as well as a mirror o the in /3 intererer created by modulation with the input signal as well as a mirror o the in /3 intererer created by modulation with the mirror image o the input signal. The resulting SFDR and SNDR or the two-path modulator were ound to be 49dB and 46.3dB respectively. The proposed three-path modulator was also ound to be susceptible to the spectral intererer located at in /3. Figure 7- represents the output spectrum o the three-path modulator in the presence o a spectral intererer located at in /3. As a result o the path selection method proposed earlier, the in /3 intererer is modulated into the signal-band o the three-path modulator as shown in the in-band detailed spectrum depicted in Figure 7-. In this igure, the mirror image o the in /3 intererer created by modulation with the input signal is evident. As a result, the SFDR and SNDR values approach those o the two-path modulator under the presence o a spectral intererer at in /3. For the three-path modulator with an intererer at in /3, the SFDR and SNDR were ound to be 49dB and 47.3dB respectively.

145 6 Figure 7-6: Typical output spectrum o three-path ourth-order bandpass Σ modulator with input requency in =.54MHz ( s = 0.MHz). Figure 7-7: Output spectrum detail o the two-path ourth-order Σ modulator with in =.54MHz.

146 7 Figure 7-8: Output spectrum detail o the three-path ourth-order Σ modulator with in =.54MHz. Figure 7-9: Output spectrum o the two-path ourth-order Σ modulator with in =.54MHz and in /3 intererer.

147 8 Figure 7-0: Output spectrum detail o the two-path ourth-order Σ modulator with in =.54MHz and in /3 intererer. Figure 7-: Output spectrum o the three-path ourth-order Σ modulator with in =.54MHz and in /3 intererer.

148 9 Figure 7-: Output spectrum detail o the three-path ourth-order Σ modulator with the input signal at in =.54MHz and a in /3 intererer. 7. Bandpass Σ Modulator Utilizing Spread- Spectrum Path Selection The susceptibility o both the two-path bandpass Σ modulator [58] and the three-path bandpass Σ modulator [59] described in the previous section to the mirror image signals and spectral intererers revealed the need to develop an eective two-path bandpass Σ modulator that is insensitive to path mismatches that result in input signal mirror image generation as well as being impervious to out-oband spectral intererers. In this section, a two-path bandpass Σ modulator that

149 30 relies on a randomized capacitor path selection scheme is presented. The proposed modulator demonstrates through simulations that it is eective at spreading the mirror image signal associated with the periodic selection o mismatched capacitor paths. In addition, simulations o the proposed modulator demonstrate that the modulator s input signal band is immune to out-o-band intererers. 7.. Capacitor Path Spread-Spectrum Randomization The modulator design proposed in this section takes advantage o spreadspectrum capacitor path randomization. In order to achieve the spread-spectrum path randomization or the bandpass Σ modulator, additional paths must be added to the traditional N-path bandpass Σ modulator resulting in a total o M paths. Additionally, path selection is constrained so that a path may not be selected again until N other paths are chosen. The resulting path selection sequence has blue noise spectral properties (i.e., the spectrum o the selection sequence has a low requency deiciency). This method is very eective at spreading the mirror image created by path mismatch in the traditional -path bandpass Σ modulator. A new two-path Σ modulator design is proposed in the ollowing sections with a speciic look at a pseudo-two-path bandpass Σ modulator utilizing spread-spectrum path selection. 7.. Modulator Operation The proposed resonator structure requires our overall capacitor paths (i.e., our input capacitor pairs and our eedback capacitor pairs), which allow or randomization according to a spread-spectrum path selection sequence. The improved our-path resonator structure is shown in Figure 7-3. The design operates as a ully-dierential, double-sampling, pseudo-two-path bandpass ilter as described

150 3 in [58]. The operation o the proposed double-sampling pseudo-two-path bandpass ilter is described below in detail. The double-sampling structure operates such that during one clock phase, the input is being sampled, while at the same time the previous input signal sample is being transerred to the resonator. In this design, the sampling capacitor pairs: Csa, Csb; Csa, Csb; Cs3a, Cs3b; and Cs4a, Cs4b and the charge storage capacitor pairs: Ca, Cb; Ca, Cb; C3a, C3b; C4a, C4b are controlled by the random phase clock signals that are determined according to the spread-spectrum path selection sequence. For simplicity, assume that the values o all capacitors are equal. The ilter structure shown in Figure 7-3 is designed or use as the resonator structure in a bandpass Σ modulator. Thereore, the z-domain transer unction given in Eq. (7-9) describes the ilter s operation. z H ( z) = (7-9) + z The generalized equation or the output voltage at a given time sample is then given by Eq. (7-0). vout ( n + k) = vin ( n + k ) vout ( n + k ) (7-0) To analyze the operation o the proposed resonator, an example will be described in detail. First, consider a potential path selection sequence that satisies the blue noise spectral requirements described previously. For this example the path selection sequence, 3,, 4,, will be used. This sequence is shown in Figure 7-4 as the clock signals. At time instance n, v in (n) is sampled onto capacitors Csa, Csb. The previous input sample, v in (n-), which is stored on Cs3a, Cs3b, is transerred to Ca, Cb since they are connected as eedback capacitors during this clock phase. Additionally, v out (n-), which is stored on Ca, Cb, is transerred to Ca, Cb. The described operation yields the expression or v out (n) shown by Eq. (7-).

151 3 Figure 7-3: Proposed double-sampling pseudo-two-path bandpass ilter utilizing spreadspectrum path selection. Figure 7-4: Example clock sequence.

152 33 vout ( n) = vin ( n ) vout ( n ) (7-) This expression or v out (n) agrees with the generalized expression shown in Eq. (7-0). During this clock cycle Ca, Cb become completely discharged. Also, the capacitors C4a, C4b are assumed to be discharged during one o the previous 4h clock phases. This allows the spread-spectrum path selection algorithm to choose either one o the capacitor pairs C4a, C4b or Ca, Cb or storage during the next clock cycle. Additionally, capacitors C3a, C3b store v out (n-). Next, consider the ilter operation at time instance n+. The current input, v in (n+) is sampled to Cs4a, Cs4b, while v in (n) stored on Csa, Csb and v out (n-) stored on C3a, C3b are transerred to the eedback capacitors C4a, C4b. Once the charge is transerred, C3a, C3b are discharged, preparing them or storage during the ensuing clock cycle along with Ca, Cb. The resulting expression or v out (n+) is Eq. (7-). vout ( n + ) = vin ( n) vout ( n ) (7-) Finally, consider time instance n+. The input voltage, v in (n+) is sampled to Csa, Csb according to the spread-spectrum path selection sequence. Additionally, v in (n+) stored on Cs4a, Cs4b and v out (n) stored on Ca, Cb are transerred to Ca, Cb, which are connected as eedback capacitors. The expression or v out (n+) is given in Eq. (7-3). v out (n + ) = v (n + ) v (n) (7-3) in Ater the charge transer is completed, Ca, Cb are discharged allowing the spread-spectrum path selection to choose either C3a, C3b or Ca, Cb or use during the next clock cycle. Additionally, v out (n+) is being stored on C4a, C4b. According to the spread-spectrum path selection sequence chosen or this example, path will be utilized during the next clock cycle. Ater that, paths 3 and 4 may be randomly out

153 34 selected according to the previously described spread-spectrum selection requirements Simulation Results The simulation parameters used in the pseudo-two-path ourth-order bandpass Σ modulator example provided in this section are identical to those utilized in Section These parameters are summarized in Table 7-. Simulation Parameter Value Sampling Frequency 0.MHz OSR 70 Signal Bandwidth 30kHz Input Signal Center Frequency.54MHz Ampliier DC Gain 57dB Ampliier Gain-Bandwidth 50MHz Ampliier Slew Rate 80V/µs Table 7-: Simulation parameters or the pseudo-two-path ourth-order bandpass Σ modulator example. Simulations were perormed or both the traditional pseudo-two-path modulator and pseudo-two-path modulator utilizing spread-spectrum path selection. The simulations maintained the same average path gain or both cases. Figure 7-5 displays the typical modulator output or the proposed design with an input requency o.54mhz and OSR and bandwidth speciied previously. The detailed output spectrum o the traditional pseudo-two-path design used or the simulations is shown in Figure 7-6. The mirror image produced by the gain mismatch between the two paths is present about the requency s /4. Due to the mirror image signal, the SFDR o this design is reduced to 54dB. The pseudo-two-path design utilizing

154 35 spread-spectrum capacitor path selection improves upon the SFDR metric as seen in Figure 7-7, where a detailed output spectrum around the input requency is displayed. The mirror image signal is completely removed rom the output spectrum resulting in the SFDR = 7dB. The simulations have shown that the pseudo-two-path Σ modulator with spread-spectrum path selection suppresses the mirror image at the expense o a slight noise loor increase in the signal band. The detailed output spectrum igures rom both designs (Figure 7-6 and Figure 7-7) show that the noise loor in the signal band or the pseudo-two-path design utilizing spread-spectrum path selection is, on average, db higher than that or the traditional pseudo-two-path design. This shows that the mirror image is spread as a wideband noise across the signal bandwidth when spread-spectrum path selection is utilized. As a result, the SNDR o the proposed pseudo-two-path modulator using spread-spectrum path selection suers compared to a mirror image ree pseudo-two-path Σ modulator containing perectly matched paths; however, an improvement is still made over the traditional pseudotwo-path modulator in the presence o path mismatch. The experimentally calculated SNDRs or the pseudo-two-path modulator and the pseudo-two-path modulator utilizing spread-spectrum path selection are 5.9dB and 58.4dB, respectively. The proposed pseudo-two-path modulator utilizing spread-spectrum path selection also reduces the eect o any signiicant spectral intererer located near in /3 or 5 in /3, as opposed to the designs previously proposed in [58] and [59] that are sensitive to such intererers. Simulation results indicate that the strong intererers will be spread as noise across the signal bandwidth similar to the mirror image. This penalty is modest considering the improvement to both SFDR and SNDR demonstrated through simulation. Figure 7-8 depicts the output spectrum o the proposed pseudo-two-path modulator utilizing spread-spectrum path selection in the presence o a spectral intererer at in /3. The in-band detail o this output spectrum is shown in Figure 7-9. As seen in Figure 7-9, the spectral intererer is no longer located in the signal bandwidth at the modulator output. When a strong spectral tone

155 36 is present at in /3, the proposed design achieves SFDR and SNDR improvements o db and 0.3dB, respectively, over the two-path bandpass Σ modulator utilizing a three-path structure that was presented in Section 7.. The SFDR and SNDR results or the traditional two-path modulator, the three-path modulator, and the two-path modulator utilizing spread-spectrum randomized capacitor path selection in the presence o a spectral intererer at in /3 are summarized in Table 7-. These results were obtained using the simulation parameters described previously. Modulator Design SFDR SNDR Two-Path 49dB 46.3dB Three-Path 49dB 47.3dB Two-Path with Spread-Spectrum Path Selection 70dB 56.6dB Table 7-: Comparison o SFDR and SNDR or various two-path bandpass Σ modulator designs in the presence o an intererer at in /3. Figure 7-5: Output spectrum o pseudo-two-path ourth-order bandpass Σ modulator utilizing spread-spectrum path selection with input requency in =.54MHz ( s = 0.MHz).