Design and Comparative Study of Discrete and Module based IGBT Power Converters

Transcription

1 Design and Comparative Study of Discrete and Module based IGBT Power Converters Venkatramanan D, Anil Kumar Adapa, Vinod John Department of Electrical Engineering Indian Institute of Science Bangalore, Karnataka, India Abstract This paper discusses concepts of a 25kVA power converter design and key differences between discrete IGBT and module based design approaches. Module based power converters have been typically employed in academic and research institutes for power levels of 10 kva and more. However, with advancement in IGBT technologies and the growing need to minimize system size and weight, design based on discrete devices is now an attractive alternative for such power levels. A simple design procedure is presented for power converter design, using which a state-of-the-art discrete device and module based power converter is designed. A comparison is drawn subsequently, where it is established that discrete design yields a compact and economic design up to a power level of 25 kva. A key objective of this work is to lay emphasis on laboratory design of power converters. This enables a graduate level student to build a converter from start and in the process gain insight into the underlying engineering design process. Keywords Discrete IGBT, inverter design, forced-air cooling, Renolds number, Nusselts number, dc-link capacitor, multi-layer PCB, device junction temperature. I. INTRODUCTION Power electronic devices have evolved considerably over the past decade. Their fast switching speeds and low on-state saturation voltages result in lower power loss and reduced component size. A variety of semiconductor technologies are available today that differ in switching speeds and associated energy losses, saturation voltage etc. Field-stop and Trenchgate IGBTs are designed for reduced saturation voltages [1], [2], whereas Warp IGBTs are designed for reduced switching energy losses [3]. Hybrid varieties such as high-speed Trenchstop IGBTs are also available now with optimized conduction and switching loss characteristics [4]. Power semiconductor packages have evolved as well from bulky modules to extremely compact surface mount designs. For power levels of the order of 10 kva, module based twolevel power converter designs have been prevalent in the form of off-the-shelf converter stacks, that are typically employed in various academic institutions. However today, with existing technology in semiconductor and packaging, designs based on PCB mounted discrete devices has become feasible for 10 kva power level and more. A PCB based design offers a variety of benefits such as reduced parasitic inductances in power and gate-drive circuitry, compactness, reduced system cost and weight. Because parasitics are lowered in PCB, it is possible to increase switching frequency of operation and enhance power density. Fig. 1: Power circuit configuration of two-level three-phase four leg converter In this work, a simple practical design procedure with adequate design margins is introduced first, that targets graduate level engineering students, to enable them to build a power converter in-house from the outset. The exercise of building a power converter from start allows the student to experience various underlying engineering challenges and develop a better understanding of the power electronic system. With this procedure, a module based and discrete design is analyzed and compared subsequently in Section II in terms of cost, weight and power loss. This is followed by conclusion in Section III. II. DISCRETE DESIGN PROCEDURE Design of a power converter for a given power rating begins with selection of appropriate semiconductor devices of sufficient voltage and current ratings. A typical two-level three-phase four-leg converter configuration is shown in Fig. 1. A variety of semiconductor technologies are available today that differ in switching speeds and associated energy losses, saturation voltage etc. [1] [4] and one must choose a particular type that best suits the given application. This is followed by evaluating the amount of power loss incurred in the semiconductors during operation. Subsequently, a suitable heat-sink must be chosen that is capable of dissipating the heat generated by the device losses adequately so as to maintain the heat-sink and device junction temperature around a desired value. Heat extraction is done either through natural cooling or forced cooling using air or water. Forced-air convection cooling is preferred at higher power levels as it a yields a more compact design. While there are a variety of heatsink profiles available in literature, the scope of this paper is restricted to design of one particular type as shown in Fig. 2. A suitable thermal interface material is chosen, that is used between the device case and heat-sink surface, which has a

2 TABLE I: Power converter ratings Power dc bus voltage V dc Output voltage (l-l) Output current (RMS) Nominal power factor 25 kva 800 V 400 V 36 A UPF Nominal modulation index m a 0.9 Switching frequency f sw 7.5 khz decisive effect on the device junction temperature. Ultimately, the bottleneck in any power electronic design is the device junction temperature reached at steady-state, which must be kept below the maximum device rating of 150 C or 175 C with adequate margin as explained in Section II(A). The target specifications of the converter shown in Fig. 1 is given in Table.I and the design procedures are explained below. A. Device Selection Voltage rating: Typically, device is rated such that the maximum peak collector to emitter voltage applied (inclusive of ringing excursion during turn-off transient) is about 20% below the device voltage rating. This ensures that adequate margin is available even during transients. Current rating: The ultimate current that a device can handle is constrained by bond wire current capacity and the same indicated in the safe operating area (SOA) curve. It is recommended to keep the device current level 20% below this value under all operating conditions. factor cosφ, the IGBT and diode currents are given by [5], ( 1 I T,avg = I p 2π + m ) (3) 8 ( 1 I D,avg = I p 2π m ) (4) 8 (1 I T,rms = I p 8 + m ) (5) 3π (1 I D,rms = I p 8 m ) (6) 3π The total switching losses in IGBT and diode while the converter is operating at frequency f sw is given by, P sw,t = 1 π (E on,t + E off,t ) V DC I p f sw (7) V DC,test I test P sw,d E on,d f sw = 1 4 Q rr V DC f sw (8) where, E on,t and E off,t are turn-on and turn-off energy loss stated in the device datasheet at certain test conditions V DC,test, I test, R G,on, R G,off etc, and Q rr is the diode reverse recovery charge at circuit operating conditions. Using above, the losses are evaluated at the desired operating conditions of dc-link voltage and current. Correction factor for energy loss, when different values of R G,on and R G,off are used, may be obtained from corresponding energy loss curves in datasheet [5], [6]. C. Heat Sink Selection Junction temperature: It is recommended to ensure that the device junction temperature reached under nominal operating conditions is about 25 C below the maximum rating of 150 C or 175 C. This constraint has implications on heat-sink geometry and cooling mechanism employed. B. Loss calculation Once a device is chosen, total losses incurred during operation, which includes that due to conduction and switching, must be evaluated. The conduction losses in IGBT are evaluated using an approximate model of series connected voltage source V ce0 and collector-emitter on-state resistance r ce evaluated around nominal operating point. Similar model is employed for diode as well [5]. The total conduction losses in a IGBT and diode is given by, P c,t = V ce0 I T,avg + r ce I 2 T,rms (1) P c,d = V D0 I D,avg + r D I 2 D,rms (2) where, for a three phase power converter during operation carries a peak current I p, at a modulation index m a and power Fig. 2: Geometry of forced-air cooled heat sink At higher power levels, heat-sink with forced air convection cooling using fan is the most preferred arrangement owing to its simplicity and effectiveness. A host of hear-sink geometries is available in literature, and the biggest challenge with them is to determine its thermal resistance theoretically for a given fan. It is possible to determine thermal resistance experimentally, but a method to estimate dissipation capacity of a given profile serves as a good starting point and greatly aid first-pass design. The profile chosen in this paper, as shown in Fig. 2, is one which requires relatively simpler analysis for estimating power dissipation capacity. It uses horizontal fins arranged symmetrically with fan placed at one end. A shroud is employed to prevent the air

3 from escaping through the sides, thus channelizing the flow through the fin gaps. With shroud in place, the fin gap may be treated as an uninsulated rectangular duct, which means the heat-sink as a whole would comprise of as many ducts as the no of fin gaps. The design procedure is as follows, with the aid of an example. 1) Choose a fan of a certain dimension and volumetric-flow rate, which typically is rated in cubic-foot/minute (CFM). For example, consider a 24V BLDC fan from Sanyo Denki [7], properties of which are listed in Table.II. TABLE II: Properties of DC fan from Sanyo Denki Part No Rated Power Rated Voltage Rated flow rate Max. static pressure Width Height Thickness 9G0824H W 24 V 80 cfm 171 P a 80 mm 80 mm 40 mm 2) Assume a heat-sink profile such that fin region spans the cross-sectional area of the fan. For example, for the profile shown in Fig. 2, total fin area spans the width and height of the fan considered in Table. II. Choose a certain fin thickness and fin gap, say 3.5mm and 5mm respectively. The length of the heat-sink is determined by the number of devices to be mounted and the chosen gap between them. The corresponding dimensional parameters of a 200mm long heat-sink are listed in Table.III. It is now required to estimate the heat dissipation capacity of the this heat-sink profile. 3) With the heat-sink in place, the operating CFM of the fan would decrease depending on the static pressure offered by the heat-sink fin area. Assume the CFM drops by 50%. Assume inlet air temperature to be 25 C and exit air temperature to be 60 C. Hence, the bulk temperature would be the mean value i.e C. Obtain the air properties at 40 C and 1 atm pressure from standard table, as listed in Table.IV. 4) Next, the nature of air flow (laminar or turbulent) in the duct needs is determined, with the help of Reynolds number [8] TABLE III: Heat-sink dimensions Fin thickness t f Fin gap g f Duct Parameters Width w Thickness t Length L Perimeter p 3.5 mm 5 mm 34 mm 3.5 mm 200 mm 78 mm Cross-section area A c 170 mm 2 Inner surface area A s mm 2 No of ducts n 18 TABLE IV: Properties of air at 1 atm pressure and 40 C Density ρ kg/m 3 Specific capacity Cp Thermal conductivity k 1007 J/kg.K W/m.K Kinematic Viscosity ν m 2 /s Prandtl No P r Flow rate in one duct V is given by, ( ) 0.5 V = Rated CF M = 2.22 cfm (9) n V = m 3 /s (10) Equivalent hydraulic diameter of the duct is given by, D h = 4A c p = m (11) Average velocity of air in the duct is given by, v avg = V A c = 6.17m/s (12) Reynolds number for the flow is given by, Re = v avgd h = 3158 (13) ν Flow is fully laminar when Re < 2800 and fully turbulent when Re < 10, 000 [8]. However, since the calculated Re is greater than 2800 by about 12%, it may be assumed that flow is laminar. Onset of turbulence would actually improve the rate of heat transfer than what is calculated. 5) Next, Nusselt number for the flow is calculated. Hydrodynamic entry length is calculated as, L h = 10D h = m (14) Nusselt number for the above laminar flow is given by, Nu = (D h /L).Re.P r [(D h /L).Re.P r] 2/3 (15) Nu = 7.6 (16) 6) From Nusselt number, heat transfer coefficient h for heatsink by forced air convection is evaluated. h = k Nu W/m 2. C D h (17) h = 23 W/m 2. C (18) 7) Finally, the amount of power drawn away by air through forced convection is calculated, which would give a fair idea about the capacity or effectiveness of the heat-sink of chosen dimension. Mass-flow rate through the duct is, ṁ = ρ V = kg/s (19) Assuming inlet air temperature T i is 25 C and duct surface temperature T s is 80 C, exit air temperature T e is determines as, T e = T s (T s T i )e has/ṁcp (20) T e = 39.4 C (21)

4 Logarithmic mean temperature difference is given by, T ln = T i T e ln Ts Te T s T i = 47.4 C (22) Rate of heat loss from a single duct by forced convection thus is determines as, Q = P duct = ha s T ln = = 17.1W (23) Total heat loss from whole heat-sink by forced convection is given by, P tot = np duct = = 308W (24) Therefore, the heat-sink of the chosen geometry with 80 CFM fan is capable of extracting 308 W of power, with duct surface temperature at 80 C. An additional 20% improvement in heat extraction may assumed when turbulence in flow and natural convection around devices are factored in. This would mean the above heat-sink structure can dissipate roughly 370W of power. This value is compared with total power loss incurred in semiconductors to understand the viability of heat-sink fan arrangement. D. Dc-link Capacitor selection Dimensioning of dc-link capacitor depends on combination of factors such as allowable current stress that offers a certain working life as specified in the datasheet, allowable low frequency dc-link voltage ripple in case of single-phase applications, and hold-up time required during front-end fault ride-through. In a three-phase PWM converter, only switching frequency ripple current flows through dc-link capacitor and hence it experiences only high frequency current stress [9], the RMS value of which is given by, ) ( I C,rms = I p 3ma 3ma + 4π π 9m2 a 16 cos 2 φ (25) In case of single-phase PWM converter, differential mode second harmonic current also flows through the dc-link capacitors in addition to switching frequency ripple, thus resulting in a second harmonic voltage ripple v c,100hz expressed as, v c,100hz = V o,rmsi o,rms V DC πfc dc (26) where, V o,rms and I o,rms are output RMS voltage and RMS current respectively. This value may be chosen to be 10% of nominal dc bus voltage. All the above constraints must be considered appropriately for dc-link capacitor design. III. MODULE VERSUS DISCRETE DESIGN Design of module based and discrete component power converter differs in few ways that are outlined below. Dc bus structure: External dc bus plates with bushes and appropriate geometry are employed in case of module based design. With discrete IGBTs, dc bus would be in the form of internal layer planes of a multi-layer power PCB. Distance between dc-link capacitors and devices can be considerably reduced in a PCB and hence parasitic inductance can be made lesser. Dc-link capacitor: Module based design requires screw-type dc bus capacitors that are attached to bus plates through bushes and screws appropriately. In discrete design, snap-in or plug-in capacitors are used that get soldered to the power PCB. For a given capacitance value and voltage rating, parameters such as Equivalent Series Resistance ESR, Equivalent Series Inductance ESL and current ratings would vary depending on the type of electrolytic capacitors used. For example, screw-type capacitors always possess higher ESL, lower ESR and higher current ratings as compared to snap-in capacitors. Also, screw-type capacitors are relatively expensive. Gate-drive circuit: In discrete design, gate drive circuitry may be placed closest to the device either by directly soldering them onto PCB or in the form of a daughter card [10], as shown in Fig.3(b), mounted on PCB and thus reducing parasitics to minimal. In case of modules, owing to the mechanical layout, the parasitics are relatively higher due to wired interconnection, typically in the form of twisted pairs. Power density: PCB based designs, especially when four or more layers are employed, offer much higher power density as compared to module based design. At higher power levels however, PCB trace widths must be sized sufficiently large so as to carry rated currents for a given temperature rise, which could reduce power density. This may be avoided and power density may be enhanced further by employing bus bars soldered on to PCB, as shown in Fig.3(a). Apart form device junction temperature limitation, parasitics also play a key in determining the ultimate power level up to which a given design can be operated. This is due to the fact that at higher power levels, parasitics inductances in gate-drive circuitry and dc bus plates may cause excessive ringing during switching and the device voltage excursions may well be beyond admissible stress limits. It is desirable to keep parasitics to the minimum possible extent by having a clean physical layout [11], and in this viewpoint, PCB based design is beneficial. Also, since housing of connectors is easier on a PCB, interfacing PCB based power circuit with external digital-controller is quite simple. As an example, a three-phase 25 kva PCB based two-level discrete power converter design using the above procedure is presented and compared with similar rated module based design in terms of system cost, for a three-leg topology which is prevalent in commercial converters. State of the art power devices and and other components are employed in the two designs [12] [14]. At rated operating conditions, the ripple current catered by dc bus capacitor I C,rms calculated from (25) is 20.6A and the dc bus capacitance value is chosen as 1000 µf. The PCB, as shown in Fig.3(a), is designed such that the size of the dc-link capacitor bank can be increased by interfacing with external capacitors, in case of large hold-up time requirement.

5 34 cm 22 cm (a) Fig. 3: Hardware details discrete power converter showing a) Physical placement of components on power PCB and b) Device gate-drive card and DC fan for forced-sir cooling (b) The choice of system components with associated losses and cost details are compared in Table.V. The heat-sink design procedure described in Section II would lead to similar sized heat-sink structures for module and discrete design respectively since their semiconductor losses are rather similar, as can be seen from the table. Hence, the cost of heat-sinks would be comparable in the two designs. Fig.3(a) shows physical component placement on a 4-layer, 2.4mm power PCB that uses 70µm copper, designed conforming to IPC-2221A design standard [15]. Two internal layers are used for dc-link in the power section, and for ground and power planes in the signal section. The PCB core is 1.4mm thick, made of pre-preg 7628 with 300V/mil breakdown strength. External layers are used for component interconnections and power traces. The PCB includes dc-link capacitors with bleeder resistors, devices, diode-bridge based pre-charge circuitry, heat-sink plus fan, gate-drive cards [10], on-board current sensors, output relays to power connectors, FRC connectors to external digital controller, and power -supply connectors, as shown. To enhance the power density of the PCB, 1mm thick copper busbars have been used to interconnect inverter poles and current sensors. Altogether, the PCB foot-print measures to 34cm x 22cm for a three-phase four-leg topology. All the protection mechanisms available in a commercial converter stack are available in this design that include IGBT desaturaion fault detection incorporated in gate-drive card [10], over-current protection, dc bus over/under voltage protection, and heat-sink over-temperature fault detection using thermostat [16]. It may be seen on the PCB that the distance between the device and gate-driver is less than 5cm, which leads to small gate parasitic inductance. The loss per device at rated power is about 68 W at 7.5 khz switching frequency. Total power dissipation in semiconductors is about 400W at 7.5 khz, which is 10% more than the calculated capacity of the heat-sink discussed in Section II. This is within the margin of error in calculations and hence could be considered for this system for the first pass kva of the converter W 45 W 30 W Switching frequency [khz] Fig. 4: Power level de-rating curve for various operating switching frequencies f sw at different loss per device design. Changing switching frequency of operation would alter the losses in a device and hence operating power level of the converter needs to be changed appropriately to maintain a given device junction temperature for a given heat-sink arrangement. Fig.4 shows the power de-rating curve with operating switching frequency of discrete converter for different values of device losses. It may be noted that pushing the power level further than 25 kva in a discrete design would require either a very efficient heat-sink mechanism, which could increase the size and weight of the system, or reduction in switching frequency f sw below 5 khz, by which the capacity of the device is underutilized. It can be noted from Table. V that a discrete device based laboratory design would cost only half of that of module based design. Commercially available converter stacks are not only expensive, but also are available only for power levels of 50 kva and above typically. So, for requirements up to 25 kva, one always ends up procuring a fairly overrated stack.

6 TABLE V: Component comparison of module based and discrete systems Capacitor IGBT Current Sensor Description Module Component ratings Discrete Package Screw-type Snap-in Part no Quantity used CGS202T450X5C 2 (in series) 382LX102M45 00B062V 4 (2 2 in series) Rated capacitance 1000 uf 1000 uf Rated Voltage 450 V 450 V Rated current ripple 32 A 21.5 A Power loss 14.4 W 11.2 W Unit Price (INR) Rs 10,218 Rs 2,387 Total cost(inr) Rs 20,436 Rs 9,548 Package Module TO-247 Part no SKM50GB12T4 IKW40N120H3 Voltage rating 1200 V 1200 V Current rating 81 A 80 A IGBT loss 59.3 W 62.6 W Diode loss 4.7 W 6 W Total Loss 64 W 68.6 W IGBT R θjc 0.53 C/W 0.31 C/W Diode R θjc 0.84 C/W 1.1 C/W Quantity 3 6 Unit Price (INR) Rs 7,610 Rs 690 Total cost (INR) Rs 22,830 Rs 4,140 Package Panel mount PCB mount Part no HAS-50S HLSR-32P Quantity 3 3 Unit Price (INR) Rs 2,500 Rs 1,200 Total cost (INR) Rs 7,500 Rs 3,600 Heat Sink Total cost (INR) Rs 6,000 Rs 6,000 Miscellaneous PCB - Rs 5,000 Bus-plate assembly Rs 4,000 - Relays Rs 2,000 Rs 1,000 Overall System Cost (INR) Rs 62,766 Rs 29,288 For academic and research institutes, for power levels ranging up to 25 kva, laboratory built design not only serves as an economic alternative but also allows the students to experience the design process, which includes heat-sink selection, choice of devices, loss evaluation and its switching characteristics, dc-link current and selection of capacitors, PCB layout design and trace clearance issues. IV. CONCLUSION A practical power converter design approach is presented and the same is employed to design a 25kVA three-phase two-level power converter with with state of the art discrete devices and components. A comparison is made with a similar rated converter with IGBT modules. The system cost of a module based design was found to be more than twice that of the discrete design. This difference arises primarily due the fact that semiconductor modules by themselves are far more expensive than individual devices of similar rating, and that modules necessitate usage of expensive screw-type dc-link capacitors and panel mountable current sensors that further add to the system cost. PCB based discrete approach leads to a compact system with minimal parasitics and is appropriate for power levels up to 25kVA. Module based design would be appropriate and economic only for multi-level power converters wherein the device count is higher, and for power levels more than 50 kva with large operating current levels for which discrete devices are non-viable. Paralleling of multiple discrete devices on PCB not only introduces additional parasitics due to asymmetry and affects performance at higher power levels, but also renders the system bulky and uneconomic. Modules rated for higher currents incorporate devices paralleled at chip level and hence are best suited for such high power applications. The exercise of building a power converter in-house gives a graduate engineering student better insight into the system and underlying technical challenges. REFERENCES [1] H. Shah, S. Oknaian, E. Persson, and R. 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