32K 8 CMOS STATIC RAM
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1 GNR SCRIPTION 32K 8 CMOS STTIC RM The W24258/ is a normal speed, very low power CMOS stati RM organized as bits that operates on a single 5-volt power supply. This devie is manufatured using Winbond's high performane CMOS tehnology. FTURS ow power onsumption: tive: 350 mw (max.) Standby: 25 µw (max.) ess time: 55/70 ns (max.) Single 5V power supply Fully stati operation ll inputs and outputs diretly TT ompatible PIN CONFIGURTIONS Three-state outputs Battery bak-up operation apability ata retention voltage: 2V (min.) Pakaged in 28-pin 600 mil IP, 330 mil SOP and standard type one TSOP (8 mm 3.4 mm) BOCK IGRM CK GN. PRCHRG CKT V W R O W C O COR C RRY 52 ROWS 64 X 8 COUMNS R pin IP O 0 I/O8 3 I/O I/O8 T CNTR. CK GN. I/O CKT. COUMN COR I/O I/O2 I/O3 V SS I/O7 I/O6 I/O5 I/O4 W O PIN SCRIPTION O W V pin TSOP I/O8 I/O7 I/O6 I/O5 I/O4 V SS I/O3 I/O2 I/O 0 2 SYMBO 0 4 I/O I/O8 W O V VSS SCRIPTION ddress Inputs ata Inputs/Outputs Chip Selet Input Write nable Input Output nable Input Power Supply Ground Publiation Release ate: November Revision 5
2 TRUTH TB O W MO I/O- I/O8 V CURRNT H X X Not Seleted High Z ISB, ISB H H Output isable High Z I H Read ata Out I X Write ata In I C CHRCTRISTI bsolute Maximum Ratings PRMTR RTING UNIT Supply Voltage to VSS Potential -0.5 to +7.0 V Input/Output to VSS Potential -0.5 to V +0.5 V llowable Power issipation.0 W Storage Temperature -65 to +50 C Operating Temperature 0 to 70 C Note: xposure to onditions beyond those listed under bsolute Maximum Ratings may adversely affet the life and reliability of the devie. Operating Charateristis (V = 5V ±0%; VSS = 0V; T = 0 C to 70 C) PRMTR SYM. TST CONITIONS MIN. TYP.* MX. UNIT Input ow Voltage VI V Input High Voltage VIH V +0.5 V Input eakage Current II VIN = VSS to V µ Output eakage Current IO VI/O = VSS to V, = VIH (min.) or O = VIH (min.) or W = VI (max.) µ Output ow Voltage VO IO = +2. m V Output High Voltage VOH IOH = -.0 m V Operating Power I = VI (max.), I/O = m Supply Current I/O = 0 m, Cyle = min. Standby Power Supply Current ISB uty =00% = VIH (min.), Cyle = min. uty = 00% m m ISB V -0.2V µ Note : Typial parameter is measured under ambient temperature T = 25 C and V = 5V
3 CPCITNC (V = 5V, T = 25 C, f = MHz) PRMTR SYM. CONITIONS MX. UNIT Input Capaitane CIN VIN = 0V 6 pf Input/Output Capaitane CI/O VOUT = 0V 8 pf Note: These parameters are sampled but not 00% tested. C CHRCTRISTI C Test Conditions PRMTR CONITIONS Input Pulse evels 0V to 3.0V Input Rise and Fall Times 5 ns Input and Output Timing Referene evel.5v Output oad See the drawing below C TST OS N WVFORM TT TT OUTPUT OUTPUT 00 pf Inluding Jig and Sope 5 pf Inluding Jig and Sope (For TCZ, TOZ, TCHZ, TOHZ, TWHZ, T OW) 3.0V 0V 5 ns 90% 0% 90% 0% 5 ns Publiation Release ate: November Revision 5
4 C Charateristis, ontinued (V = 5V ±0%; VSS = 0V; T = 0 C to 70 C) Read Cyle PRMTR SYM. W W UNIT MIN. MX. MIN. MX. Read Cyle Time TRC ns ddress ess Time T ns Chip Selet ess Time T ns Output nable to Output Valid TO ns Chip Seletion to Output in ow Z TCZ* ns Output nable to Output in ow Z TOZ* ns Chip eseletion to Output in High Z TCHZ* ns Output isable to Output in High Z TOHZ* ns Output Hold from ddress Change TOH ns These parameters are sampled but not 00% tested Write Cyle PRMTR SYM. W W UNIT MIN. MX. MIN. MX. Write Cyle Time TWC ns Chip Seletion to nd of Write TCW ns ddress Valid to nd of Write TW ns ddress Setup Time TS ns Write Pulse Width TWP ns Write Reovery Time, W TWR ns ata Valid to nd of Write TW ns ata Hold from nd of Write TH ns Write to Output in High Z TWHZ* ns Output isable to Output in High Z TOHZ* ns Output tive from nd of Write TOW ns These parameters are sampled but not 00% tested - 4 -
5 TIMING WVFORMS Read Cyle (ddress Controlled) TRC ddress TOH T TOH OUT Read Cyle 2 (Chip Selet Controlled) OUT TCZ T T CHZ Read Cyle 3 (Output nable Controlled) T RC ddress T O OUT TO TOZ T TCZ TOH TOHZ TCHZ Publiation Release ate: November Revision 5
6 Timing Waveforms, ontinued Write Cyle TWC ddress T WR O TCW TW W TS T WP OUT TOHZ (, 4) TW TH IN Write Cyle 2 (O = VI Fixed) T WC ddress TCW TWR TW W TS TWP TOH OUT TWHZ (, 4) TOW (2) (3) TW TH IN Notes:. uring this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from OUT are the same as the data written to IN during the write yle. 3. OUT provides the read data for the next address. 4. Transition is measured ±500 mv from steady state with C = 5 pf. This parameter is guaranteed but not 00% tested
7 T RTNTION CHRCTRISTI (T = 0 C to 70 C) PRMTR SYM. TST CONITIONS MIN. TYP. MX. UNIT V for ata Retention VR V -0.2V V ata Retention Current IR V -0.2V, V = 3V µ Chip eselet to ata Retention Time TCR See data retention waveform ns Operation Reovery Time TR TRC* - - ns * Read Cyle Time T RTNTION WVFORM V 0.9 V VR => 2V 0.9V TCR TR VIH = > V - 0.2V VIH ORRING INFORMTION PRT NO. CCSS TIM (ns) OPRTING CURRNT MX. (m) STNBY CURRNT MX. (m ) W mil IP W mil IP W24258S mil SOP W24258S mil SOP PCKG W24258Q Standard type one TSOP W24258Q Standard type one TSOP Notes:. Winbond reserves the right to make hanges to its produts without prior notie. 2. Purhasers are responsible for performing appropriate quality assurane testing on produts intended for use in appliations where personal injury might our as a onsequene of produt failure. Publiation Release ate: November Revision 5
8 PCKG IMNSIONS 28-pin P-IP 2 28 S B B e 5 4 Base Plane Seating Plane a e imension in Inhes imension in mm Symbol Min. Nom. Max. Min. Nom. Max B B e a e S Notes:. imensions Max. & S inlude mold flash or tie bar burrs. 2. imension does not inlude interlead flash. 3. imensions & inlude mold mismath and are determined at the mold parting line. 4. imension B does not inlude dambar protrusion/intrusion.. 5. Controlling dimension: Inhes. 6. General appearane spe. should be based on final visual inspetion spe pin SOP Wide Body 28 5 H e Symbol 2 b e imension in Inhes imension in mm Min. Nom. Max. Min. Nom. Max S Seating Plane e b y 4 2 θ etail F e See etail F H S y θ Notes:. imensions Max. & S inlude mold flash or tie bar burrs. 2. imension b does not inlude dambar protrusion/intrusion. 3. imensions & inlude. mold mismath and determined at the mold parting line. 4. Controlling dimension: Inhes. 5. General appearane spe should be based on final visual inspetion spe
9 Pakage imensions, ontinued 28-pin Standard Type One TSOP b e H 2 Symbol 2 b H e Y θ imension In Inhes Min Nom. Max. Min. Nom. Max imension In mm θ Y Controlling dimension: Millimeters Publiation Release ate: November Revision 5
10 VRSION HISTORY VRSION T PG SCRIPTION 4 pr dd standby power supply urrent (ISB) typial parameter when operation temperature T = 25 C 5 Nov. 998, 2, 7, 9 edut reverse type one TSOP pakage Headquarters Winbond letronis (H.K.) td. No. 4, Creation Rd. III, Rm. 803, World Trade Square, Tower II, Siene-Based Industrial Park, 23 Hoi Bun Rd., Kwun Tong, Hsinhu, Taiwan Kowloon, Hong Kong T: T: FX: FX: Voie & Fax-on-demand: Taipei Offie F, No. 5, Se. 3, Min-Sheng ast Rd., Taipei, Taiwan T: FX: Winbond letronis North meria Corp. Winbond Memory ab. Winbond Miroeletronis Corp. Winbond Systems ab N. First Street, San Jose, C 9534, U.S.. T: FX: Note: ll data and speifiations are subjet to hange without notie
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ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
Functional Block Diagram. Row Decoder. 512 x 512 Memory Array. Column I/O. Input Data Circuit. Column Decoder A 9 A 14. Control Circuit
32K X 8 STATIC RAM PRELIMINARY Features High-speed: 35, 70 ns Ultra low DC operating current of 5mA (max.) Low Power Dissipation: TTL Standby: 3 ma (Max.) CMOS Standby: 20 µa (Max.) Fully static operation
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
IS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS
ISWVDALL/DALS ISWVDBLL/DBLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JANUARY 0 FEATURES HIGH SPEED: (IS/WVDALL/DBLL) High-speed access time:, 0,, 0 ns Low Active Power: mw (typical) Low Standby Power:
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS
IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
W91350N SERIES 13-MEMORY TONE/PULSE DIALER WITH HANDFREE AND HOLD FUNCTIONS GENERAL DESCRIPTION FEATURES
GENERAL DESCRIPTION 13-MEMORY TONE/PULSE DIALER WITH HANDFREE AND HOLD FUNCTIONS The W91350N series are tone/pluse switchable telephone dialers with thirteen memories, hold function, and a handfree dialing
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2011 FEATURES High-speed access time: 45ns Low Active Power: 50 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby TTL compatible interface levels Single
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM MAY 2012 FEATURES HIGH SPEED: (IS61/64WV3216DALL/DBLL) High-speed access time: 8, 10, 12, 20 ns Low Active Power:
IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
IS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7
128K x 8 Static RAM Features High speed t AA = 12 ns Low active power 495 mw (max. 12 ns) Low CMOS standby power 55 mw (max.) 4 mw 2.0V Data Retention Automatic power-down when deselected TTL-compatible
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023
FEATURES: SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo ROM + SRAM SST30VR021: 256K x8 ROM + 128K x8 SRAM SST30VR022: 256K x8 ROM + 256K x8 SRAM SST30VR023: 256K x8 ROM + 32K
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable FEATURES DESCRIPTION Very low operation voltage : 45 ~ 55V Very low power consumption : = 50V C-grade: 40mA (Max) operating current
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
28K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2005 FEATURES High-speed access time: 8, 0 ns CMOS low power operation 756 mw (max.) operating @ 8 ns 36 mw (max.) standby @ 8 ns TTL compatible
IS61WV10248ALL IS61WV10248BLL IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM MARCH 2017 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
Winbond Bus Termination Regulator W83310DS/DG
Winbond Bus Termination Regulator W83310DS/DG W83310DS Datasheet Revision History Pages Dates Version Version on Web Main Contents 1 May/03 0.5 N.A. All versions before 0.5 are only for internal use. 2
SEMICONDUCTOR TECHNICAL DATA
SEMIONDUTOR TEHNIAL DATA The M4093B Shmitt trigger is onstruted with MOS P hannel and N hannel enhanement mode devies in a single monolithi struture. These devies find primary use where low power dissipation
Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating
IS61WV10248EDBLL IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
2Mx32 5V NOR FLASH MODULE
2Mx32 5V NOR FLASH MODULE WF2M32-XXX5 FEATURES Access Time of 90, 120, 150ns Packaging: 66 pin, PGA Type, 1.15" square, Hermetic Ceramic HIP (Package 401). 6 lead, Hermetic CQFP (G2U), 22.4mm (0.0") square
Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
13-MEMORY TONE/PULSE DIALER WITH SAVE, KEYTONE, LOCK, AND HANDFREE FUNCTIONS
1-MEMORY TONE/PULSE DIALER WITH SAVE, KEYTONE, LOCK, AND HANDFREE FUNCTIONS GENERAL DESCRIPTION The W9150N series are tone/pulse switchable telephone dialers with 1 memories, keytone or lock, and handfree
1Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc) Operating Temperature A 0 -A 16 I/O 0 -I/O 7
1Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 8 bit N01L83W2A Overview The N01L83W2A is an integrated memory device containing a 1 Mbit Static Random Access Memory organized as 131,072 words by 8 bits.
A4 A3 A2 A1 A0 DQ0 DQ15. DQ2 DQ3 Vcc GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12
128K x 16 Low Power SRAM Rev 1.5 04/2007 Features 48-Ball BGA (CSP), Top View Single power supply voltage of 2.7V to 3.6V Power down features using CE Low operating current : 30mA(max for 55 ns) Maximum
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. 256K (32K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to
R1RP0416D Series. 4M High Speed SRAM (256-kword 16-bit) Description. Features. Ordering Information. REJ03C Z Rev Mar.12.
4M High Speed SRAM (256-kword 16-bit) REJ03C0108-0100Z Rev. 1.00 Mar.12.2004 Description The R1RP0416D Series is a 4-Mbit high speed static RAM organized 256-k word 16-bit. It has realized high speed access
BSI BH62UV8000. Ultra Low Power/High Speed CMOS SRAM 1M X 8 bit
FEATURES Wide low operation voltage : 1.65V ~ 3.6V Ultra low power consumption : = 3.0V = 2.0V High speed access time : -70 70ns at 1.V at 5 O C Ultra Low Power/High Speed CMOS SRAM 1M X bit Operation