Signal Processing Level III (BAC)

Size: px

Start display at page:

Download "Signal Processing Level III (BAC)"

Wesley Bell
5 years ago
Views:

Signal Processg Level III (BAC) combcd0_clr T combcd0_clr combcd0_clk T combcd0_q3t

TRUE cnaits0_d0 T TRUE cnaits0_d1 T 10 cnaits0_d2 T ALSE cnaits0_d3 T ALSE cnaits0_d4

016 0 D0-1 D1 En Sampl 8 D0 Q0 Q1 D1 Q2 En D2 R_LATCH_4B D2 0 5 10 Registre 4 bits CNA

samold0 sample Vref flaits0 Vréf scna 4 subv1 flaits1 Vréf / 4 0.

0.25 CNA 2 bits poids moyens CAN LASH 2 bits poids moyens 1 V CNA-LIN2BITS Registre 2

1 Signal Processg Level III (BAC) combcd0_clr T combcd0_clr combcd0_clk T combcd0_q3t combcd0_q2t combcd0_q1t updcpt0_clr T updcpt0_clr combcd0_q0t 0 5 updcpt0_clkt ALSE TRUE cnaits0_d0 T TRUE cnaits0_d1 T 10 cnaits0_d2 T ALSE cnaits0_d3 T ALSE cnaits0_d4 T ALSE cnaits0_d5 T ALSE +1 ALSE ms Q1 Q3 Q5 cnaits0_s Q0 Q2 Q D0-1 D1 En Sampl 8 D0 Q0 Q1 D1 Q2 En D2 R_LATCH_4B D Registre 4 bits CNA 2 bits poids forts CAN LASH 2 bits poids forts 0 V V q0 D0 q1 Vref D1 LASH2BITS samold0 sample Vref flaits0 Vréf scna 4 subv1 flaits1 Vréf / dt3 dt1 Vref CAN LASH 2 bits poids faibles 6 5 q0 D0 q1 Vref LASH2BITS 2 cnaits CNA 2 bits poids moyens CAN LASH 2 bits poids moyens 1 V CNA-LIN2BITS Registre 2 bits flaclr S&H Q2 D3 rla_4b1 Q3 Set ALSE ms Echantillonneur Bloqueur Q0 Q1 10 D3 rla_4b0 Q3 0.76ms 9 R_LATCH_4B D1 7 1 V CNA-LIN2BITS scna q0 LASH2BITS 2 subv0 cnaits1 Vref q1 flaits2 Vréf / dt4 Topics and Reports Author : N Gally KOMA Professor Electronic BTS Z.A. La Clef St Pierre - 5, rue du Groupe Manoukian ELANCOURT rance Tel. : 33 (0) / ax : 33 (0) ge@didalab.fr - Web : : ETD RefRef : ETD

2 2/124

3 SUMMARY Ex.1 : BASIC RS AND R S LIP-LOP RS LIP-LOP WITH NOT-OR PORTS RS LIP-LOP WITH NOT-AND PORTS PRACTICAL WORKS... 9 Ex.2 : LATCH OR LOCKED LIP-LOP LATCH LIP-LOP UNCTIONAL DESCRIPTION R S LIP-LOP REALISATION R S LIP-LOP REALISATION PRACTICAL WORKS DIAGRAMS Ex.3 : RS AND JK MASTER - SLAVE LIP-LOPS RS MASTER - SLAVE LIP-LOP JK MASTER - SLAVE LIP-LOP DIERENCE BETWEEN THE RS AND THE JK MASTER - SLAVE PRACTICAL WORKS WIRING DIAGRAMS TEST DIAGRAMS PULSE TIMING DIAGRAMS Ex.4 : D TYPE LIP-LOP UNCTIONAL DEINITION THEORETICAL STUDY PRACTICAL WORKS DIAGRAM Ex.5 : SYNCHRONOUS BCD UP AND DOWN COUNTERS PRINCIPLE TRUTH TABLE AND THE JK PHASES DIAGRAM UP AND DOWN COUNTER STUDY PRACTICAL WORKS DIAGRAMS Ex.6 : REVIEW ADC and DAC CONVERSION LESSON TARGET CHAIN O DIGITAL SIGNAL PROCESSING SAMPLING AND MAINTENANCE OR BLOCKING (S/M or S/B or S/H) /124

4 6.4 MAJOR DEECTS IN THIS DIAGRAM DIGITAL - ANALOG CONVERSION ANALOG-DIGITAL CONVERTER: ADC Ex.7 : DIGITAL -ANALOG CONVERSION: DAC PRINCIPLE DIAGRAM PRACTICAL WORKS Ex.8 : SINGLE RAMP ADC to COUNT and DAC PRINCIPLE DIAGRAM PRACTICAL WORKS DIAGRAMS Ex.9 : TRACKING ADC PRINCIPLE DIAGRAM PRACTICAL WORKS DIAGRAMS Ex.10 : SEMI-LASH ADC REALIZATION PRINCIPLE DIAGRAM fig PRACTICAL WORKS TEST DIAGRAM Ex.11 : ANALOG ILTERS LOWPASS ILTER O 1st Order PRACTICAL WORKS UNIVERSAL ILTER /124

5 Ex.11 : ANALOG ILTERS 11.1 LOWPASS ILTER O 1st Order Background on the analog tegrator The relationship lkg the output s (t) to the put e (t) of figure 1 is: ò fig.1 t t The Laplace transform of the temporal equation gives: This gives the transfer function: Transfer function of analog filter They are given by the relationship: Prciple diagram t t w t t The H(p) function is realized by the tegrator, INTEGRATE Block, whose time constant determes the filter cut-off frequency with : t rom the figure 2 diagram, it demonstrates the relationship givg T(jw). fig.2 111/124

6 11.2 PRACTICAL WORKS Test diagram Wire the test diagram below figure 4. The calculation part of the Bode diagrams (Ga and Phase) comes from the demonstration diagram by M. Jean-Marie ORY, author of ETD410 module Primitives. Note the Bode diagram and check the low-pass filter characteristics of the first order Bode Diagrams They are given by figure 3. Check the ga value cut-off frequency and the slope when the frequency tends to fity. 112/124

7 ilter to test 1st order Low pass: fc = 500Hz 2-1 1madd0 3 clear INTEGRATE 3 tega0 BODE DIAGRAM Of a 1 st order analog filter 0 WAIT AD-DA SAMPLE s =1e5Hz 15 SCOPE 1:1 Note: Only use the scope for educational purposes To get a quality recordg, leave the scope stopped Calculation of the average power of the output of the filter cos(wt) 1 S-Cos Gen re freq =1000. Hz 1 im gsicos0 phi A cos(wt+phi) 4 1 re 2 2 im exp(-jwt) mult0 Complex sus generator Hz lp10 8.5Hz lp ga0 1/2 A cos(phi) 1/2 A s(phi) 9 2. ga1 _re _im 7 x² square0 11 Argument a 10 phase x² square1 requency reference geometric progression adds0 13 A² DECIBEL module Y2 = Phase degrees Y1 = Ga db start_ 14 start_out y1_x PLOTTER y2 u_out negate0 fig.3 113/124

8 fig.4 114/124

9 115/124

10 11.3 UNIVERSAL ILTER Prciple functional diagram It is given by the figure 4. Before the appearance of digital computers, this function was used to simulate the differential equations, especially Physics, the study of systems with state variables (described by differential equations). The S1, S2 and S3 outputs can successively and simultaneously realize the filters: highpass, band-pass and low-pass; this is what gave this function, where the name is UNIVERSAL ILTER. The sum of the high-pass and low-pass outputs can realize the notch or band-stop filter. Summator with the Weighted puts: a, b, c fig.4 Lear tegrator outputs transfer functions rom the transfer function H(p) = 1/tp defed , determe the relationships: 116/124

11 Derive the 4 followg transfer functions: w w w w Set the transfer functions their canonical form by identifyg the parameters if : w : w w w w w w w w w w w w w w w PRACTICAL WORKS or the clarity reasons of test diagram, the function which can calculate the Ga and the Phase of the Bode diagram was encapsulated under the name Bode fig.5 and detail fig.6. Realize the diagram of figure 7and take down the Bode diagrams of different transfer functions; compare them with the 8 to 11 figures diagrams. Determe each one s important characteristics. 0 Real Complex BODE bode0 fig.5 Ga Phase 117/124

12 118/124 fig.6 Reel Complex Ga Phase mult re im.5hz lp ga0 2 x² square0 3.5Hz lp ga1 5 x² square1 6 Argument phase 7 _re _im adds DECIBEL decbel0 9 1/2 A cos(phi) 1/2 A s(phi) A²

13 1 5 S4 2 freq Complexe sus generator 1 S-Cos Gen =1000. Hz 1 re im a S1 UNIVERSAL ILTER clear 3 INTEGRATE S2 clear addv0 ov 4 S3 INTEGRATE gsicos0 phi -b wsum30 tega0 tega1 Ga and Phase calculation -c negate0 9 SCOPE 1:1 requency reference geometric progression 0 WAIT AD-DA SAMPLE s =1e5Hz start_out 8 u_out PLOTTER start_ y2 y1_x Real 2 BODE Complex bode0 Y2 = Phase degrees Y1 = Ga db Ga Phase fig.7 119/124

14 120/124

15 fig.8 fig.9 121/124

16 fig /124

17 fig /124

18 124/124

Signal Processing. Level IV/V CITE, BTS/DUT/Licence. i_5. i_6 LOWPASS. 5 in2. w0 =6000rad/s xi =.8; G =3 lp2a1. mul0. Filtre passe-bas.

Signal Processing. Level IV/V CITE, BTS/DUT/Licence. i_5. i_6 LOWPASS. 5 in2. w0 =6000rad/s xi =.8; G =3 lp2a1. mul0. Filtre passe-bas. Signal Processing Level IV/V CITE, BTS/DUT/Licence. Modulation FSK à phase continue i_8 Tension de commande V1 Interrupt SCOPE AD-DA EVENT Fs = 1E5 Hz 1:1.15 i_4 Modulation FSK à phase continue LOWPASS