A Software Implemented Spread Spectrum Modem based on two TMS320C50 DSPs

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A Software Implemented Spread Spectrum Modem based on two TMS320C50 DSPs Eric Kooistra Eindhoven University of Technology, Faculty of Electrical Engineering, Telecommunications Division, P.O.

1 A Software Implemented Spread Spectrum Modem based on two TMS320C50 DSPs Eric Kooistra Eindhoven University of Technology, Faculty of Electrical Engineering, Telecommunications Division, P.O. Box 513, 5600 MB Eindhoven, The Netherlands, fax: +31-(0) Abstract A BPSKIDS-CDMA modem is described. Many functions of this spread spectrum modem are implemented in software on a DSP board. Constraints for proper IF receiver operation are given, plus BER measurement results for a prototype and a frequency-synthesizer resolution enhancement algorithm. Brief description of the poster session The poster session describes the design of a direct-sequence spread spectrum modem based on a signal processing board that contains a D/A-converter, an AID-converter, and two digital signal processors (DSP) [2,3]. The spread spectrum signal is generated at baseband by multiplying each bit with the pseudo-noise code, so Tb=NcTc where Nc is the code length [chips]. The modulation scheme applied is BPSK with square-root raised-cosine pulse shaping of the chips (p 1). The IF receiver demodulates the input signal at an intermediate frequency (e.g. hr128 khz) through coherent subsampling, using a software Costas loop for carrier tracking. This subsampling creates a baseband replica by spectrum folding (p2). The despreading also occurs in software by means of a serial search code acquisition scheme, and a delay-lock loop (DLL) for code tracking [6]. The proper operation of the DLL and Costas loop is determined by three constraints that concern the resolution of the sample frequency its and chip rate!c, the loop bandwidth BL and the loop sample frequency ff [1,4,5] (p3). A prototype version of the modem was built using one TMS32OC25 DSP. This prototype can achieve 16 kchip/s and measurement results are presented of its bit error rate performance (p4). A new design of the modem uses two TMS32OC50 DSPs. On this new modem a multiple correlator scheme can be implemented, in order to increase the sample frequencies of the loops, so fs»ij, instead of fs=fb' Furthermore, thanks to a smooth resolution enhancement algorithm, both the sampling frequency and the chip rate can be generated by means of the timers of the DSPs. The algorithm has a recursive structure and is implemented by means of a look-up table. The O's and 1 's in this table state whether the next timer period has to be T or T+l [.1.Tmin], and the size of the table determines the resolution enhancement factor (e.g. a factor 7). Together the two DSPs are expected to be sufficiently powerful to implement in software all functions of the baseband transmitter and IF receiver for chip rates up to 64 kchip/s (p5). References [1] Best, E.B., Phase-locked loops, theory, design and applications, second edition, McGraw Hill, 1993 [2] Kamperman, F.L.A.J., Design study for a spread-spectrum picoterminal satellite network and the realization of a modem, IVO Report EUT, Telecommunications Division, 1993 [3] Kooistra, E., On the development of a spread spectrum transceiver based on a digital signal processor, IVO Report EUT, Telecommunications Division, 1995 [4] Lindsey, W.C., C.M. Chie, A survey of digital phase-locked loops, Proceedings IEEE, Vol. 69, pp , Apr [5] Natali, P.D., All-digital coherent demodulator techniques, Proc. lnt. Telemetering Conf., Vol. VIII, pp , Oct [6] Ziemer, R.E. and R.L. Peterson, Digital communications and spread spectrum systems, Macmillan Publishing Company,

2 The BPSK / DS-CDMA transceiver pi The baseband transmitter and modulator data c od e d; Data signal Pi Pulse i --..t fb spreader shaping I DAC f--~ LPF T fo. filter f DAC Pi I' Vo(t) = Ad(t)p(t), , cos(21tfil,t) BPSK modulator C25-transceiver Transmit clock analog IF carrier oscillator The IF receiver BPFR Frequency synthesizer To analog amplifiers in the receiver AGC,-{ Receiver control I frs NCO J~, 2(,,. Vi Digital I,Q Pulse shaping ~ - data.. ADC f-+ --JI> Despreading r flf down conversion HR(z) i fb i C25-transceiver Tasks: Demodulation Despreading ~databits 92

3 Demodulation by subsampling p2 4 Digital I,Q downconversion, ffs = 2m+ 1 fif Time domain: = sample moment t Frequency domain: Baseband replica 93

4 p3 Oespreading by correlating with the code I It====== ~ Correlators Correlators Code tracking Early Late IF in Baseband PN code generator i Chip rate NCO 1'01-",, Data out Digital Central l'v lc ~ Nc downconverter VI I VIC> V QC ADC I,Q ~-' i Correlators If i f l VQ ' ' Nd Frequency fro synthesizer Costas loop Sampling frequency Carrier tracking Code Code phase! shift II I acquisition I i I j -- ::::]. 1 1.,, 1 Receiver control I 1 I... _.. * Functions: 1 Code acquisition (coarse) 2a Code tracking delay-lock loop, DLL (fine) 2b IF carrier tracking Costas loop Constraints for the loops:. 1 DLL: ~Tmin< SON f ' d c Costas: LiT ;in < O.SBL, Tc ~fmin< O.SBL, 94

5 Performance of the C25-transceiver p4 BER measurement results: 10 2~~~~~,..,.,..,..,..,~~~-:-c-:-:-:-:-~~~~~.,...,..,...,~ :::: ::::: ::,:: ::::: ::: ::,:,:::,::,: ::,: :::.::: :::.:::: ::::::: :,:: :: :::::,:,::::::,.:::,: ::::... : : : : : : : : : : : : ::: : : : : : : : : : : ::: : : : : : : : ' : : : ~ : : :: : : : : : : : ~ : : ; : : : : : : : : :::: ::::::::: ~ : : : : : : : : : : : ;.:.:::::::,, "... '., ' '.',, l', ', '.'.,, (.,. ',',...,.. ","",-,...,:...,... ':'.,...,...,. : '..,... ".. :...,...,' ':... ".., ~ ,... -'...,...,...,...,......,..., '...,...,...,., ~...,,..,,.".. ~~~ T~~!!~~~~!::T!n!~:Ly!!:!::d:::::~::::~i::;»::: :TT::\~:::: ::<~T>:T:... ".,...,..., ','.. """.,.".,;'"...,' "',""..,. '.'...,.,.,,'.., '.,,... ",".,."""...,...,...,.... "... "..,...,.,,, ' '1...,..,.... :. ~ : : ~ : : :. : ::: : : : : : : : : : : ::: : : : : : : :~: ~: : :. ~ : ~ : : : : : ~ ~ : : : : : ~ ~ : ~. :::. : :. : : : : : : : : : : : : : : : : : : : ;: ::.....,., : - : Nc=15 : : :,,: :!::.7!!::!!!!!:: i::!!!::::!!!!!::::::!: J::!:!:':::i!::,,:::!!::!::' '-tl,,':!::::::::::,..""",..:"..,.. ".,.;... "... ";...,..,,. ':.,.. "....;.,... "".,;,...,.,.,..., " ~ ~ ::]:]!:: i!!!:::::::: ::!;: : :;: : ~ : :! ::::::: i: : : : : ~ : ::::::!::::!:;:::::::: j : \ : ; :!::!:: ~ ::::::::::::::::::::::::}:::::::::::1:::::::::::::::::::::::::::::::::::::i:::: ::::::1:\:::::::..,,...,., " ' :. ;.,,.". "', '..,,....,...,, ~... '...,': " , _...L..-_...I..-_-.l..-.._-1--_--'---_--'--_---:""::-_-----: Eb/No [db] Chip rate: fc ~ 16 kchip/s (due to limited processor capabilities) Bit rate: fb ~ 250 bitls (due to the minimum update frequency fs of the control loops ) code length: Nc = 63 chips 95

6 The CSO-transceiver p5 Schematic diagram of the DSP board: Receiving t Transmitting ~r ADC DAC L ;). I timer I TMS320 C50.. timer J TMS320 C50 Expected performance: - fc = 64 kchip/s - Increased fs by means of multiple correlators Particularities: ADC samples switch - Two timers for generating Tc and T fs ~:~:~:~:~:~:~ ~ 0,0,1,0,0,0,1.4 "'R p 0, 1,0, 1,0,0, 1 Resolution enhancement algonthm, e.g.: 0,1,1,0, 1,0,1 0, 1, 1, 1, 0, 1, 1 0, 1, 1, 1, 1, 1, 1 1, 1, 1, 1, 1, 1, 1 96

THIS work focus on a sector of the hardware to be used

THIS work focus on a sector of the hardware to be used DISSERTATION ON ELECTRICAL AND COMPUTER ENGINEERING 1 Development of a Transponder for the ISTNanoSAT (November 2015) Luís Oliveira luisdeoliveira@tecnico.ulisboa.pt Instituto Superior Técnico Abstract