Oversampling D/A Converter Design for Improved Signal to Quantization Noise Ratio

Transcription

1 International Journal of Computer Trends and Technology (IJCTT) volume 8 Number 4 October 5 Oversampling D/A Converter Design for Improved Signal to Quantization Noise Ratio Himanshu Mahatma, Rajesh Mehra, 3 Gyan Prakash Pal,3 ME Scholar, Associate Professor,, 3 Department of Electronics & Communication Engineering National Institute of Technical Teachers Training & Research, Chandigarh, India Abstract - Signals dealt in real world are mostly analog in nature and are needed to convert them in digital format before processing; finally when these signals are again represented to real world a reverse conversion is necessary. The accuracy of this conversion is dependent on number of bits used and/or number of samples taken during conversion, the error between the original signal and reconstructed signal represents a noise called quantization noise. This noise can be reduced if the numbers of samples are increased. The oversampling technique is used to increase the number of samples, which reduces the spacing between the samples so the accuracy of the output is improved and SNR is increased. To further improve the performance of D/A converter, sigma delta modulator with one bit quantization level is used to decrease word length while maintaining good resolution. In this paper, some examples are used to show D/A conversion with improved SQNR by using oversampling technique. Keywords: oversampling, D/A converter, sigma delta modulator, multirate signal processing, single-bit quantization, multi-bit quantization. I. INTRODUCTION Apart from processing in discrete time most of the real world signals are in continuous time, for example speech, music and other multimedia signals. Means that we have to obtain continuous signal finally no matter what kind of processing we have done earlier in digital format []. Most of such signals like for telephony, wireless radio signals, industrial measurement and instrumentation signals, and other audio signals are processed by digital signal processing techniques. The inputs and outputs of these processors are conventionally in analog form so some interface stages are needed which can convert the signal in digital form needed by processing core and then back to analog form []. So it is necessary to relate analog and discrete signals both in time and frequency domain []. Figure : Digital processing system with an ADC and DAC at the input and outputs Figure : (a) DAC Symbolic representation; (b) input-output relation of a DAC showing effect of quantization When digital signal is converted into analog form to output is actually a staircase like waveform, so a smoothing filter is needed after the converter which is also known as reconstruction filter[]. Figure 3: Block diagram representation of the discrete-time digital processing of a continuous time signal The DAC output contains desired frequency components as well as high frequency image components located at the multiples of the sampling frequency which may be not audible but can cause intermodulation products and overloading of amplifier [3]. When using converters near at nyquist rate the accuracy is achieved at most to 4 bit due to dependency on matching components used, more than that it may become impractical to implement [4]. Also ISSN: Page 67

2 International Journal of Computer Trends and Technology (IJCTT) volume 8 Number 4 October 5 the reconstruction filter must have sharp cut off filter involving very higher order reconstruction filter with high precision components []. Other converters like counting converters have very long conversion time for each sample which limits them to be used for low frequency application. Various applications in real world uses these techniques in improving characteristics like image compression [6], OFDM transceivers [7], applications like modern wireless communication [8], PSO based IIR design [9] and error reduction techniques [] also finds application areas in these type of converters. II. OVERSAMPLED DATA CONVERTER Such converters use oversampling of data combined with noise filtering via feedback to reduce quantization noise to very low levels. The resulting reduction in speed is much less compared to conventional converters [4]. Oversampling deals with this problem by tolerating wide transition band in frequency response of reconstruction filter which requires low precision circuit components but more complex digital interpolation filter []. The idea of oversampling is to increase the sampling rate of the digital signal manifolds typically from 3 to 4 times [4]. This result in finer spacing between samples so that relatively simple reconstruction filter is required for smoothing out of band noise. The quantization noise power is spread over a wide band evenly which makes possible high resolution DAC conversion with help of low resolution D/A converter [3]. Figure 6: Block diagram of SDM using error feedback [5] A. Single Bit Modulator In single bit sigma delta modulator performance is improved by one bit quantizer which extracts the MSB from its inputs and subtracts remaining LSBs bits in form of quantization noise from input. The output MSB is passed from a one bit DAC and filtered by a reconstruction filter to remove unwanted frequency components. The spectrum of quantized output is nearly same as its inputs []. Figure 7: The Sigma Delta Quantizer. [] The input-output relation of the quantizer is given by y[n]-e[n]=x[n]-e[n] y[n]=x[n]+e[n]-e[n] () Figure 4: Block diagram representation of oversampling D/A conversion [] Where y[n] is MSB of nth sample of the adder output and e[n] is the nth sample of quantization noise composed of all except MSB bit []. III. SIGMA DELTA D/A CONVERTERS Sigma delta converter uses techniques which can reduce word length while maintaining sufficient resolution of digital signals. To keep mismatch error low one bit word length is desirable to input of converter. This can be implemented by a one bit quantizer in sigma delta modulator. But this introduces large quantization noise to be removed by analog expansive filter and also stringent requirement on clock jitter []. To deal with this problem order of SDM may be increased but the stability is reduced []. B. Multibit Modulator A variant of single bit modulator can be implemented as multibit SDM in which N bit input signal is splitted in two parts of L & M bits representing LSB and MSB which are then further processed by corresponding adders & delays [5]. Figure 5: Implementation of sigma delta DAC [4] Figure 8: A bit split realization of DSDM using first order implementation [5]. ISSN: Page 68

3 International Journal of Computer Trends and Technology (IJCTT) volume 8 Number 4 October 5 IV. Oversampling D/A Conversion An Example is taken, to analyze the oversampling D/A conversion with low resolution D/A converter. First we choose an input digital signal with base sampling rate fs of units and observe its reconstruction to analog waveform (fig.9), which is an inaccurate analog output signal index index Figure : Oversampling of BSR, f s=f s Figure 9: Base Sampling rate (BSR), f s = units We further increase sampling rate by L=4 and f s =4f s to get nearly perfect analogous to input waveform with high SNR. Next we increase sampling frequency to the same sequence by oversampling factor L= and f s =f s and see the effect of oversampling in its output. ISSN: Page 69

4 International Journal of Computer Trends and Technology (IJCTT) volume 8 Number 4 October index [3] Emmanuel C. Ifeachor, Barrie W. Jervis Digital Signal Processing Pearson Education, ISBN , pp86-87, Second Edition, 7. [4] Gabor C. Temes Oversampling A/D And D/A Converters Dept. of Electrical and Computer Engineering, Oregon State University, Corvallis, OR 9733, USA [5] Nadeem Afzal and J Jacob Wikner Power Efficient Arrangement of Oversampling Sigma-Delta DAC / IEEE, pp. -4, [6] Sugreev Kaur, Rajesh Mehra, High Speed and Area Efficient D DWT Processor based Image Compression" Signal & Image Processing An International Journal(SIPIJ) Vol., No., December [7] Shaminder Kaur, Rajesh Mehra, FPGA Implementation of OFDM Transceiver using FFT Algorithm International Journal of Engineering Science and Technology (IJEST), ISSN : , Vol. 4 No.4 April [8] Rajesh Mehra, Garima Saini, Sukhbir Singh, FPGA based high speed BCH encoder for wireless communication applications, Communication Systems and Network Technologies (CSNT), International Conference pp [9] Lipika Gupta, Rajesh Mehra, Modified PSO based adaptive IIR filter design for system identification on FPGA, International Journal of Computer Applications ( ) Volume No.5, pp-7 May [] Rajesh Mehra, Abhishek Singh, Real time RSSI error reduction in distance estimation using RLS algorithm, Advance Computing Conference (IACC), 3 IEEE 3rd International, pp66-665, 3. [] M. Aboudina and B. Razavi, A new DAC mismatch shaping technique for sigma-delta modulators, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 57, no., pp , dec. [] N. Afzal and J. J Wikner, Study of modified noise-shaper architectures for oversampled sigma-delta DACS in NORCHIP, pp. 4, Nov...5 Authors: Figure : Oversampling of BSR, f s=4f s V. CONCLUSION So far we have studied the effect of oversampling technique and sigma delta modulator in digital to analog conversion process. In this paper the results are shown for different sampling rates, f s, f s and 4f s to improve output signal quality. Also the quality of reconstructed signal is much better as compared to previously generated signals with more precise representation of original analog signal. REFERENCES [] Sanjit K Mitra Digital Signal Processing Tata McGRAW-Hill, ISBN , pp7, pp9-9, Third Edition, 6 [] G. C. Temes, An Overview of Nyquist-Rate and Oversampled Data Converters in Telecommunications, Actas I. Conferencia Nacional de Telecommunicacoes, Aveiro, Portugal, pp. 58, April, 997. Himanshu Mahatma is currently associated with Board of Technical Education Rajasthan and working as Lecturer in Govt. Women s Polytechnic College Bikaner, Rajasthan in Electronics and communication Engineering Department since 9. He is ME Scholar at National Institute of Technical Teacher s Training & Research, Chandigarh, India. He completed his Bachelor of Engineering in ECE from Rajasthan University in 6. His research areas are Digital Signal Processing and Embedded system design. Dr. Rajesh Mehra: Dr. Mehra is currently associated with Electronics and Communication Engineering Department of National Institute of Technical Teachers Training & Research, Chandigarh, India since 996. He has received his Doctor of Philosophy in Engineering and Technology from Panjab University, Chandigarh, India in 5. Dr. Mehra received his Master of Engineering from Panjab Univeristy, Chandigarh, India in 8 and Bachelor of Technology from NIT, Jalandhar, India in 994. Dr. Mehra has years of academic and industry experience. He has more than 5 papers in his credit which are published in ISSN: Page 7

5 International Journal of Computer Trends and Technology (IJCTT) volume 8 Number 4 October 5 refereed International Journals and Conferences. Dr. Mehra has 55 ME thesis in his credit. He has also authored one book on PLC & SCADA. His research areas are Advanced Digital Signal Processing, VLSI Design, FPGA System Design, Embedded System Design, and Wireless & Mobile Communication. Dr. Mehra is member of IEEE and ISTE. Gyan Prakash Pal received the Bachelors of Technology degree in Electronics and Communication Engineering from Uttar Pradesh Technical University, Lucknow, India in 5, and Perusing Masters of Engineering degree in Electronics and Communication Engineering from National Institute of Technical Teachers Training & Research, Panjab University, Chandigarh, India. He is an Assistant Professor in the Department of Electronics & Communication Engineering, Shanti Institute of Technology, Meerut, India. He has 9 years of academic and industry experience. He has more than 5 papers in his credit which are published in refereed International Journals and Conferences. His research areas are Advanced Digital Signal Processing, Computer Networking, VLSI Design, and Wireless & Mobile Communication. He is member of IEEE. ISSN: Page 7