RECENT advances in MEMS technology, coupled with

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1 1740 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks Yuen Hui Chee, Student Member, IEEE, Ali M. Niknejad, Member, IEEE, and Jan M. Rabaey, Fellow, IEEE Abstract This paper presents the principles for designing low-power transmitters for wireless sensor networks. Based on these principles, an injection-locked transmitter is implemented in a standard m CMOS process and packaged using chip-on-board assembly. The transmitter utilizes a film bulk acoustic resonator (FBAR) to obtain a stable carrier at 1.9 GHz. At 0 dbm output power, the transmitter achieves an efficiency of 32% at 50 kb/s and 28% at 156 kb/s. With 50% on-off keying, the transmitter consumes 1.6 and 1.8 mw, respectively. Index Terms Film bulk acoustic resonator (FBAR), injection locking, low power, MEMS, transmitter, wireless sensor networks. I. INTRODUCTION RECENT advances in MEMS technology, coupled with low-power, low-cost digital and RF circuits, have made it conceivable to build a dense network of inexpensive wireless nodes, each having sensing, computational, and communication capabilities [1]. These wireless sensor networks (WSNs) are expected to be widely used in a vast variety of applications such as office environmental control, warehouse inventory, smart homes, interactive toys, and data collection. The key challenge in widespread deployment of such networks is to build an energy-self-sufficient sensor node, since it is infeasible to replace batteries of thousands of sensor nodes or attach a large energy-scavenging unit to each node. Among all its functions, communication between nodes typically accounts for most of the energy budget and, hence, it is essential to have an energy-efficient transmitter. In typical WSN applications, the distance between neighboring nodes is less than 10 m and the required radiated power is less than 1 mw [1]. At such a low radiated power, the power consumption of the circuits prior to the power amplifier (pre-pa power) is significant and degrades the transmitter efficiency substantially. For example, in the direct-modulation transmitter reported in [2], the power amplifier (PA) achieves a drain efficiency of 40% while delivering 250 W but its pre-pa circuits consumes 675 W, thus reducing the transmitter efficiency to 19%. The pre-pa power is even more significant in the traditional direct-conversion transmitter due to higher complexity. For instance, the pre-pa circuits in [3] consume about 15 mw, degrading the efficiency of the direct-conversion transmitter to 3.3% at 0 dbm output power. Thus, at low radiated power, an ef- Manuscript received December 14, 2005; revised March 21, This work was supported in part by the Defense Advanced Research Projects Agency (DARPA) under Grant N The authors are with the Berkeley Wireless Research Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, CA USA ( yhchee@eecs.berkeley.edu). Digital Object Identifier /JSSC ficient transmitter requires both a high PA efficiency and a very low pre-pa power. Achieving both requirements concurrently is particularly challenging since a more efficient power amplifier often has a higher drive requirement, which leads to a higher pre-pa power. In this paper, we propose to use injection locking and RF MEMS to achieve higher transmitter efficiency at low radiated power levels. Injection locking allows the PA to be self driven to minimize its drive requirement [4], while high quality-factor ( ) RF-MEMS allows for low-power RF carrier generation to reduce the pre-pa power. Using these techniques, the injectionlocked transmitter radiates 0 dbm with an efficiency of 32% at 50 kb/s and 28% at 156 kb/s. With 50% on-off keying data, the transmitter achieves a power consumption of 1.6 and 1.8 mw, respectively. This paper is organized as follows. In Section II, the principles of designing low-power transmitters for WSN are presented. Based on these principles, the architecture and design of the injection-locked transmitter are discussed in Sections III V. Section VI presents the measured results and Section VII concludes this paper. II. DESIGN PRINCIPLES OF LOW-POWER WSN TRANSMITTERS A wireless transmitter can be modeled as a PA and a pre-pa block that represents all the circuits prior to the PA as shown in Fig. 1. In WSN applications, the transmitter is duty cycled; it wakes up, transmits the data and then returns to sleep before the next transmission. Thus, the average power consumption of the transmitter is given as where is the transmitter s setup time, is the transmit time, is the duty cycle period, is the transmitter s setup power, is the pre-pa power, is the radiated power, and is the PA drain efficiency. Though a lower packet rate and packet size can certainly reduce the average power consumption, they are often determined by nontransmitter-related factors such as the protocol being used, synchronization header, number of error correction bits, payload, and allowable latency. Thus, for a given packet size and packet rate, (1) shows that lower power consumption can be achieved by minimizing the following factors. A. Pre-PA Power In cellular and WLAN applications, the radiated power of the transmitter is much higher than its pre-pa power and setup (1) /$ IEEE

2 CHEE et al.: AN ULTRA-LOW-POWER INJECTION LOCKED TRANSMITTER FOR WIRELESS SENSOR NETWORKS 1741 Fig. 1. Model of a wireless transmitter. Fig. 2. Block diagram of the injection-locked transmitter. power. Thus, the transmitter efficiency is mainly determined by its PA efficiency. On the other hand, in WSN applications, the pre-pa power is comparable or higher than the radiated power. This is because the required radiated power is less than 1 mw (due to the short communication distance between neighboring nodes), and the pre-pa power does not scale with communication distance. As a result, reducing the pre-pa power, rather than decreasing the radiated power or improving the PA efficiency, will result in higher power savings. To achieve a low pre-pa power, the number of circuit blocks and their power consumption have to be minimized. The number circuit blocks can be reduced by using simpler transmitter architectures such as the injection-locked transmitter and the direct modulation transmitter. These simple transmitter architectures are applicable because the low data rate and low spectral efficiency requirements in WSN applications allow for the use of less complex modulation schemes such as on-off keying or frequency shift keying. The circuit power consumption is reduced by using high- RF MEMS and passives to reduce losses, and subthreshold MOSFET operation to achieve a higher transconductance efficiency. The use of subthreshold transistors to design gigahertz circuits is possible because today s submicron CMOS transistors have greater than 100 GHz. B. PA Power When the pre-pa power is reduced to less than the radiated power, improving the PA efficiency now becomes more effective in reducing the average power consumption. However, a more efficient PA typically demands a higher drive requirement, resulting in a higher pre-pa power. Therefore, it is challenging to design an efficient transmitter at low radiated power since it requires both a high PA efficiency and a very low pre-pa power. To overcome this tradeoff, injection locking and high- RF MEMS are used to reduce the PA drive requirement and pre-pa power simultaneously. To further reduce the transmitter power consumption, the entire transmit chain is optimized concurrently. In addition, power control scheme can also be used to reduce the radiated power when two nodes are close together or when the communication channel between them is good. C. Transmitter Active Time Equation (1) shows that in order to reduce the transmitter power consumption, both the transmit time and setup time have to be minimized. The transmit time can be decreased by increasing the data rate. However, a higher data rate typically requires a higher transmit power to achieve the same bit error rate and increases the receiver power due to tighter constraints on timing recovery, higher analog-to-digital (A/D) sampling rate, and possibly more complex modulation schemes. Thus, the transmitter power savings obtained with a higher data rate must be weighed against the power increase in other parts of the transceiver. Typically, the data rates for WSN applications range from tens of kb/s to a few hundreds of kb/s [1]. In WSN applications, the setup time can be a significant overhead due to the short packet size. To achieve a short setup time, the frequency synthesizer and operating points of the circuits must be designed to settle to their steady-state value quickly. III. TRANSMITTER ARCHITECTURE The injection-locked transmitter [5] consists of a reference oscillator and a power oscillator as shown in Fig. 2. The reference oscillator provides a stable carrier at 1.9 GHz and the power oscillator delivers 0 dbm to the antenna. With fewer active circuits, the transmitter has a lower pre-pa power and a higher efficiency. In the injection-locked transmitter, the power amplifier is replaced by an efficient power oscillator. The power oscillator is driven to the edge of the voltage-limited regime, allowing the output voltage to swing closer to the supply to minimize its device loss. Since the power oscillator is self-driven, it does not have a large drive requirement and its pre-pa power is reduced considerably. The antenna loads the output tank of the power oscillator and degrades its -factor. Thus, the power oscillator suffers from poor phase noise performance and has an unstable oscillation frequency. To stabilize the carrier frequency, the power oscillator is locked to a low-power reference oscillator, whose oscillation frequency is stabilized by a high film bulk acoustic resonator (FBAR) [6]. The startup time of the FBAR oscillator is only a few microseconds, resulting in a fast setup time. Baseband data is modulated onto the carrier using on-off keying by power cycling the power oscillator. Frequency shift keying can also be employed using a tunable FBAR oscillator. The data rate is the determined by the startup time of the power oscillator and its lock-in time. IV. INJECTION LOCKED POWER OSCILLATOR A. Injection Locking Injection locking is a nonlinear phenomenon whereby a free running oscillator, when perturbed by an external signal, changes its frequency to that of the external signal when their frequencies are close. This concept can be illustrated with an LC oscillator perturbed by a small signal having frequency as shown in Fig. 3 [7]. In the absence of the injected signal, the oscillator oscillates at its free running frequency and the current through the negative resistance is equal to the tank current in both magnitude and phase. When a

3 1742 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 Fig. 3. Oscillator under small perturbation. (a) Equivalent circuit. (b) Steady-state phasor diagram. (c) Frequency response of the LC tank. small signal with frequency is injected, it introduces a phase shift between and. This causes the LC tank to oscillate at to provide the necessary phase shift in order to maintain. For small perturbations (i.e., small and ), the dynamics of this pull-in process are described by Adler s equation [8], given as (2) where is the quality factor of the LC tank and is the instantaneous beat frequency. When the oscillator achieves lock, and the single-sided lock-in range is given as (3) Fig. 4. Schematic of the injection-locked power oscillator. The lock-in time is obtained by solving (2), which gives where and is the integration constant. B. Circuit Design The schematic of the power oscillator is shown in Fig. 4. The oscillator core consists of a cross-coupled transistor pair to provide the negative resistance needed for sustained oscillation, and an LC tank to set the oscillation frequency at 1.9 GHz. The LC tank consists of two bond wire inductors and, a 5-bit switched capacitor array, bond pad capacitances, interconnect capacitances and drain capacitances of transistors and. Bond wire inductors are used because of their high -factors to reduce losses. To deliver 1 mw from a supply of approximately 300 mv, the 50- antenna is (4) transformed into a 200- differential load using a 1:4 balun. The loads the output tank of the LC oscillator and reduces its -factor, which degrades the oscillator s phase noise and frequency stability. To stabilize the frequency of the power oscillator, injection locking is used to synchronize to the carrier frequency provided by the FBAR oscillator using transistors and. Due to the high- FBAR resonator, the FBAR oscillator provides a stable carrier frequency with good phase noise performance. Since the power oscillator is self-driven, its drive requirement is greatly reduced and the widths of transistors - are chosen to be small to minimize their loading on the FBAR oscillator and to improve reverse isolation. Three parallel cross-coupled transistor pairs with binary weighted widths are used for power control [9]. Parallel devices are preferred over a programmable tail current source because they eliminate the voltage headroom needed for the tail current source, and therefore maximizes the available voltage swing and efficiency of the cross-coupled transistors

4 CHEE et al.: AN ULTRA-LOW-POWER INJECTION LOCKED TRANSMITTER FOR WIRELESS SENSOR NETWORKS Device loss is further reduced by driving the oscillator to the edge of the voltage-limited regime. A 5-bit switched capacitor array is employed to mitigate the variations of the bond wire inductance and to ensure that lies in the lock-in range. The LSB of the capacitor array is chosen such that MHz to reduce the lock-in time. The size of the switches is chosen so that the of the capacitor array is more than 60 to minimize losses. The transistor pairs and are each controlled by a foot switch to allow for on-off keying modulation. C. Lock-in Range and Lock-in Time The lock-in range is inversely proportional to the tank and, and proportional to as shown in (3). Since the tank and are determined by the output power, antenna load and tank inductor, has to increase to widen. With GHz and, is equal to 12 MHz when is chosen to be 5%. The lock-in range is sufficient since the capacitive array has a resolution of 4 MHz to ensure that MHz. The data rate depends on the lock-in time, which is given in (4). For a fast lock-in time, it is desirable to have a large and a small.for MHz, MHz and, the lock-in time is estimated to be about 300 ns. Faster lock-in time can be achieved by increasing or using a finer resolution capacitor array to reduce. D. Layout The layout of the power oscillator is given in Fig. 5. It uses an L-shaped differential trace to provide two orthogonal outputs to the antenna and the bond wire inductors. Orthogonal outputs minimize mutual coupling between the bond wires and allow for easy placement of the balun and the bond wire inductors. To minimize the interconnect capacitance, the cross-coupled devices are sandwiched in between the output differential traces. With less interconnect capacitances, a larger inductor can be used to increase the efficiency or a larger capacitor array can be employed to achieve a wider tuning range. The capacitor bank and the injection-locking devices are placed next to the cross coupled devices to minimize their interconnect capacitances. V. ULTRA-LOW-POWER FBAR OSCILLATOR A. Film Bulk Acoustic Resonator (FBAR) Recent advances in MEMS technology have made it possible to fabricate MEMS devices that operate at RF frequency. RF MEMS devices offer potential for higher integration, lower power consumption and better linearity than traditional components [10]. One such RF MEMS device is the FBAR [6]. The FBAR resonator consists of a thin layer of Aluminum-Nitride piezoelectric material sandwiched between two metal electrodes and supported by a micromachined silicon substrate as shown in Fig. 6(a). The metal/air interfaces serve as excellent reflectors to form a high- acoustic resonator. The FBAR occupies only about m m [see Fig. 6(b)] and it can be integrated into standard CMOS process [11]. The FBAR resonator is modeled using the modified Butterworth Van Dyke circuit [12] as shown in Fig. 6(c).,, Fig. 5. Layout of the injection-locked power oscillator. and are the motional inductance, capacitance, and resistance, respectively. models the parasitic parallel plate capacitance between the two electrodes and and accounts for the electrode to ground capacitance. Losses are modeled by, and. As shown in Fig. 6(d), the FBAR behaves like a capacitor except at its series and parallel resonances, where it exhibits a -factor of more than This high -factor allows the implementation of low-power, low-phase-noise oscillators. In addition, the FBAR can be co-designed with the circuit to eliminate the 50- termination requirement (e.g., in SAW filters) to achieve a lower power dissipation. B. Circuit Design The schematic of the FBAR oscillator [13] is shown in Fig. 7. The oscillator uses the Pierce configuration with a CMOS inverting amplifier comprising of transistors and. A large resistor is used to bias the gate and drain of the transistors at to maximize the allowable voltage swing and minimize its loading on the resonator. Transistors and share the same current but their transconductances and sum. Thus, only about half the current is needed to provide the needed for oscillation. Further reduction in power is obtained by operating and in the subthreshold regime to achieve a higher. The drain-source voltage of transistors and is designed to be a few to achieve a high output resistance and minimize its loading on the resonator. Capacitance and include capacitances from the FBAR electrodes, transistors, bond pads and interconnects. They transform the amplifier transconductance into a negative resistance. In subthreshold operation, and thus, a higher negative resistance requires a higher current consumption. The impedance looking from FBAR across node X and node Y is given as [14] (5)

5 1744 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 Fig. 6. Film bulk acoustic resonator (FBAR). (a) Structure. (b) Die photo. (c) Equivalent circuit. (d) Frequency response. Fig. 7. Schematic of the FBAR oscillator. where,, and. To ensure the oscillator startup, the negative resistance is typically designed to be about 2 to 3 times higher than. When the oscillator voltage swing increases to a sufficiently large amplitude, it pushes and into gain compression, which reduces and. Steady-state oscillation is reached when is equal to the large signal. Fig. 8 shows a plot of the negative resistance as a function of and for ms, pf and. For a given, there is a pair of and that minimizes. By varying, the maximum negative resistance and its corresponding and can be found for each. With and to ensure startup, the minimal is 7.8 ms and ff. Using complementary devices with each contributing equal transconductance, we have ms. Fig. 8. Negative resistance of FBAR oscillator as a function of C and C. VI. EXPERIMENTAL RESULTS The injection-locked transmitter is implemented in a standard m CMOS process from ST Microelectronics. The FBAR resonator and the CMOS dies are packaged onto a test board using chip-on-board assembly as shown in Fig. 9. Two short bond wires are used to connect the FBAR to the CMOS die to minimize parasitic and avoid spurious oscillations. Each bond wire is estimated to be approximately 250 ph and is taken into account in the design. Fig. 9(a) shows that the bond pads for the FBAR electrodes are not identical. The capacitance of the smaller force electrode is 20 ff whereas the capacitance of the larger sense electrode is 150 ff. These are also incorporated into the design to ensure that ff to maximize the negative resistance at GHz. Two parallel bond wires, each

6 CHEE et al.: AN ULTRA-LOW-POWER INJECTION LOCKED TRANSMITTER FOR WIRELESS SENSOR NETWORKS 1745 Fig. 9. Close up of the chip-on-board assembly of the (a) FBAR oscillator and (b) power oscillator. approximately 2.5 mm long, are used as inductors for the power oscillator. The injected signal is fed from the FBAR oscillator through a balun and the output of the power oscillator is connected to the 50- antenna using a 1:4 balun to provide a 200 load to the power oscillator. Due to the number of test and biasing pads needed, the FBAR oscillator and the power oscillator occupies about mm and mm, respectively. When integrated into a transceiver, only the active circuitry is needed and the required area is reduced to about 0.4 mm. Fig. 10 shows the measured transmitter efficiency as a function of radiated power at various power oscillator s supply when the power oscillator is locked to the FBAR oscillator. Power control is realized using three binary weighted cross-coupled transistors -. For a targeted output power, there is an optimal supply voltage that maximizes the transmitter efficiency as indicated by the dotted line. With 0 dbm output power, the transmitter efficiency is 32% and it consumes 1.6 mw for on-off keying data with equal probability of 1 and 0. The efficiency of the power oscillator is 33% and the FBAR oscillator degrades the efficiency by only 1% with a minimal power consumption of 90 W. This clearly demonstrates the effectiveness of using injection locking to reduce the power oscillator drive requirement and hence the pre-pa power. The phase noise performances of the transmitter before and after injection locking are shown in Fig. 11. Prior to locking, the power oscillator suffers from a poor phase noise performance of 98 dbc/hz at 100 khz offset and 113 dbc/hz at 1 MHz offset due to its low -factor. When the power oscillator achieves lock, it tracks the phase of the FBAR oscillator and its phase-noise performance follows that of the FBAR oscillator. Due to the high FBAR resonator, the transmitter phase noise is improved to 120 dbc/hz at 100 khz offset and 132 dbc/hz at 1 MHz offset. The improvement in phase noise is evident in the output spectrum of the transmitter as shown in Fig. 12. Prior to locking, the output spectrum is broad and noisy. Once the power oscillator acquires lock, a clean and stable carrier frequency is obtained. Fig. 13 shows the amount of frequency pulling as a function of the output power. The carrier frequency changes by 50 khz when the output power varies from 4.3 dbm to 0 dbm. The measured supply pushing of the FBAR oscillator Fig. 10. Transmitter efficiency. Fig. 11. Phase noise performance of transmitter. is 3.88 MHz/V. When the supply of the FBAR oscillator varies by 10%, its frequency deviates less than 120 khz. The achieved frequency stability is acceptable for the targeted WSN receivers in [15] and [16], which have a bandwidth of 500 khz and 3 MHz, respectively. Fig. 14 shows the measured single-sided lock-in range as a function of the bias current of the injection-locking transistors and. A higher bias current increases the of these transistors, resulting in a higher injected signal and lock-in range. However, it also increases the power consumption of transistor and and degrades the overall efficiency. For MHz, the peak efficiency is reduced by about 1%.

7 1746 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 Fig. 12. Transmitter output spectrum. (a) Free running. (b) Injection locked. Fig. 13. Measured frequency pulling as a function of output power. Fig. 15. Measured lock-in time. Fig. 14. Measured lock-in range. Fig. 16. Waveform of on-off keying data. Fig. 15 shows the measured lock-in time for MHz as a function of the bias current of the injection-locking transistors and. Again, a higher bias current increases the injected signal and reduces the lock-in time. For MHz, the lock-in time is about 1.9 s. With the start up time of the power oscillator being less than 100 ns, the total overhead time is approximately 2 s. If the overhead time accounts for 10% of the symbol period, the transmitter can support on-off keying modulation at a data rate of 50 kb/s. The modulated on-off keying waveform at 50 kb/s is shown in Fig. 16. A higher data rate is obtained by increasing the injected signal. When the bias current is increased to 516 A, the lock-in time is decreased to 540 ns. Thus, the overhead time is reduced to 640 ns and the transmitter can support data rates up to 156 kb/s. At this bias current, the transmitter efficiency is reduced to 28% and it consumes 1.8 mw for 50% on-off keying data. To reduce the lock-in power, a 5-bit capacitor array is used to tune close to. Fig. 17 shows the output frequency as a function of the capacitor code. The capacitive array has a tuning range of 103 MHz with a resolution at most 4 MHz. This resolution allows to be tuned to be within 2 MHz of. VII. CONCLUSION In this paper, we have established the principles for designing low-power transmitters at low radiated power levels. At low

8 CHEE et al.: AN ULTRA-LOW-POWER INJECTION LOCKED TRANSMITTER FOR WIRELESS SENSOR NETWORKS 1747 TABLE I COMPARISON WITH EXISTING STATE-OF-THE-ART WSN TRANSMITTERS ACKNOWLEDGMENT The authors would like to thank Agilent Technologies for the FBAR resonator and ST Microelectronics for the CMOS fabrication. Fig. 17. Measuring tuning range of capacitor array C. radiated power levels, the pre-pa power is significant and degrades the transmitter efficiency substantially. Thus, it is crucial to minimize the number of circuit blocks in the transmitter and reduce both their power consumption and active time. Based on these principles, we proposed using injection locking and RF MEMS to achieve higher transmitter efficiency at low radiated power levels. Injection locking allows the PA to be self driven to minimize its drive requirement, while high- RF-MEMS allows for low-power RF carrier generation to reduce the pre-pa power. The 1.9-GHz injection-locked transmitter is designed and implemented in a standard m CMOS process. At 0 dbm output power, the transmitter achieves an efficiency of 32% at 50 kb/s and 28% at 156 kb/s when active. With 50% on-off keying, the transmitter achieves a power consumption of 1.6 and 1.8 mw, respectively. The performance of the transmitter compares favorably with existing state-of-the-art WSN transmitters as shown in Table I. REFERENCES [1] J. Rabaey et al., PicoRadios for wireless sensor networks: the next challenge in ultra-low power design, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2002, pp [2] A. Molnar et al., An ultra-low power 900 MHz RF transceiver for wireless sensor networks, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2004, pp [3] P. Choi et al., An experimental coin-sized radio for extremely low power WPAN (IEEE ) application at 2.4 GHz, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2003, pp [4] K. C. Tsai and P. R. Gray, A 1.9 GHz, 1-W CMOS class-e power amplifier for wireless communications, IEEE J. Solid-State Circuits, vol. 34, no. 7, pp , Jul [5] Y. H. Chee, A. M. Niknejad, and J. Rabaey, An ultra-low power injection locked transmitter for wireless sensor networks, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2005, pp [6] R. C. Ruby et al., Thin film bulk wave acoustic resonators (FBAR) for wireless applications, in Proc. IEEE Ultrasonics Symp., Oct. 2001, vol. 1, pp [7] B. Razavi, A study of injection locking and pulling in oscillators, IEEE J. Solid-State Circuits, vol. 39, no. 9, pp , Sep [8] R. Alder, A study of locking phenomena in oscillators, Proc. IEEE, vol. 61, pp , Oct [9] M. Rofougaran, A. Rofougaran, and A. A. Abidi, A 900 MHz CMOS RF power amplifier with programmable output, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1994, pp [10] C. Nyguen, Vibrating RF MEMS for next generation wireless applications, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2004, pp [11] M. Dubois et al., Integration of high-q BAW resonators and filters above IC, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp [12] J. D. Larson, III et al., Modified Butterworth-Van Dyke circuit for FBAR resonators and automated measurement systems, in Proc. IEEE Ultrasonics Symp., Oct. 2000, vol. 1, pp

9 1748 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 [13] Y. H. Chee, A. M. Niknejad, and J. Rabaey, A sub-100 W 1.9 GHz CMOS oscillator using FBAR resonator, in IEEE Radio Frequency Integrated Circuits (RFIC) Symp. Dig. Papers, Jun. 2004, pp [14] E. A. Vittoz, M. B. R. Degrauwe, and S. Bitz, High performance crystal oscillator circuits: theory and application, IEEE J. Solid-State Circuits, vol. 23, no. 3, pp , Jun [15] B. Otis, Y. H. Chee, and J. Rabaey, A 400 W, 1.6 mw TX superregenerative transceiver for wireless sensor networks, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2002, pp [16] B. Otis, Y. H. Chee, R. Lu, N. M. Pletcher, and J. Rabaey, An ultra-low power MEMS-based two channel transceiver for wireless sensor networks, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp [17] T. B. Cho, D. Kang, C. H. Heng, and B. S. Song, A 2.4 GHz dualmode 0.18 m CMOS transceiver for Bluetooth and b, IEEE J. Solid-State Circuits, vol. 39, no. 11, pp , Nov Yuen Hui Chee (S 02) received the B.Eng. and M.Eng. degree from the National University of Singapore in 1998 and 2000, respectively. He is currently working towards the Ph.D. degree at University of California, Berkeley. Since 2001, he has been working on ultra-lowpower RF circuits for wireless sensor network applications. His current research interests are in the area of RF/analog integrated circuits and MEMS/circuit co-design, particularly applied to wireless communication circuits. He is the author or coauthor of more than 13 scientific papers. Mr. Chee was a recipient of the 2005 Analog Devices Outstanding Designer Award and a co-winner of the 2003 ISPLED design contest. Ali M. Niknejad (S 92 M 00) received the B.S.E.E. degree from the University of California, Los Angeles, in 1994, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1997 and 2000, respectively. From 2000 to 2002, he worked at Silicon Laboratories, Austin, TX, where he was involved with the design and research of CMOS RF integrated circuits and devices for wireless communications applications. He is currently an Assistant Professor in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. His current research interests are in the area of analog integrated circuits and device modeling, particularly as applied to wireless and broadband communication circuits. He is an active member of the Berkeley Wireless Research Center (BWRC) and he is the co-director of the BSIM Research Group. From 2002 to 2005, Dr. Niknejad was an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is currently serving on the Technical Advisory Board of CICC and ISSCC. He was a co-recipient of the ISSCC 2004 Best Technology Directions Paper Award and the RFIC 2005 Best Student Paper Award. Jan M. Rabaey (F 95) received the E.E. and Ph.D. degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium, in 1978 and 1983, respectively. From 1983 to 1985, he was connected to the University of California, Berkeley, as a Visiting Research Engineer. From 1985 to 1987, he was a Research Manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He has been a visiting Professor at the University of Pavia (Italy), Waseda University (Japan), Technical University Delft (Netherlands), Victoria Technical University and the University of New South Wales (Australia). He was the Associate Chair (EE) of the Department of Electrical Engineering and Computer Science at UCBerkeley from 1999 to 2002, and is currently the Scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the GigaScale Systems Research Center (GSRC). He has authored or co-authored a wide range of papers in the area of signal processing and design automation. His current research interests include the conception and implementation of next-generation integrated wireless systems. This includes the analysis and optimization of communication algorithms and networking protocols, the study of low-energy implementation architectures and circuits, and the supporting design automation environments. Dr. Rabaey has received numerous scientific awards, including the 1985 IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN Best Paper Award (Circuits and Systems Society), the 1989 Presidential Young Investigator award, and the 1994 Signal Processing Society Senior Award, and the 2002 ISSCC Jack Paper Award. In 1995, he became an IEEE Fellow. He is past chair of the VLSI Signal Processing Technical Committee of the Signal Processing Society and chaired the executive committee of the Design Automation Conference. He is serving on the Technical Advisory Board of a wide range of companies.