CASIS: a Very High Dynamic Range Front-End Electronics with Integrated Cyclic ADC for Calorimetry Applications

Transcription

1 CASIS: a Very High Dynamic Range FrontEnd Electronics with Integrated Cyclic ADC for Calorimetry Applications V. V. Bonvicini, Bonvicini, G. G. Orzan, Orzan, G. G. Zampa, Zampa, N. N. Zampa Zampa (INFN (INFN Trieste) Trieste) Presented Presented by by V. V. Bonvicini Bonvicini The The CASIS CASIS chip: chip: motivations, motivations, objectives objectives and and design; design; First First (preliminary) (preliminary) experimental experimental results; results; Outlook. Outlook. IEEE IEEE NSS NSS October October November November 3, 3, Honolulu Honolulu (Hawaii) (Hawaii) 10/31/2007 Valter Bonvicini IEEE NSS

2 The CASIS project CASIS (Silicon Calorimetry for Space) : INFN R&D project aimed at improving the present performance of Si W calorimeters (both detectors and frontend electronics) in view of future astroparticle physics experiments, where very high energy (up to ev) particles are to be studied. Development of integrated frontend electronics with very large dynamic range for silicon detectors in calorimeter applications Phase (CASIS1.0): frontend circuit with Range of 50 pc (~ 10 4 MIP for 380 µm thick Si detectors); Phase2 Phase (CASIS1.1): (CASIS1.2): improved Final 16channel prototype, complete including circuit all lessons with 1 ENC < 6000 e Cdet = 300 pf; learned ADC/channel. from CASIS1.0 (especially concerning the ADC) Power consumption < 3 mw/channel. Perform a feasibility test of integration of one ADC/channel Design approach: Frontend section: a double gain (double range) CSA with automatic gain control followed by a Correlated Double Sampling (CDS) filter. ADC: Cyclic ADC with 12 bits of resolution, clock up to a few MHz. Technology: 0.35 um C35B4 CMOS from AMS (4M/2P, 3.3V supply). 10/31/2007 Valter Bonvicini IEEE NSS

3 From CASIS1.0 to CASIS1.1 The frontend part (CSA + CDS) in CASIS1.0 fulfilled all design specs (dynamic range, noise, linearity and power consumption), therefore: Only minor improvements and modifications were implemented in CASIS1.1 (mainly in the CSA feedback and feedback control networks). The ADC part in CASIS1.0 have shown some (expected) problems, mainly due to the effect of random device mismatch on the Diff. Op. Amps: Percentage of working channels ~ 50%; Anomalous power consumption in the nonworking channels (~ 10 times) Therefore: We revised the design of the Diff. Op. Amps of the ADC, implementing 9 ADC channels designed around 2 alternative solutions. 10/31/2007 Valter Bonvicini IEEE NSS

4 CASIS1.1: CSA and Correlated Double Sampling block scheme 10/31/2007 Valter Bonvicini IEEE NSS

5 CASIS1.1: Cyclic ADC block scheme CLK2N SUBNEG Vref+ Vom CLK4 CLK3N SUBPOS Vref CLK3 Vinput SAMPLE ADCON 0.5 pf 0.25 pf + CYCLE ADCON Vim Vcm CLK2 CLK2 0.5 pf 0.5 pf + CLK1 ADCON Vcm CYCLE 0.5 pf Vip CLK2 0.5 pf Vcm 0.25 pf 0.5 pf CYCLE ADCON CLK2 CLK1 ADCON Vop CLK4 CLK3N Vcm SUBPOS Vref+ CLK3 Vcm CLK2N SUBNEG Vref CLK3 CLK3 SUBPOS SUBPOS Q Q CLK2 30 ff CLK3 CLK3 SUBNEG SUBNEG 30 ff Q Q Vcm 10/31/2007 Valter Bonvicini IEEE NSS CLK2 + CLK3 Q CLR Q CLK3

6 Diff. Op. Amp. Solution 1 (baseline) Input diff. amp. Bias Output buffer CMFB amplifier 10/31/2007 Valter Bonvicini IEEE NSS

7 Diff. Op. Amp. Solution 2 (backup) 10/31/2007 Valter Bonvicini IEEE NSS

8 Micrograph of a die (chip CASIS1.1) 3 Type F ADC 3 Type N ADC 3.1 mm Buffer ch. 1 CDS ch. 1 ADC control CSA bias 3 Type O ADC The CASIS chip CSA was ch. designed 1 during 2006/2007 and produced within an Europractice MPW run started in April /31/2007 Valter Bonvicini IEEE NSS mm

9 CASIS1.1: Frontend results Linearity_HighGain Linearity_LowGain y = x y = x Output voltage, m V %Error Nonlinearity_HighGain Input charge, MIP Input charge, MIP Output voltage, m V % E rror Nonlinearity_LowGain Input charge, MIP Input charge, fc Dynamic ranges : 560 MIP for high gain, and MIP for low gain (or ~ 52 pc) Maximum deviation from linear fit : < 0.3% for high gain, and 0.6% for low gain Power consumption: 2.8 mw/channel 10/31/2007 Valter Bonvicini IEEE NSS

10 CASIS1.1: Frontend results ENC, e rm s Measured noise y = x ENC Linear (ENC) Cd, pf ENC@0 pf = 2280 e (~12.9 SNR for 1 MIP) rms ENC@200 pf = 3800 e rms (~7.76 SNR for 1 MIP) ENC@300 pf = 4560 e rms (~6.5 SNR for 1 MIP) 10/31/2007 Valter Bonvicini IEEE NSS

11 Signal ped. [ADC ch.] Linearity (FE + int. ADCs) Chip Input 2500charge [MIP] All ADC channels work! (19 chips fast tested, i.e. 171 ADC channels); First, preliminary indications are consistent with 12bit resolution; Complete and detailed measurements are under way to exactly determine the ADC performance. ADC channels 0 CASIS1.1: ADC results Ch2ADC1 Ch2ADC2 Ch2ADC3 Ch2ADC4 Ch2ADC5 Ch2ADC6 Linearity (FE + int. ADCs), Chip1 Ch2ADC7 Ch2ADC8 Ch2ADC Input 120 charge, MIP ADC channels Preliminary! 10/31/2007 Valter Bonvicini IEEE NSS ADC2 ADC3 ADC4 ADC5 Chip1_ADCtest ADC6 ADC7 ADC8 ADC9 ADC Input voltage, mv ADCOnd ADCO1 ADCO2 ADCF1 ADCF2 ADCFnd ADCN1 ADCN2 ADCNnd

12 Summary and Outlook The 2 nd prototype of a VLSI frontend chip (CASIS1.1) intended for the readout of silicon calorimeters has been designed, produced and tested in the framework of the INFN R&D experiment CASIS2. The chip features 2 channels including a doublerange CSA (with gains 2.94 mv/mip and 146 µv/mip) with realtime control feedback network, a CDS filter and an output buffer, and 9 channels with fully differential cyclic ADCs (2 different designs for the Diff. Op. Amps). The frontend part (CSA + CDS) fulfils all design specs. In particular, a dynamic range of 52.2 pc (in LowGain mode), an ENC = 2280 e e /pf, a very good linearity and a power consumption of 2.8 mw/ch have been achieved. Tests on the ADC part are under way, from the results available at this time we can conclude that: a) 100% of the channels convert correctly (171 ADC channels fasttested at 250 khz and 1 MHz) and display the expected power consumption we solved the random device mismatch problems; b) Preliminary indications show that the ADC resolution is close to the design one, but we need to complete the measurements to fully determine all ADC performance (missing codes, linearity ). On the basis of the results on this prototype, we are confident to be able to design the final chip version (CASIS1.2) with 16 complete channels in This work has been completely supported by the Istituto Nazionale di Fisica Nucleare (INFN) 10/31/2007 Valter Bonvicini IEEE NSS

13 Backup slides 10/31/2007 Valter Bonvicini IEEE NSS

14 Monte Carlo simulation of the modified Diff. Op. Amp. (500 runs) Counts Power consumption [mw] DC gain [db] Counts Counts Counts Phase margin [deg] Unitygain frequency [MHz] The corrections made on the input differential amplifier solve the mismatch problem 10/31/2007 Valter Bonvicini IEEE NSS

15 CASIS: results of the frontend section 400 MIP 300 MIP 200 MIP 100 MIP From the bottom: 7000 MIP 8000 MIP 9000 MIP MIP Oscilloscope pictures of the output of the CDS. Input charge injected by a pulse generator through an external capacitor. 10/31/2007 Valter Bonvicini IEEE NSS

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