Ansoft Designer with Nexxim. Statistical Eye Capabilities

Transcription

1 Ansoft Designer with Nexxim Statistical Eye Capabilities

2 Problem Statement Load Generic 0.25um M odels Buffer PCIE Connector BYPASS Planar EM S S S TRL TRL TRL TRL TRL TRL Programmable W-Element SI Wave + Port1 Port2 Complex system analysis Specification BER analysis Buffer design Integration of modeling types Equalization schemes Frequency & Time domain mapping 0 Low BER Necessitates simulation with LARGE bit bit count

3 Generic Solutions Multiple tools from different EDA vendors Spice 1. Many Spice solutions have difficulty handling frequency to time domain transforms Three-dimensional EM solutions 2. Most time domain simulation tools require s-parameter outputs (see issue 1) Statistical analysis 3. Most don t support mixed elements from within Spice (i.e. w- elements, s-parameters, transistor and behavioral buffers) Speed 4. Many EDA vendors only support transient analysis Capacity 5. Many solutions support up to a maximum of around ports usually requiring s-parameters (see issue 1) 6. Most only allow s-parameter referencing to 50 ohms. This is a problem for SSO/SSN simulations that need power planes referenced to lower impedances, ~1 ohm, for increased numerical accuracy (see issue 1) Interoperability of EDA tools!

4 Ansoft Designer with Nexxim Overview Multiple Analysis domains Time and Frequency consistency High speed & capacity Transistor-level accuracy Native support HSpice netlists & design kits Spectre/SpectreRF netlists & design kits IBIS v4.0 & Verilog-A Superior S-Parameter Handling State-Space and Convolution Benchmarked 660 ports! Mixed port impedances Flexibility in design flow and integration Ansoft Designer Co-simulation with Ansoft EM Cadence ADE Multiple output/viewing formats Applications in Signal Integrity, Mixed-Signal and Analog Design

5 Ansoft Designer with Nexxim Integrated Circuit Simulation EM Tools HFSS SIWave Q3D 2D Extr PlanarEM Time Freq Cadence ADE Ansoft Designer Nexxim System Mixed Signal 3 rd Party Tools SimuLink Matlab Analog Digital Hspice Spectre Verilog A

6 Latest Developments Nexxim circuit simulation enhancements Passivity and State-space Algorithms Speed and accuracy Design flow VerifEye TM QuickEye TM Post-processing

7 High Speed Channel Analysis Load Generic 0.25um Models Buffer PCIE Connector BYPASS Planar EM S S S TRL TRL TRL TRL TRL TRL Programmable W-Element SI Wave + Port1 Port2 0 Circuit simulation challenges: Reliable Bit Error Rate (BER) Prediction at FAST simulation speeds

8 Statistical Eye Overview Transient Eye requires 1/BER time 1x10 15 bits not uncommon Long transient simulations Approximations are needed Statistics VerifEye TM "Rise time" calculation for BER QuickEye TM Step" and ISI characteristic calculate BER

9 Statistical Eye Analysis (lower accuracy, highest speed) VerifEye TM Algorithm: Run transient Generates step response Detect the delay Impose the step response On UI grid Calculate probability of error (BER) For a single cell in the grid Based on statistical assumptions Generate Eye contour Assumes LTI

10 Advantages: SPEED! Mixed model channel W-elements S-parameters Spice Visualizes worst eye TX jitter TX DCD VerifEye TM

11 Algorithm: Run transient Generates step response Convolve QuickEye TM Bridge between Statistical Eye & transient (medium accuracy, medium speed) Input bit-stream with step response Allows for very long input bit patterns Provides fast time and eye plots Assumes LTI system V(Port1) [mv] XY Plot Time [ns] Curve Info Nexxim1 V(Port1) Transient

12 QuickEye TM Advantages: SPEED! View full transient output Detect Worst Case Packet Visualize eye mask violations Determine Jitter through Histogram of threshold crossings

13 View Eye Diagrams at Various Points SI Chane XY Plot SI Chane XY Plot 1 SI Chane XY Plot 1 Curve Info aeyeprobe856 QuickEyeAnalysis : QuickEyeAnalysis SI Chane XY Plot 1 Curve Info aeyeprobe862 QuickEyeAnalysis 1.50 Curve Info aeyeprobe859 QuickEyeAnalysis aeyeprobe859 [V] aeyeprobe862 [V] Curve Info aeyeprobe846 QuickEyeAnalysis aeyeprobe856 [V] aeyeprobe846 [V] aeyeprobe856 [V] Time [ps] Time [us] Time [ps] Time [us] Time [ps] - - SI Chane XY Plot 1 SI Chane XY Plot 1 Time [us] Time [us] aeyeprobe859 [V] Time [ps] Time [us] Curve Info aeyeprobe865 QuickEyeAnalysis SI Chane XY Plot Curve Info aeyeprobe849 QuickEyeAnalysis 40 Time [ps] Time [us] 70 - Curve Info aeyeprobe859 QuickEyeAnalysis North Bridge aeyeprobe859 [V] aeyeprobe849 [V] aeyeprobe849 [V] aeyeprobe846 [V] 40 Time [ps] aeyeprobe865 [V] 20 aeyeprobe865 [V] 10 aeyeprobe862 [V] 1.50 aeyeprobe859 [V] Time [ps] Time [us] Allcomponents components"active" "Active" All 80

14 Effect Of Connector XY Plot 1 SI Chane SI Chane Curve Info aeyeprobe859 QuickEyeAnalysis Time [ps] aeyeprobe859 [V] - 40 Time [ps] Time [us] ConnectorIn InCircuit Circuit Connector Time [us] 1 2 XY Plot 2 SI Chane Connector"Bypassed" "Bypassed" Connector Curve Info aeyeprobe859 QuickEyeAnalysis aeyeprobe859 [V] aeyeprobe859 [V] XY Plot 1 Curve Info aeyeprobe859 QuickEyeAnalysis aeyeprobe859 [V] aeyeprobe859 [V] Allother other components components"active" "Active" All Time [us]

15 High Speed Channel Example Simulation time Comparison Transient Transient QuickEye QuickEye VerifEye VerifEye

16 Transient Results Behavioral 4 Tap Tap CTLE Buffer 98,304 Bits 1, Seconds ~ minutes

17 QuickEye TM Without FFE Results Behavioral 4 Tap Tap CTLE Buffer 98,304 Bits Seconds 130x Faster!

18 QuickEye TM With 4 Tap FFE Results 98,304 Bits Seconds

19 VerifEye TM Results seconds,

20 VerifEye TM 3D plot

21 Equalization Effects DC=1 0 V425 fivetap_fir FILTER LEVEL_SHIFTER CTLE Vbias + CML - Differential_SL_100ohms_tand INVERTER PNUM=1 RZ=50ohm IZ=0ohm 0 0 PNUM=2 RZ=50ohm IZ=0ohm Comparison of of circuit circuit with with and and without without feed feed forward forward equalization for for VerifEye VerifEyeand and QuickEye

22 VerifEye TM No No equalization Equalization VerifEye_Contour PCIe3_NoFFE aeyeprobe45 00e e e e e e e e e e VerifEye_Contour PCIe3 aeyeprobe45 00e e e e e e e e e e Amplitude Amplitude UnitInterval UnitInterval

23 QuickEye TM No No equalization Equalization

24 VerifEye TM Bathtub No No equalization Equalization E+000 E-001 E-002 VerifEye_BER PCIe3_NoFFE Curve Inf o aeyeprobe458 VerifEyeAnalysis E+000 E-001 E-002 E-003 VerifEye_BER Curve Info aeyeprobe458 VerifEyeAnalysis PCIe3 E-003 E-004 E-004 E-005 E-005 E-006 aeyeprobe458 E-006 E-007 E-008 aeyeprobe458 E-007 E-008 E-009 E-009 E-010 E-010 E-011 E-011 E-012 E-012 E-013 E-013 E-014 E UnitInterval E-015 E UnitInterval

25 Back Up

26 S Parameter Modeling Methodologies State-space mapping with rational functions Strengths Guaranteed causality Optional passivity enforcement Very good interpolation & extrapolation over broad F range Efficient simulation in the time domain Model is saved within Nexxim, no need to resolve Limitations Not well suited to long transmission time delays Convolution Strengths Accurately models transmission time delay Multiple options for DC Extrapolation and Filtering Limitations Needs continuous f-domain data, from DC to highest freq. Simulation run-time grows quadratically with # of time steps