Micromachined Silicon Optical Bench for the Low Cost Optical Module

Transcription

1 Micromachined Silicon Optical Bench for the Low Cost Optical Module Ki-Chang Song* a, Jong-Uk Bu a, Young-Sam Jeon a, Chil-Keun Park a, Jae-Hoon Jeong a Han-Joon Koh b, Min-Ho Choi b LG Corporate Institute of Technology 16 Woomyeon-Dong, Seocho-Gu, Seoul , Korea b Optoelectronic Device Lab., LG Cable Ltd. 555 Hogye-Dong, Dongan-Gu, Anyang-Shi, Kyungki-Do 431-8, Korea Abstract A novel self-aligning silicon optical bench for fully passive alignment of optical components and its fabrication method are presented. Key technologies developed in this work are multi-step silicon anisotropic etching for manufacturing SiOB, photolithography on three-dimensional surface, precise size control of optical active chip, and flux- and pressure-free die bonding technology. The measured size tolerance of silicon grooves for the active chip and the fiber reveals less than ±.5µm. The photolithography process on three-dimensional surface of each site is investigated to get the patterns for deposition of electrodes, mirror, and solders, respectively. The precisely cleaved laser diode chip is obtained by V-groove etching to define the cleaving lane. This technique allows the chip to be defined with a dimensional accuracy of ±.5µm. In addition, the pressure-free bonding technique using the electroplated Au-Sn solder makes it possible to reduce the production cost. The fabricated SiOB does not need any pre-alignment process of the optical chip and fiber to desired position such as index alignment method. On the basis of these technologies, it is shown that the fully passive alignment of optical component packaging is successfully preformed. The measured results reveal that the coupling efficiency of the laser diode module was achieved better than 8% and the responsivity of the photo diode module was better than.85 A/W. Keywords: silicon optical bench, SiOB, passive alignment, coupling efficiency, anisotropic etching, and flux-, pressure- free bonding 1. Introduction Recently, there has been considerable interest in manufacturing the low cost optical module. Since packaging steps of individual optoelectronic components dominate the product cost of photonic devices, the improvement of optical alignment procedure between active devices and optical fibers has been a crucial issue to achieve low cost and compact size optical module, while maintaining the desired functionality and performance. So far, active investigations and developments based on passive aligning technology have been carried out to obtain a low cost mass production 1,2. The basic consideration of the passive alignment techniques was flip-chip bonding surface mount technology using the surface tension of molten solder 3,4, index alignment of optical devices with the marker 5 and mechanical contact alignment on the precisely fabricated planar light waveguide 6,7 or micromachined silicon platform 8~1. For the index alignment method, it needs high-resolution solders and markers on the optical parts for a marker alignment 11,12, while the formation of solder bumps and the precise placing of the chip onto the solder bump site are required for the solder bump self-alignment methods 13,14. These conventional methods are in need of a precise prealigning of the optical chip before fixing on silicon optical bench (SiOB) and require an auxiliary part for alignment. These are weak points of manufacturing process for the low cost optical module using existing passive alignment technology. On the other hand, the passive alignment of optoelectronic components using micromachined SiOB for hybrid integration of optoelectronic components has the potential for low cost implementation if the dimensional accuracy of the SiOB and the chip is to be controlled less than.5µm. In this paper, we proposed the novel self-aligning SiOB for a fully passive alignment and its fabrication method. In addition, the passive alignment technology of optical components using micromachined SiOB was demonstrated through the development of required key technologies, multi-step silicon anisotropic etching for manufacturing optical bench, photolithography on three dimensional surface, precise size control for optical active chip and flux- and pressure-free die bonding technology. In addition, through the fabrication of laser diode and photo diode modules, the *Correspondence: skc@lgcit.com; Telephone: ; Fax:

2 self-positioning effect of the wet etched trapezoidal silicon groove which guides the laser diode and photo diode chips to its own positions will be presented and discussed. This conceptual technology for optical component packaging offers important advantages over other passive alignment technologies of a real align free passive alignment and a realization of simple pick and place function without high resolution flip chip bonder. 2. Experiment 5 inch (1) p-type silicon wafers were used as starting materials to fabricate the SiOB. The silicon wafer was anisotropically etched in 2vol% IPA added 2wt% ~ 4wt% KOH solution at 7 ~ 9. The etched dimension was measured by three-dimensional optical measuring equipment with.1µm resolution and step profiler (DEKTAK II Sloan) was used for the depth measurement. In order to estimate the surface roughness of the etched planes and the etching selectivity of (1) plane to (111) plane, atomic force microscopy (AFM) and scanning electron microscopy (SEM) were used. The laser diode used in this study were InP strained multi-quantum well structure grown by MOCVD which has 13 nm in wavelength. Precisely size controlled laser diode chip was fabricated by wet etching process after formation of photolithographically defined 1µm-wide window using SiNx passivation layer. It was etched away showing a necktie shape grooves along the [11] direction. Electroplated Au-Sn eutectic alloy was adopted as a solder material for bonding the active chip onto the optical bench. The composition and melting temperature of solder were analyzed by energy dispersive X-ray spectroscopy (EDX) and differential thermal analysis (DTA). Solder surface was treated with Ar and O 2 mixed gas plasma to remove the oxide and carbon contamination layer and auger electron spectroscopy (AES) was used to analyze the chemical state of the solder surface. 3.1 Fabrication of SiOB 3. Results and discussion It is widely used for bulk micromachining of single crystal to fabricate the packaging platform for optical device. The structural nature of silicon makes it possible to fabricate the precise three-dimensional shape. In general, silicon has a high etching selectivity of (1) to (111) plane in anisotropic wet etching, and it offers a fascinate advantage to apply silicon to the optoelectronic device packaging. In order to use the micromachined SiOB in optical component packaging, the dimensional accuracy is extremely important and the size of etched site is to be controlled with an accuracy of less than.5µm. Therefore, it is necessary to obtain preliminary data regarding the KOH etching characteristics such as surface roughness of (1) and (111), alignment with <11> on (1) surface, and etching selectivity of (1) to (111). Fig. 1 shows the etching properties with KOH concentration and solution temperature. As shown in results, we achieved the good etching properties that the surface roughness of each plane is less than 5nm analyzed by AFM and the selectivity of (1) to (111) is higher than 7 at etching condition of 25wt.% KOH, 8 and IPA 25vol.%. Fig. 2 (a) and show the smooth surface of (1) and (111) and Fig. 2 (c) reveals the etching defect on (111) surface when the etching condition was not optimized. Additionally, pattern alignment with <11> is an important factor to obtain the smooth (111) surface without significant defects such as micro-facet or micro-step. Even though primary flat of asreceived silicon wafer is cut with <11> direction, most primary flats are a little tilted from inborn <11> direction. Therefore, it is important to find the exact <11> direction before photolithography process for defining the size of the terraces. By using pre-etching of fan-shaped patterns that arranged with.1 o spacing, we aligned a pattern to the exact <11> direction on wafer surface within direction accuracy of ±.2 o. Fig. 2 (d) shows the (111) surface having micro-facet due to misalignment with exact <11> and this kind of (111) surface on SiOB causes the misalignment of optical chips to fibers. Another important factor of wet etching process for manufacturing the SiOB is to compensate a convex corner. Since the convex corners of pattern are attacked during the KOH etching process, convex corner need a compensation patterns to obtain desired three-dimensional structures. To optimize the compensation pattern and to determine the compensation pattern shape and size, anisotropic etch processes were simulated using AnisE module (IntelliSense Co.) in the etching condition of 2wt.% ~ 45wt.% KOH solution at 7. Fig. 3 shows pattern shapes of simulation and their result. As shown in Fig. 3, branch type compensation patterns (#5, 6) were proved to be the most effective shapes to protect a convex corner. It is clearly explained in Fig. 4 the corner compensation effect at the laser diode site of SiOB, (a) is the wet etched convex corner pattern without compensation pattern and shows the compensated convex corner when the etch depth was about 1µm.

3 Selectivity of (1) to (111) Optimal condition; KOH 2wt.%~3wt.% IPA 25vol.% temp. 7 o C~8 o C Roughness of (111) plane (A ) Fig. 1. The relationship between etching the selectivity of (1) to (111) and the roughness of (111) plane according to etching conditions. (111) (111) (1) (a) (111) (111) micro-step (c) Fig. 2. SEM photographs showing the wet etched silicon surface of (1) and (111) plane. (d) Schematic views of SiOBs are shown in Fig. 5. Fig. 6 represents SEM pictures of the fabricated SiOBs for the photo diode module and the laser diode module, respectively. In both cases, only one wet etching mask is used during three times etching processes to provides the good advantage to eliminate a pattern displacement error that might happen between each etching step. The coupling efficiency of assembled module strongly depends on the dimensional accuracy of the SiOB because the size deviation of the SiOB from designed dimension causes coupling loss. It is proven that the dimensional accuracy is higher than ±.5µm and the uniformity is less than.5% at 4 inch actual area in 5 inch wafer. The dimension of laser diode terrace for laser diode module is a width of 298µm, a length of 3µm and a depth of 25µm. One of the most difficult processing issues in manufacturing the SiOB is the photolithography on three-dimensional surface. This process is indispensable to get the patterns for the electrodes, the mirror, and the solder on SiOB. Several

4 etch depth (2 %KOH, 7 o C) compensation pattern etch depth (3 %KOH, 7 o C) compensation pattern (4 %KOH, 7 o C) (45 %KOH, 7 o C) etch depth etch depth µm compensation pattern compensation pattern Fig. 3. Compensation patterns in silicon wet etch simulation and the etch depth when compensation patterns are disappeared at each etching condition. Etch depth: 1µm Etch depth: 25µm Etch depth: 25µm (a) Fig. 4. Photographs showing the etched pattern at the convex corner (a) without and with compensation pattern. methods for the conformal coating of photoresist on three-dimensional surface such as electroplating of photoresist or spray coating, have been reported 15, 16, but they require additional process or an equipment. In order to solve this problem, a planarization process on three-dimensional surface by using thick photoresist was developed. High viscosity phtoresists such as AZ-433 and AZ-456 were used to achive a semi-planarization effect with low speed spin coating and reflow step was followed. Fig. 7(a) shows the photolithography pattern on three-dimensional surface using this technique and Fig. 7 reveals the electrode pattern of Ti/Pt/Au (3A/3A/25A) formed by electron beam evaporation and lift-off process using developed photolithography process. 3.2 Precise cleaving of laser diode The fully passive alignment of optical module in this work premises that it can be possible to get the precise size control of optical chip with a dimensional tolerance of less than ±.5µm. Because the dimension error of the optical chip and the SiOB causes to deteriorate a coupling efficiency of optical components, the size control of those is extremely important. On the other hand, since the dimensional tolerance of photo diode is allowed to be a few µm, it is not so critical as that of laser diode and optical bench. It is enough to cleave the photo diode with conventional cleaving method. The laser diode used in this study was 13 nm wavelength InP strained multi-quantum well structure grown by MOCVD. Precisely size controlled laser diode chips were fabricated by wet etching using photolithographically defined

5 (1) LD mpd (1) PD optical fiber optical fiber Receiver PD site monitor PD Site Laser diode site Optical fiber site Optical fiber site Au-Sn Solder (a) Silicon optical bench for self-aligning Silicon optical bench for self-aligning Fig.5. Schematic views of (a) the laser diode module and the photo diode module. (a) Fig. 6. SEM photographs showing the multi-step etched silicon optical bench for (a) the laser diode module and the photo diode module. 1µm window of SiNx. As shown in Fig. 8, it was etched with a necktie shape grooves for cleaving along the [11], and with V-grooves for cleaving along the [1-1] directions. Top contact layer of InGaAs and InP cladding layer were etched by H 2 SO 4 based etchant and a mixed solution of HCl and CH 3 COOH 17,18, respectively. In this wet etching process, the cleaving grooves were etched all along the [11] direction, while the edge parts were etched along the [1-1] direction. The etched wafers were cleaved to chip bars perpendicular to the active stripe of laser diode. After deposition of SiO 2 and TiO 2 on the facet for anti-reflection of light, the chip bar was cleaved parallel to the active stripe to be the precise dimension. Fig. 9 is SEM ptotograph showing necktie shape groove of precisely wet etched laser diode chip. Using this process, the etching of 2µm width and 5µm depth V-groove with nearly vertical sidewall has been realized. The dimension of cleaved chips was investigated by three-dimensional optical measuring equipment, and the chip size was measured as the width of 298µm and the length of 3µm with the size deviation of less than ±.5µm.

6 (a) Fig. 7. Photographs showing (a) the photolithography pattern and the metal pattern on three-dimensional surface. necktie shape groove [11] [1-1] V-groove cleaving plane Fig. 8. Schematic diagram of the precise chip size control. Fig. 9. SEM photograph showing the necktie shape groove. 3.3 Principle of passive alignment The mechanism of passive alignment of optoelectronic components on etched silicon groove is shown in Fig. 1. The precisely cleaved laser diode is placed exactly on the desired position because the outside dimension of laser diode and inside part of trapezoidal silicon groove were controlled with the same size within the accuracy of.5 µm. The sidewall of wet etched silicon groove has the angle of o, which is very helpful to self-aligning of optical chip to its position by pick and place. In fig. 1, it is schematically showed that the laser diode chip moves to its site along the inclined sidewall of micromachined optical bench and is fastened with surface tension of molten solder. Fig. 11 shows the cross-sectional view of self-aligned laser diode on the precisely machined laser diode terrace. The laser diode was positioned exactly on the desired position of silicon groove. The two joining points between the edge of the laser diode and the plane of the silicon sidewall have an exact contact. From this result, it is clearly proven that the aligning accuracy of less than ±.5µm can be reproducibly achieved in the lateral direction, and that the coupling between the laser diodes and optical fibers is accomplished within the tolerance of 1 µm. 3.4 Chip bonding and solder formation In order to bond the chip onto the SiOB, we have approached with flux- and pressure-free bonding technique. If any pressure is applied to the optical chips for bonding, it may be difficult to obtain the aligning accuracy in multi-chip bonding on the same optical bench and the mass productivity will be degraded. Several works have been reported on the flux- and pressure- free two-step chip bonding by applying primary thermo-compression bonding of several chips on

7 Si groove for self-aligning size controlled laser diode chip Au-Sn solder (1) Si groove ( Au-Sn LD Fig. 1. Schematic views of the self-alignment mechanism. Laser Silicon optical bench Au-Sn solder Fig. 11. Photograph showing the cross sectional view of the self-aligned laser diode chip on the silicon optical bench. the prepared silicon platform and later full die bonding together through elevating the temperature above the melting point of used solder 19. Most of previous methods require external force or considerable process time to bond the optoelectronic devices, which might inflict a mechanical damage from the applied ultrasonic bonding force. In the semiconductor chip packaging, various solder materials are used. However, in case of optoelectronic device packaging, 8wt%Au-2wt%Sn eutectic material is being widely used due to its thermal stability. Several studies have been reported on the deposition of Au-Sn solder by the alternation of Au and Sn layer using electron-beam evaporation, thermal evaporation of Au-Sn composite film and the alternation of Au and Sn layer by electroplating 2, 21. In the case of the electron-beam evaporated Au-Sn solder, it is known that its composition is determined by thickness ratio of each layer and its quality is relatively good enough. However, in this work, it is found that photoresist layer is exposed thermal damage during the thick Au-Sn layer is deposited on the SiOB which has a thick photoresist pattern of 25µm ~ 4µm in depth. Therefore, the electroplating process for the Au-Sn solder was tried. The thickness and composition uniformity of the electroplated Au-Sn in 4 inch working area are within ± 5% and ±.8%, respectively. Its chemical composition analyzed by EDX is 78.5wt%Au-21.5wt%Sn, and its melting point measured by DTA is in the range of 28 o C to 288 o C. As shown in Fig. 12, the AES depth prfile of the as-electroplated solder surface shows that solder layer has approximately 2 Å ~3 Å-thick oxide film. By plasma treating in Ar+O 2 gas after electroplating, it is effectively removed the oxide film less than 1 Å. It is realized that the flux- and pressure- free chip bonding using electroplated solder of 2µm is successfully carried out by simply heating up optical components mounted on SiOB. Although there was no significant difference of bonding state between the as-electroplated solder and the Ar+O 2 plasma treated solder, it was hard to conclude the 2Å~3Å oxide layer of solder surface do not affect the bonding strength. Through the longterm stability study of the modules, it is being examined and will be reported later. The chip bonding was carried out in a chamber at 295 o C after evacuating chamber to 1-4 Torr and refilling N 2 +1%H 2 gas to avoid from the surface oxidation. No pressure was applied on the optical components during soldering process, as mentioned above. 3.5 Characterization To estimate the coupling efficiency of passive alignment using micromachined SiOB, the laser diode and photo diode modules were assembled and measured. The coupling efficiency of laser diode module was revealed more than 8%, which is satisfied required specification at the directly butt-coupled laser diode. The output power was 1 dbm at 2 ma. It is expected to be greatly improved using a tapered optical fiber or a spot size converted laser. According to these results, the overall alignment accuracy is estimated to be less than ±3µm. The responsivity of the receiver module was estimated to be better than.85 A/W and the dark current was less than 1 na. Furthermore, the capacitance of assembled SiOB was.7 pf at a bias voltage of 5 V.

8 Sputtering rate: 1A/min Sputtering rate: 1A/min Fig. 12. Comparison of AES depth profile of (a) as-electroplated and Ar+O 2 plasma treated Au-Sn solder surface. 4. Conclusion The premise for a fully passive alignment of optical module is the precise size control of the optical chip and the SiOB with dimensional tolerance of less than ±.5µm. We have successfully demonstrated the micromachined SiOBs, through development of several key technologies such as multi-step anisotropic wet etching without pattern displacement error between each step, compensation pattern design for protection of convex corner, phtolithography on three dimensional surface, and electroplating of Au-Sn eutectic solder. It is realized that a fully passive alignment technology presented in this work does not need any auxiliary processes such as pre-positioning to alignment marker or use of high accuracy bonder. A coupling efficiency of the laser diode module was achieved better than 8% between the laser diode and the flat end fiber, and its output power was -1dBm. The responsivity of the photo diode module was estimated to be better than.85 A/W. This conceptual technology for optical component packaging offers important advantages over other passive alignment technologies of a real align free passive alignment and a realization of simple pick and place function without high resolution flip chip bonder. Acknowledgments The authors would like to thank the assistance of Hong-Jun Chun at Optoelectronic Device Lab., LG Cable Ltd. in the assembly and estimation of the optical module. This work is partially sponsored by the Ministry of Commerce, Industry and Energy, and Ministry of Science and Technology, Republic of Korea, under G7 Advanced Technology Development Program. References [1] H. L. Althaus, W. Gramann, and K. Panzer, Micro systems and wafer processes for volume production of highly reliable fiber optic components for telecom- and datacom-application, Proc. ECTC 97, pp [2] J. V. Gates, G. Henein, J. Shmulovich, D. J. Muehlner, W. M. MacDonald, and R. E. Scotti, Uncooled laser packaging based on silicon optical bench technology, SPIE 96, vol. 261, pp [3] L. F. Miller, Controlled collapse reflow chip joining, IBM J. of Res. Develop., pp , [4] M. J. Wale, and C. Edge, Self-aligned flip-chip assembly of photonic devices with electrical and optical connections, IEEE Trans. Comp. Hybrids, Manufact. Technol., vol. 13, pp , 199. [5] K. Kurata, K. Yamauchi, A. Kawatani, H. Tanaka, H. Honmou, and S. Ishikawa, A surface mount type single-mode laser module using passive alignment, Proc. ECTC 95, pp [6] T. Hayashi, An innovative bonding technique for optical chips using solder bumps that eliminate chip positioning adjustments, IEEE Trans. Comp. Hybrids, Manufact. Technol., vol. 15, pp , [7] Y. Yamada, S. Suzuki, K. Moriwaki, Y. Hibino, Y. Tomori, Y. Akatsu, Y. Nakasuga, T. Hashimoto, H. Terui, M. Yanagisawa, Y. Inoue, Y. Akahori, and R. Nagase, Application of planar lightwave circuit platform to hybrid integrated optical WDM transmitter/receiver module, Electron. Lett., vol. 31, pp , 1995.

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