User s Guide to. Centre for Materials for Electronics Technology Panchawati, Off Pashan Road, Pune September Version 2.

Transcription

1 User s Guide to Centre for Materials for Electronics Technology Panchawati, Off Pashan Road, Pune September 2013 Version 2.1

2 Contents 1 Designing of LTCC Structures and Design Rules Guidelines to Designers Design Rules Approaching C-MET for Development and fabrication User Entry User Entry C-MET Process Leading to Fabrication Annexure I 951 Materials List available at C-MET... 23

3 1. Designing of LTCC Structures and Design Rules Design Rules are a necessary feature of LTCC structure while realizing any design. For any fabrication laboratory, the capabilities and capacities of fabrication process define the design rules. Here in C-MET, a set of Design Rules that are followed are principally dependant on installed equipment and chosen materials. Apart from this, the experience gained during the fabrication of various packages over the years has also played a crucial role in compiling the set of design rules. These design rules are closely comparable to various private manufacturers such as, CTS Microelectronics, VTT Electronics, Kyocera, Sip Technology, Advanced Ceramic Corporation, DuPont Microcircuit Materials, VIA Electronics, SEI Electronics, Anaren and HIRAI etc. 1.1 Guidelines to Designers There are few considerations which the designer has to look at before actual drafting of the design or just before handing it over to C-MET. Following is a list of such considerations. The design should be prepared in 1:1 scale. All design layers shall include a substrate outline (line width 100μm). All designs shall have a common origin. Designing & Measuring unit system should be Metric. Preferably, the Artwork should be designed with Fired dimensions i.e. final required dimensions. The artwork then will be scaled-up, considering the shrinkage [approximately 12.9% in X & Y] during Firing process. Alternatively, the artwork can be designed directly with un-fired dimensions. Layers should be numbered from bottom to top i.e. Bottom layer will be Layer 1. Here, Layer means the ceramic dielectric separating the conductors. All the files should be Autodesk AutoCAD 2006 compatible [ DWG or DXF ]. If user is using any other EDA tool for designing and then exporting it the specified format then he must ensure that all patterns such as line width (rectangle, square), via (circle) etc. remain as an independent entity. All designs should be preferably made with even number of layers of each thickness 1 P age

4 1.2 Design Rules The following sub-sections, A through G, provide design rules for various parameters for LTCC design. Please note that all the dimensions given in the sub-sections A to E are un-fired dimensions, whereas, from F to I, processes and hence dimensions are post-fired. A: Conductor Lines Internal Signal Line Dimensions (µm) Min. line width 100 Min. line spacing 150 Min. conductor spacing to via cover pad 150 Min. Conductor spacing to substrate edge 500 Catch Pad 2 x Via dia External co-fired Conductor Min. line width 100 Min. line spacing 100 Contact Pad 700 x 700 Post-Fire Conductor min. line width 100 line spacing 100 wire bond pads cavity edge to pad 100 pad pitch 1.5 x PAD Dimensions Conductor overlap Same as the line width Distance between the two different conductors on a same layer (edge to edge) 2 times of the line width *Note: Line ends shall have a square end Table 1.2.1: Design rules for Conductor Lines 2 P age

5 Figure 1.2.1: Depiction of conductor lines for design rule parameter definition 3 P age

6 * Note: If two different pastes (conductor) are being screen printed on the same layer (as shown in Figure 1.2.2) then try to re-route those lines by placing an additional layer and connecting them through via (as shown in Figure 1.2.3). Figure 1.2.2: Conductor overlap to be avoided Figure 1.2.3: Conductor overlap that is through via is allowed. 4 P age

7 B. Via Parameters Dimensions (µm) Typical Diameter 100 Min. via cover pad 2 via dia. Min. Pitch within same layer 3 via dia. Minimum via spacing to the designed fired substrate or cavity edge 500+ via dia. Stacking of via is acceptable through any number of layers. Yes Table 1.2.2: Design Rules for via Figure 1.2.4: Depiction of via for design rule parameter definition 5 P age

8 C. Cavity Parameter Dimensions (µm) Cavity floor thickness 750* Cavity wall 10 x tape thickness Via edge to cavity wall 2.5 via dia. Bond Shelf width 1000 Cavity wall aspect ratio 2 Cavity bottom conductor to cavity wall 500 Corner Radius 100 Die Punching can be done for Cavities of larger sizes Rectangle, Square or Allowed Shapes Circle Geometrically feasible shapes Minimum dimension 2 mm Dia or Side Distance between two cavities Min 3 mm Maximum opening allowed in 100 mm x 100 mm 60 % area (Even distribution) Note: Cavities or holes are punched in unfired state * This is the minimum thickness recommended. The required floor thickness may vary depending upon the dimensions of the cavity size above the floor Table 1.2.3: Design rules for Cavities Figure 1.2.5: Depiction of cavity for design rule parameter definition 6 P age

9 D. Resistors Distance between the edge of the Substrate and edge of the Resistor ( A, Figure 1.2.6) shall be 0.8 mm minimum Termination overlap of the resistor should ideally be 3/4 th of the width of the conductor. Resistor pattern length (without overlap) should be 6 times of the pattern width minimum. Trimming of Resistors is possible. LASER Trimming for open resistors Trimmed values = 0.5 % of original Resistance ( Original R < 10kΩ and 1 % for resistance > 10 kω) High - Voltage Trimming for buried resistors* Trimmed values = 0.5 % of original Resistance ( Original R < 10kΩ and 1 % for resistance > 10 kω) * Experimental only Figure 1.2.6: Depiction of the Resistor and Thermistor 7 P age

10 E. Ground and Power Planes The design rules for ground and power planes are as follows: Ground and power planes shall be a grid pattern of less than 50 % conductor coverage. The preferred plane uses 250μm thick lines and 550μm [edge to edge] spaces. Ground or Power plane which is printed with Post-Fired pastes may be solid. The grid pattern of planes on adjacent layers should be offset to provide a uniform substrate thickness. Solid conductor areas on the grid plane can be used locally to improve RF performance. The grid plane connection to via can be improved by using a square catch pad which shares the current flow to several grid lines. A minimum of 300μm spacing shall separate the plane pattern from any feed through via. The grid pattern should be placed parallel to the rectangular / package / circuit edge. Figure 1.2.7: Depiction of the Ground and Power Planes Signal via shall be isolated from the ground plane by minimum distance equal to ½ pad size 8 P age

11 Figure 1.2.8: Isolated Via F. Ball Grid Array (Post-fired process and dimensions) a. By Attachment of Spheres Parameter Dimensions (µm) 600 and above (in available BGA Diameter sphere sizes) Pad Dimension (Square or Circle) Side/ dia Equal to sphere dia Conductor to package edge Substrate Edge to center of the pad design rule to be followed Pad Pitch Min 2 x pad dimension Table 1.2.4: Design rules for Ball Grid Array by Attachment of Spheres b. By Stencil Printing (Semi Spherical) Parameter Dimensions (µm) BGA Diameter 200 and above Pad Dimension (Square or Round) 250 dia or side Conductor to package edge design Substrate Edge to centre of the pad rule to be followed Pad Pitch Min 2 x pad dimension Table 1.2.5: Design rules for Ball Grid Array by Stencil Printing 9 P age

12 Figure 1.2.9: Depiction of BGA design parameters G. Hermetic Sealing (Post-fired process and dimensions) For the hermetic sealing of chip components, a metal lid can be soldered using an appropriate solder preform. Seam sealing of substrates is also possible. (Only rectangular samples) The brazable conductor consists of three layers of conductor patterns; (1) Adhesion Layer (2) Barrier Layer and (3) Braze Layer The brazing conductor pattern shall be 1 mm wider than the lid flange. The adhesion printing pattern shall be at least 100μm smaller in width than the brazing conductor. [Braze conductor should not be exposed to the Adhesion layer material] Substrate overall thickness shall be 0.8 mm minimum. Conductors passing under the hermetic seal area should do so, at-least 2 tape layers below the surface. Figure 1.2.9: Cross-section of package to be sealed using KOVAR seal ring 10 P age

13 KOVAR ring cross-sectional dimensions: 0.5 mm x 0.5 mm Conductor track of width 0.75 mm on each side of the ring shall be printed H. Brazing / Soldering of KOVAR Pins & Tubes (Post-fired process and dimensions) Brazing of KOVAR pins is possible for reliable mounting of the sample Standard pins of dimensions (given below), are available with C-MET Pin Head: 0.5 mm x 0.85 mm Pin Dia: 0.45 mm Pin Length: 10 mm An array of contacts is also possible by brazing of KOVAR pins to the LTCC substrate; Figure provides a possible attachment drawing along with pitch. The best pitch possible for these pins is 2.5mm Pins with different dimensions can also be brazed as depicted in the following figure. Figure : Brazing of KOVAR pins to the LTCC substrate and standard KOVAR pin available at C-MET Brazing of KOVAR tubes is also possible as shown in the Figure Standard tube under consideration is of ID = 0.5 mm and OD = 1.5 mm flange: 3.5mm Soldering is usually performed after co-firing / post firing of conductor tracks of similar dimensions as in Figures to , using eutectic Sn-Pb solder paste or High lead solder paste (90Pb-10Sn). 11 P age

14 Figure : Array of KOVAR pins Figure : Brazing of KOVAR tube on to the LTCC substrate over embedded channel Similar to the brazing of KOVAR ring mentioned earlier, conductor track of width 0.75 mm on each side shall be printed for stronger brazing of Pins & Tubes 12 P age

15 I. Post-fired Singluation Dicing (Post-fired process and dimensions) Sometimes singulation of the samples is required due to other significant postfired processes, where Dicing can be done Considering the Dicing blade width + chipping on both the sides, cutting path of 0.4 mm shall be considered while placing the dicing marks. Please refer to the depiction below. Figure : Dicing marks and path at the corner of the sample 13 P age

16 2. Approaching C-MET for Development and Fabrication Practically, C-MET's LTCC facility can be used for any kind of LTCC application, within the limitations listed in the previous Section. For all such developmental projects, C-MET can be looked upon as a prototype fabrication foundry, implementing user's designs. It is expected that the user is clear about the development and knows exactly what is expected from the LTCC package or circuits he needs C-MET to develop. While C-MET's expertise and previous experience can be made available, if necessary, user's clarity about these aspects helps a lot in quickly concluding and finalizing the package or circuit. There are several steps in LTCC design implementation. Once the user is clear about the idea, he may design the application and engage C-MET for processes starting from Design Rule Check (DRC). Alternatively, C-MET can take up the design for the user. Thus, there are two 'entry levels' for the user for any prototype development. The following paragraphs describe the tasks to be undertaken by the user and C-MET for the two entry levels. 2.1 User Entry Level 1 The user, at entry level 1 (EL1) may come up with the circuit diagram, schematic, or an artwork and provide it to C-MET for undertaking conversion to LTCC based multilayer fabrication. For example, a circuit shown in Figure can be provided, along with the details of the external dimensions, connection requirements and pads, wires drawings etc. Overall, the following inputs are required from user at EL1 for the fabrication of LTCC packages: 1. A complete circuit design or artwork 2. Dimensions of all SMD components, Die, ASIC or any other embedded structure along with the pad/pin drawings 3. Circuits input and output connection requirement in detail and its required format, such as, kovar pins, cut via for soldering or as ball grid array. 14 P age

17 Figure 2.1.1: Example of circuit details to be provided by the user at EL1 4. Requirement of any other input and output port, such as, any air pressure inlets or microfluidic inlet / outlet 5. Any specific need of buried components, or, 6. Any kind sensor material deposition 7. Dimensions of critical components based on simulation results Through a detailed study of the user s needs C-MET prepares a concept drawing in multilayer format, such as, one shown in Figure Figure 2.1.2: Schematic of multilayer LTCC format This concept drawing is sent to the customer. The customer is expected to understand and check the multilayer circuit / package and provide a feedback, if any. The multilayer circuit concept / package design may be redesigned in case of any correction suggested by the user. Once the concept is finalized, a detailed design of the circuit is undertaken as per the design rule guidelines. The design is again cross-checked with the user, and the fabrication process begins after user's approval. 15 P age

18 2.2 User Entry Level 2 The user can engage C-MET at another level; the entry level 2 (EL2). Here, the user is expected to have completed the design of the circuit. The user is expected to be in a position to provide layer-wise drawings of the package / circuit, as well as the assembly drawing of the layers in a blown-out form. A 3D picture of the assembly may also help. An example of a layer design and isometric view the package is shown in Figure An example of the blown-out layer-wise 3D picture is shown in Figure P age

19 1.6 mm via for air inlet 2.8 mm via for air outlet Figure 2.2.1: Single layer and Isometric view of 3D package Figure 2.2.2: Blown-out 3D view of separated layers seen from two sides 17 P age

20 Once received, C-MET checks the design for its compatibility with the Design Rules (DRC). This DRC (Design Rule Check) will include checking of via dimesnisons, conductor line width, line width spacing, substrate edge to via, line width distance, cavity to via or conductor line with etc. Any design rule violation is raised with the user and the necessary changes in the design are requested. After receiving the corrected version of the drawing C-MET revisits those corrections and the process of consultation continues until an acceptable design is evolved. The design is then taken up for further processes leading to fabrication. These processes are described in the following Section. 2.3 C-MET Processes Leading to Fabrication C-MET's fabrication processes begin as soon as the layer-wise design is final. Depending upn the size of the package, each layer design is first repeated into an array to create a design for each layer of the 4 4 tile. Alignment of individual circuit / package is crosschecked carefully. The layer-wise design of each tile, is now separated into punching, via filling and screen printing files. Each screen and stencil and via punching file is added with alignment marks. Appropriate cut marks are placed at this stage on the top layer for tile isolation and singulation of packages. This usually ends the design generation process. The screens and stencils are then fabrication through a regular vendor. After receipt of all required consumables, the fabrication of the circuits / packages is takenup. The user is kept apprised of the developments, and his approval is obtained at appropriate levels. The Green Tape boundary, 4 x 4 tile area, cutting / singulation marks and alignment marks etc are illustrated in Figure P age

21 Figure 2.3.1: Illustration of cutting marks, alignment marks area, 4 x 4 tile area and 6 x 6 Green Tape Many-a-times, the packages have big cavities. In theory, the programmable punching machine available at C-MET should be able to handle any such cavity fabrication. However, in practice, this is possible only if the cavities are small, and less in number over the tile. Here it may be noted that the tape is held by vacuum along its periphery while punching. Therefore, cavity creation during this process may cause sagging of the tape, in turn causing mis-placed punching. Unfortunately, it is not possible to define the maximum cavity area that can be safely created by programmable punching. Apart from the total punched out area, this also depends upon its distribution, tape thickness and die-punch quality. However, C-MET engineers may be able to provide feedback when the design is available, so that appropriate action can be taken by the user. For cases where large size punched out area over the tile is inevitable, C-MET carries out the work by preparing individual die-punch pairs for each punched out layer. This process has its own limitations, such as, limited shapes, lower limit on distance between cavities as well as the cavity size in the range of 3-5mm, reduced alignment accuracy 19 P age

22 and much higher cost. Nevertheless, this method at least allows fabrications of such packages. The process of creating such cavities begins after design of each layer of the tile is finalized. Additional alignment marks are added, and the cavity design is separated, just as the via punching, stencil and screen printing designs for each layer are separated out. A set of die punches are then ordered from a standard vendor. These sets are put through rigorous testing and validation; mostly with respect to the placement, size and shape as well as the quality of the punched cavity. This punching is carried out using a hydraulic power press with utmost care with respect to cleanliness. Typical punch designs for two different layers prepared for die-punching fabrication are shown in Figure Incidentally, these die-punch sets were prepared for the same package shown in Figure and Figure Figure 2.3.2: Examples of designs for die-punch sets for two different layers for the package show in Figure and The flowcharts in Figure present the steps in fabrication of LTCC packages / circuits for EL1 and EL2. 20 P age

23 User entry level 1 Receipt Design/ Circuit /artwork Concept Design for Multilayer LTCC Correction Does Discrepancy exist? YES Inform Customer NO Design as per design rule Correction YES Does Discrepancy exist? Inform Customer NO Convert the package design into 4 X4 tile area Prepare punch, screen and stencil files and fabricate screens and stencils Take-up Fabrication (a) 21 P age

24 User entry level 2 Receipt of Design as per design rule Perform DRC Correction YES Does Discrepancy exist in DRC? Inform Customer NO Convert the package design into 4 X4 area Prepare punch, screen and stencil files and fabricate screens and stencils Sent for fabrication (b) Figure 2.3.3: The process steps for design implementation, for (a) User entry level 1 (EL1), and (b) User entry level 2 (EL2). 22 P age

25 Annexure I Series 951 Green Tape Materials List from DuPont Description Gold System Silver System Mixed Metal System Internal or External Conductor Signal Lines 5734 Au 6142D Ag 6142D Ag Signal Lines 5742 Au 6145 Ag 6145 Ag Signal Lines 6742 Ag Signal Lines 6158 Ag (EU Product) Ground Planes 5731 Au 6148 Ag 6148 Ag Ground Planes 6158 Ag (EU Product) Capacitor Electrodes 6142D Ag 6142D Ag Via conductor Via fill 5738 Au 6141 Ag 7824 Pt/Ag Via Fill (951C2) 6151 Ag 7825 Pt/Ag Outer via 6138 Pd/Ag 6138 Pd/Ag 6XX3 Pt/Ag Cover Pad (Solderable for TC) Wire-Bondable and Solderable Conductor Co-fired Au Wire Bonding 5734 Au 5731 Au Au Wire Bonding 5731 Au Au Wire Bonding 5742 Au 5742 Au Thin Al Wire Bonding 5742 Au 5743 Au Thin Al Wire Bonding 6146 Pd/Ag Heavy Al Wire Bonding Solderable 5739 Au 6146 Pd/Ag 6146Pd/Ag Platable Cofired Conductor (Ni/Au Plating) Solderable, Wirebondable 6154 Ag 6116 Ag/ Pt Ni/Au Plateable Wire-Bondable and Solderable Conductor - Post-fired Au Wire Bonding 5743A Au 5743A Au (EU Product) (EU Product) Au Wire Bonding 5715 Au 5715 Au Thin Al Wire Bonding 5743A Au (EU Product) 5743A Au (EU Product) 23 P age

26 Thin Al Wire Bonding 5725 Au 5725 Au Heavy Al Wire Bonding 5743A Au (EU Product) 5743A Au (EU Product) Heavy Al Wire Bonding 5725 Au 5725 Au Solderable 4596 Pt/Pd/Au 6177T Pd/Ag 6177T Pd/Ag Solderable 6143 Pd/Ag 6143 Pd/Ag Brazing Adhesion Layer 5062D D Barrier Layer 5063D D Braze Alloy Resistors Post Fired 7200 Series 7200 Series 7200 Series QT-80 Series (EU Product) QT-80 Series (EU Product) QT-80 Series (EU Product) Co-fired CF0XX Series CF0XX Series CF0XX Series Capacitors Tape Layer as capacitor C2 tape C2 tape C2 tape Co-fired Paste (K60) 5674,5674N 5674,5674N 5674,5674N Overglaze Post fired 500C QQ550 QQ550 QQ550 Co-fired P age