WEI HUANG Curriculum Vitae
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1 1 WEI HUANG Curriculum Vitae 4025 Duval Road, Apt 2538 Phone: (434) Austin, TX (preferred) PARTICULARS Areas of Interest Inspired by my experience as a researcher at IBM Austin Research Lab, I am interested in power-aware techniques at the hardware, firmware and OS levels and architecture design for processors, large-scale computing as well as mobile computing. In particular, I am currently interested in exploring the interactions across the system hardware stack including chips, servers, data centers and buildings and identifying opportunities to improve performance and energy efficiency, with awareness of physical constraints such as energy, power delivery, temperature and reliability. Education University of Virginia Charlottesville, VA Ph. D. in Electrical Engineering January 2007 University of Science and Technology of China Hefei, China Bachelor of Engineering, Dept. of Automation June 1998 Dissertation Title: HotSpot A Chip and Package Compact Thermal Modeling Methodology for VLSI Design. Advisors: Prof. Mircea Stan (EE), Prof. Kevin Skadron (CS) Current Status Citizen of China; US permanent resident AWARDS Best Paper Award at International Green Computing Conference (IGCC), First Place Winner (Phase One) and Second Place Winner (Phase Two) in the System-on-Chip (SoC) Design Challenge sponsored by the Semiconductor Research Corporation (SRC), Best Student Paper Award at International Symposium on Computer Architecture (ISCA), Honorable Mention at 40th ISSCC/DAC Student Design Contest, OTHER ACCOMPLISHMENTS To date, HotSpot thermal modeling tool, of which I have been the lead developer, has been downloaded over 3000 times. My research papers have been cited about 1800 times according to Google Scholar.
2 Wei Huang 2 EMPLOYMENT / EXPERIENCES 01/2010-present. Researcher, IBM Austin Research Lab. Performance, power and thermal analysis and management for IBM POWER7 processor and POWER7- based server platforms; IBM System-z power management; Developing power-aware features for future IBM processors and server platforms; System, chip and core-level power modeling; Energy-efficient data center design. Across-stack system design considerations among chips, servers/mobile devices, and data centers. 01/ /2009. Researcher, Department of Computer Science, University of Virginia. Enhance HotSpot and HotLeakage to industry-strength tools; Temperature-aware manycore architecture; Analysis on thermal/power IR-imaging characterization technique. (08/ /2009) Visited Prof. Mark Horowitz s group at Stanford University for potential collaboration. 09/ /2006. Graduate Research Assistant, Department of Electrical and Computer Engineering, University of Virginia. Temperature-aware architecture research; Develop HotSpot thermal modeling tool; VLSI design (SoC for ultrasound imaging; analog Turbo decoder; on-chip inductor design and characterization); Reliability-aware design to reclaim performance margin; Thermal characterization of industry processors (IBM and NVidia). 06/ /2004. Research Intern, IBM T. J. Watson Research Center. IBM processor leakage and thermal characterization and analysis. 07/ /2001. Hardware Design Engineer, Alcatel China (now Alcatel-Lucent China). Hardware and firmware design and debug for access servers connecting PSTN and Internet; System-level integration for Internet access servers. PROFESSIONAL ACTIVITIES Program committee member, IEEE/ACM Design, Automation and Test in Europe (DATE) Program committee member, IEEE International Conference on Networking, Architecture and Storage (NAS) Keynote Speaker at Workshop on Thermal Modeling and Management (TEMM), in conjunction with International Green Computing Conference (IGCC) Invited talk to the Microprocessor and Memory Architecture Technology Community (MMTC) of IBM System and Technology Group (STG), broadcast to IBM employees world wide, Tutorial at IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Tutorial at IEEE International Symposium on Workload Characterization (IISWC) Web and Registration chair, IEEE International Symposium on Workload Characterization (IISWC) Session chair, International Green Computing Conference (IGCC) Reviews (>150 papers) for top conferences and journals.
3 Wei Huang 3 PATENTS 2 patent applications filed for IBM in patent applications filed for IBM in patent applications filed for IBM in PAPERS K. Sudan, K. Rajamani, W. Huang, J. B. Carter, Tiered Memory: An Iso-Power Memory Architecture to Address the Memory Power Wall, under minor revisions to IEEE Trans. on Computers K. Sankaranarayanan, B. H. Meyer, W. Huang, R. J. Ribando, H. Haj-Hajiri, M. R. Stan, and K. Skadron, Architectural Implications of Spatial Thermal Filtering., Elsevier Integration, the VLSI Joural (to appear), W. Huang, K. Rajamani, M. R. Stan and K. Skadron, Scaling with Design Constraints: Predicting the Future of Big Chips, IEEE Micro, Special Issue on Big Chips. July/Aug, W. Huang, M. Allen-Ware, J. B. Carter, E. Elnozahy, H. Hamann, T. Keller, C. Lefurgy, J. Li, K. Rajamani, J. Rubio, TAPO: Thermal-Aware Power Optimization Techniques for Servers and Data Centers. Best Paper Award. International Green Computing Conference (IGCC), Wei Huang, Malcolm Allen-Ware, John B. Carter, Edmund Cheng, Kevin Skadron, Mircea Stan, Temperature- Aware Architecture: Lessons and Opportunities. IEEE Micro, May/June, J. Li, W. Huang, L. Zhang, C. Lefurgy, W. Denzel, R. Treumann, K. Wang, Power Shifting in Thrifty Interconnection Network. International Symposium on High-Performance Computer Architecture (HPCA), K. Skadron, M. R. Stan, W. Huang, Thermal Modeling for Processors and Systems-on-Chip (book chapter, ISBN: ). Processor and System-on-Chip Simulation. Eds. O. Temam and R. Leupers, Springer Inc., Z. Qi, B. H. Meyer, W. Huang, R. J. Ribando, K. Skadron, M. R. Stan, Temperature-to-Power Mapping. International Conference on Computer Design (ICCD), W. Huang, M. R. Stan, S. Gurumurthi, R. J. Ribando, and K. Skadron, Interaction of Scaling Trends in Processor Architecture and Cooling. IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm), W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan, Exploring the Thermal Impact on Manycore Processor Performance. IEEE Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm), W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan, Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2009.
4 Wei Huang W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan, Accurate, Pre-RTL Temperature- Aware Processor Design Using a Parameterized, Geometric Thermal Model, IEEE Transactions on Computers (TCOMP), September, W. Huang, M. Stan, K. Sankaranarayanan, R. Ribando and K. Skadron. Many-Core Design from a Thermal Perspective, Design Automation Conference (DAC), June W. Huang, K. Sankaranarayanan, R. Ribando, M. Stan, K. Skadron. An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations, WDDD workshop held in conjunction with International Symposium on Computer Architecture (ISCA), June Z. Lu, W. Huang, K. Skadron, J. Lach and M. R. Stan. Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications, IEEE Transactions on Very Large-Scale Integrated Circuits (TVLSI), February, Z. Qi, W. Huang, A. Cabe, W Wu, Y Zhang, G. Rose, M. R. Stan. A Design Methodology for a Low-Power, Temperature-Aware SOC Developed for Medical Image Processors, IEEE International System-On-Chip Conference (SOCC), Sept W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron and M. R. Stan. HotSpot: Thermal Modeling for CMOS VLSI Systems, IEEE Transactions on Very Large-Scale Integrated Circuits (TVLSI), May W. Huang, M. R. Stan and K. Skadron. Parameterized Physical Compact Thermal Modeling, IEEE Transactions on Component and Packaging Technologies (TCAPT), December, W. Huang, E. Humenay, K. Skadron and M. Stan. The Need for a Full-Chip and Package Thermal Model for Thermally Optimized IC Designs. Intl. Symp. on Low Power Electronic Design (ISLPED), August S. Velusamy, W. Huang, John Lach, Mircea R. Stan, Kevin Skadron, Monitoring temperature in FPGA based SoCs International Conference on Computer Design (ICCD), Oct K.-J. Lee, K. Skadron and W. Huang. Analytical model for sensor placement on microprocessors International Conference on Computer Design (ICCD), Oct S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. Experiences using FPGAs for Temperature- Aware Microarchitecture Research. Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, D. Tarjan, Temperature-Aware Microarchitecture: modeling and implementation, ACM Transactions on Architecture and Code Optimization (TACO), March Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron. Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design. International Conference on Computer Aided Design (ICCAD), November W. Huang, M. R. Stan, and K. Skadron. Physically-Based Compact Thermal Modeling -Achieving Parameterization and Boundary Condition Independence. International Workshop on Thermal Investigations of ICs (THERMINIC), Sept
5 Wei Huang W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact Thermal Modeling for Temperature-Aware Design. Design Automation Conference (DAC), June K. Skadron, M.R. Stan, W. Huang, K. Sankaranarayanan, Z. Lu, and J. Lach. The Need for a Computer- Architecture Approach to Thermal Management in Computer Systems. IEEE International Conference on Thermal, Mechanical and Thermo-Mechanical Simulation and Experiments in Micro-electronics and Microsystems (EuroSimE), May (Keynote presentation within session.) K Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware computer systems: opportunities and challenges, IEEE Micro Magazine, Nov-Dec M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, S. Velusamy, HotSpot: a Dynamic Compact Thermal Model at the Processor-Architecture Level, Microelectronics Journal, June K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-Aware Microarchitecture. International Symposium on Computer Architecture (ISCA), June (Best Student Paper Award) K. Skadron, M. Stan, M. Barcella, A. Dwarka, W. Huang, Y. Li, Y. Ma, A. Naidu, D. Parikh, P. Re, G. Rose, K. Sankaranarayanan, R. Suryanarayan, S. Velusamy, H. Zhang, Y. Zhang. HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level. International Workshop on Thermal Investigations of ICs (THERMINIC), Sept REFERENCES References are available upon request.
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