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1 Mingyu Gao Gates Hall Phone: +1(650) Serra Mall, Room Stanford, CA, mgao12 Research Interests Computer architecture and systems with emphasis on systems for data-intensive applications including deep learning and graph analytics. Specifically, I designed scalable and efficient Near-Data Processing systems for such applications. My research developed a coherent set of hardware and software techniques that address key challenges including practical support for common programming models, efficient reconfigurable substrates, memory dataflow optimizations, and domain-specific acceleration for deep neural networks. Education Sep Jun Ph.D. in Electrical Engineering (expected) Stanford, CA Stanford University Advisor: Prof. Christos Kozyrakis Dissertation: Scalable Near-Data Processing Systems for Data-Intensive Applications Sep Jun M.Sc. in Electrical Engineering Stanford University GPA: 4.175/4.3 Aug Jul Bachelor of Science in Microelectronics Tsinghua University Ranking: 1/57 Selected Awards and Honors Stanford, CA Beijing, China IEEE Micro s Top Picks from the Computer Architecture Conferences for paper DRAF: A Low-Power DRAM- Based Reconfigurable Acceleration Fabric 2017 HiPEAC Paper Award for TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory 2017 HiPEAC Paper Award for DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric 2016 HiPEAC Paper Award for HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing 2016 Outstanding Graduate of Tsinghua University, 67/ Outstanding College Graduate in Beijing City 2012 Excellent Undergraduate Thesis of Tsinghua University 2012 National Scholarship of China (twice) 2009 &

2 Meritorious Reward in Mathematical Contest in Modeling (MCM 2011) 2011 Golden Medal in the 9th Asian Physics Olympiad 2008 Golden Medal in the 24th Chinese Physics Olympiad 2007 Conference Papers Mingxing Zhang, Youwei Zhuo, Chao Wang, Mingyu Gao, Yongwei Wu, Kang Chen, Christos Kozyrakis, and Xuehai Qian. GraphP: Reducing Communication of PIM-based Graph Processing with Efficient Data Partition. In Proceeding of the 24th IEEE Symposium on High Performance Computer Architecture (HPCA), Feb 2018 William Hwang, Mohamed M. Sabry Aly, Yash H. Malviya, Mingyu Gao, Tony F. Wu, Christos Kozyrakis, H.-S. Philip Wong, and Subhasish Mitra. 3D Nanosystems Enable Embedded Abundant-Data Computing. In Proceeding of the 12th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2017 Mingyu Gao, Jing Pu, Xuan Yang, Mark Horowitz, and Christos Kozyrakis. TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory. In Proceeding of the 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Apr 2017 Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, and Christos Kozyrakis. DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. In Proceeding of the 43rd International Symposium on Computer Architecture (ISCA), Jun 2016 Mingyu Gao and Christos Kozyrakis. HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing. In Proceeding of the 22nd IEEE Symposium on High Performance Computer Architecture (HPCA), Mar 2016 Mingyu Gao, Grant Ayers, and Christos Kozyrakis. Practical Near-Data Processing for In-memory Analytics Frameworks. In Proceeding of the 24th International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct 2015 Journal Papers Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, and Christos Kozyrakis. DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. IEEE Micro, 37(3):70 78, 2017 Mohamed M. Sabry Aly, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeff Bokor, Franz Franchetti, Kenneth E. Goodson, Christos Kozyrakis, Igor Markov, Kunle Olukotun, Larry Pileggi, Eric Pop, Jan Rabaey, Christopher Re, H.-S. Philip Wong, and Subhasish Mitra. Energy-Efficient Abundant-Data Computing: The N3XT 1,000x. Computer, 48(12):24 33,

3 Patents Mingyu Gao, Hongzhong Zheng, Krishna T. Malladi, and Robert Brennan. Reconfigurable Logic Architecture, Feb US Patent 9,577,644 Mingyu Gao, Hongzhong Zheng, and Krishna T. Malladi. Space-Multiplexing DRAM-Based Reconfigurable Logic, Nov US Patent 9,503,095 Research Experience Sep Present Research Assistant, Computer Systems Lab, Stanford University, Stanford, CA Advisor: Prof. Christos Kozyrakis Working on scalable and efficient memory systems for data-intensive applications such as deep learning and graph analytics Jun Sep Research Intern, Memory Solution Lab, Samsung Semiconductor, Inc., San Jose, CA Manager: Dr. Hongzhong Zheng Using commodity DRAM technology to build low-cost, high-density reconfigurable fabric with multi-context technique File three patent applications based on the research results Jun Sep Research Intern, Memory Solution Lab, Samsung Semiconductor, Inc., Milpitas, CA Manager: Dr. Hongzhong Zheng Understanding the opportunities and exploring the design space for next generation memory technology with processing capability Jun Sep Research Associate, Data-Centric Data Center Group, HP Labs, Palo Alto, CA Manager: Dr. Parthasarathy Ranganathan, Dr. Jichuan Chang Identifying performance and energy efficiency bottlenecks in current memory systems and exploring the active memory design space Jul Jun Research Intern, Hardware Computing Group, Microsoft Research Asia, Beijing Manager: Ms. Jing Yan FPGA acceleration for web indexing system based on binary document signatures Mar Jul Research Assistant, Institute of Microelectronics, Tsinghua University, Beijing Advisor: Prof. Yangdong Deng Exploring and simulating memory-execution overlap in GPU with GPGPUSim Teaching Experience Spring 2017 Fall 2016 Guest Lecturer, Stanford University Guest Lecturer and Teaching Assistant, Stanford University CS316 Advanced Multi-Core Systems 3

4 Fall 2016 Spring 2016 Spring 2016 Spring 2014 Student Project Mentor, Stanford University Aditya Mundada, Kushaagra Goyal, Yash Malviya, Hardware Acceleration foreural Networks Training Yangyang Yu, Warner Krause, Olivier Jin, Mapping Convolutional Neural Network Workloads to the Convolution Engine Russell Stewart, Alexander Sosa, Han Ye, Rethinking Architectures for Energy Efficient Analog Computing Teaching Assistant, Stanford University Student Project Mentor, Stanford University Wesson Altoyan, Anthony Pelot, Zelin Zhang, Building Memory-Centric Accelerator for Data-Centric Application using Hybrid Memory Cube Architecture Teaching Assistant, Stanford University Selected Talks Deep Learning Acceleration leveraging 3D Integration Technologies SystemX Fall Conference, Nov TETRIS: Scalable and Efficient Neural Networkcceleration with 3D Memory ASPLOS-22, Apr Stanford Platform Lab Review Meeting, Feb DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric ISCA-43, Jun Practical and Efficient Near-Data Processing for In-Memory Analytics EPFL, Mar HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing HPCA-22, Mar Practical Near-Data Processing for In-Memory Analytics Frameworks PACT-24, Oct Understanding the Challenges and Opportunities of Processing-in-Memory: A Design Space Exploration Samsung, Sep Improving Energy Efficiency with Memory-Side Computing Stanford Pervasive Parallelism Lab Retreat, Jun 2014 Active Memory Opportunities: Data-Centric Compute at Memory HP Labs, Aug

5 Selected Posters TETRIS: Scalable and Efficient Neural Networkcceleration with 3D Memory Stanford Platform Lab Annual Retreat, Jun ASPLOS-22, Apr DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric IAP-Stanford Cloud Workshop, Oct Practical Near-Data Processing for In-Memory Analytics Frameworks Stanford Pervasive Parallelism Lab Retreat, May 2016 DRAM-Based Reconfigurable Logic Samsung, Jul Understanding the Challenges and Opportunities of Processing-in-Memory: A Design Space Exploration Samsung, Aug Reevaluating Memory Systems for Energy Efficiency: Bringing Computation and Data Closer Stanford Pervasive Parallelism Lab Retreat, Jan 2014 Stanford Computer Forum Poster Session, Apr Active Memory Opportunities: Data-Centric Compute at Memory HP Labs, Jul Press The Next Platform, Stanford s TETRIS Clears Blocks for 3D Memory Based Deep Learning, Nicole Hemsoth, Mar Academic Service Reviewer for IEEE Computer Architecture Letters (CAL) Reviewer for IEEE Micro Reviewer for ACM Transactions on Architecture and Code Optimization (TACO) Member of IEEE, 2015 to present 5

Address: 9110 Judicial Dr., Apt. 8308, San Diego, CA Phone: (240) URL:

Yongle Wu CONTACT INFORMATION Address: 9110 Judicial Dr., Apt. 8308, San Diego, CA 92122 Phone: (240)678-6461 Email: wuyongle@gmail.com URL: http://www.cspl.umd.edu/yongle/ EDUCATION University of Maryland,